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watch library: implement UART

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This commit is contained in:
Joey Castillo
2022-01-26 19:31:49 -05:00
parent 71ea3b9de9
commit 0c78fdf535
5 changed files with 150 additions and 40 deletions
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3
watch-library/hardware/hw/driver_init.h
View File

@@ -33,6 +33,7 @@ extern "C" {
#include <hal_ext_irq.h>
#include <hal_i2c_m_sync.h>
#include <hal_spi_m_sync.h>
#include <hal_usart_sync.h>
#include <hal_delay.h>
#include <hal_slcd_sync.h>
@@ -40,6 +41,8 @@ extern struct adc_sync_descriptor ADC_0;
extern struct i2c_m_sync_desc I2C_0;
extern struct usart_sync_descriptor USART_0;
extern struct slcd_sync_descriptor SEGMENT_LCD_0;
void I2C_0_CLOCK_init(void);

98
watch-library/hardware/watch/watch_uart.c
View File

@@ -22,6 +22,103 @@
* SOFTWARE.
*/
#include "watch_uart.h"
#include <string.h>
struct usart_sync_descriptor USART_0;
struct io_descriptor *uart_io;
void watch_enable_uart(const uint8_t tx_pin, const uint8_t rx_pin, uint32_t baud) {
SERCOM_USART_CTRLA_Type ctrla;
SERCOM_USART_CTRLB_Type ctrlb;
ctrla.reg = SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE(1);
ctrlb.reg = SERCOM_USART_CTRLB_CHSIZE(0);
MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3;
GCLK->PCHCTRL[SERCOM3_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN(0) | GCLK_PCHCTRL_CHEN;
while (0 == (GCLK->PCHCTRL[SERCOM3_GCLK_ID_CORE].reg & GCLK_PCHCTRL_CHEN)) {
// wait
}
usart_sync_init(&USART_0, SERCOM3, (void *)NULL);
SERCOM3->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
switch (tx_pin) {
case A2:
gpio_set_pin_direction(tx_pin, GPIO_DIRECTION_OUT);
gpio_set_pin_function(tx_pin, PINMUX_PB02C_SERCOM3_PAD0);
ctrla.reg |= SERCOM_USART_CTRLA_TXPO(0);
ctrlb.reg |= SERCOM_USART_CTRLB_TXEN;
break;
case A4:
gpio_set_pin_direction(tx_pin, GPIO_DIRECTION_OUT);
gpio_set_pin_function(tx_pin, PINMUX_PB00C_SERCOM3_PAD2);
ctrla.reg |= SERCOM_USART_CTRLA_TXPO(1);
ctrlb.reg |= SERCOM_USART_CTRLB_TXEN;
break;
default:
break;
}
switch (rx_pin) {
case A1:
gpio_set_pin_direction(rx_pin, GPIO_DIRECTION_IN);
gpio_set_pin_function(rx_pin, PINMUX_PB01C_SERCOM3_PAD3);
ctrla.reg |= SERCOM_USART_CTRLA_RXPO(3);
ctrlb.reg |= SERCOM_USART_CTRLB_RXEN;
break;
case A2:
gpio_set_pin_direction(rx_pin, GPIO_DIRECTION_IN);
gpio_set_pin_function(rx_pin, PINMUX_PB02C_SERCOM3_PAD0);
ctrla.reg |= SERCOM_USART_CTRLA_RXPO(0);
ctrlb.reg |= SERCOM_USART_CTRLB_RXEN;
break;
case A3:
gpio_set_pin_direction(rx_pin, GPIO_DIRECTION_IN);
gpio_set_pin_function(rx_pin, PINMUX_PB03C_SERCOM3_PAD1);
ctrla.reg |= SERCOM_USART_CTRLA_RXPO(1);
ctrlb.reg |= SERCOM_USART_CTRLB_RXEN;
break;
case A4:
gpio_set_pin_direction(rx_pin, GPIO_DIRECTION_IN);
gpio_set_pin_function(rx_pin, PINMUX_PB00C_SERCOM3_PAD2);
ctrla.reg |= SERCOM_USART_CTRLA_RXPO(2);
ctrlb.reg |= SERCOM_USART_CTRLB_RXEN;
break;
default:
break;
}
SERCOM3->USART.CTRLA.reg = ctrla.reg;
SERCOM3->USART.CTRLB.reg = ctrlb.reg;
if (hri_usbdevice_get_CTRLA_ENABLE_bit(USB)) {
uint64_t br = 65536 - ((65536 * 16.0f * baud) / 8000000);
SERCOM3->USART.BAUD.reg = (uint16_t)br;
} else {
uint64_t br = 65536 - ((65536 * 16.0f * baud) / 4000000);
SERCOM3->USART.BAUD.reg = (uint16_t)br;
}
SERCOM3->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
usart_sync_enable(&USART_0);
usart_sync_get_io_descriptor(&USART_0, &uart_io);
}
void watch_uart_puts(char *s) {
io_write(uart_io, (uint8_t *)s, strlen(s));
}
char watch_uart_getc(void) {
uint8_t retval;
io_read(uart_io, &retval, 1);
return retval;
}
// Begin deprecated functions
/*
* UART methods are Copyright (c) 2014-2017, Alex Taradov <alex@taradov.com>
* All rights reserved.
@@ -50,7 +147,6 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "watch_uart.h"
#include "peripheral_clk_config.h"
void watch_enable_debug_uart(uint32_t baud) {