diff --git a/Sensor Watch Starter Project/astudio/demo.atsln b/Sensor Watch Starter Project/astudio/demo.atsln new file mode 100755 index 00000000..f9190a2d --- /dev/null +++ b/Sensor Watch Starter Project/astudio/demo.atsln @@ -0,0 +1,17 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# Atmel Studio Solution File, Format Version 11.00 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "demo", "demo.cproj", "{22CBC4AC-0DB7-F32F-F866-38AB515616EC}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Release|ARM = Release|ARM + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {22CBC4AC-0DB7-F32F-F866-38AB515616EC}.Release|ARM.ActiveCfg = Release|ARM + {22CBC4AC-0DB7-F32F-F866-38AB515616EC}.Release|ARM.Build.0 = Release|ARM + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/Sensor Watch Starter Project/astudio/demo.cproj b/Sensor Watch Starter Project/astudio/demo.cproj new file mode 100755 index 00000000..189359b9 --- /dev/null +++ b/Sensor Watch Starter Project/astudio/demo.cproj @@ -0,0 +1,496 @@ + + + + 2.0 + 7.0 + com.Atmel.ARMGCC.C + {22CBC4AC-0DB7-F32F-F866-38AB515616EC} + ATSAML22N18A + none + Executable + C + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + Demo + Demo + Demo + Native + true + false + true + true + 0x20000000 + + exception_table + 2 + 0 + + + + + + + + + + + + + com.atmel.avrdbg.tool.edbg + SWD + + + + false + 2000000 + + SWD + + com.atmel.avrdbg.tool.edbg + ATML2241030200000619 + EDBG + + true + ATML2241030200000619 + 0x10810000 + 2000000 + + + + 2000000 + + SWD + + com.atmel.avrdbg.tool.atmelice + J41800003910 + Atmel-ICE + + + + + + True + False + False + True + False + True + True + + + __SAML22N18A__ + DONT_USE_CMSIS_INIT + F_CPU=16000000 + + + + + ../../include + ../.. + + + Optimize for size (-Os) + True + True + False + Maximum (-g3) + True + False + + + %24(ProjectDir)\Device_Startup + + + True + + -Wl,--script=../../linker/saml22n18.ld + + + ../../include + ../.. + + + + + Demo + .elf + + + + compile + include\component\ac.h + + + compile + include\component\adc.h + + + compile + include\component\aes.h + + + compile + include\component\ccl.h + + + compile + include\component\dmac.h + + + compile + include\component\dsu.h + + + compile + include\component\eic.h + + + compile + include\component\evsys.h + + + compile + include\component\freqm.h + + + compile + include\component\gclk.h + + + compile + include\component\mclk.h + + + compile + include\component\mtb.h + + + compile + include\component\nvmctrl.h + + + compile + include\component\osc32kctrl.h + + + compile + include\component\oscctrl.h + + + compile + include\component\pac.h + + + compile + include\component\pm.h + + + compile + include\component\port.h + + + compile + include\component\rstc.h + + + compile + include\component\rtc.h + + + compile + include\component\sercom.h + + + compile + include\component\slcd.h + + + compile + include\component\supc.h + + + compile + include\component\tal.h + + + compile + include\component\tc.h + + + compile + include\component\tcc.h + + + compile + include\component\trng.h + + + compile + include\component\usb.h + + + compile + include\component\wdt.h + + + compile + include\instance\ac.h + + + compile + include\instance\adc.h + + + compile + include\instance\aes.h + + + compile + include\instance\ccl.h + + + compile + include\instance\dmac.h + + + compile + include\instance\dsu.h + + + compile + include\instance\eic.h + + + compile + include\instance\evsys.h + + + compile + include\instance\freqm.h + + + compile + include\instance\gclk.h + + + compile + include\instance\mclk.h + + + compile + include\instance\mtb.h + + + compile + include\instance\nvmctrl.h + + + compile + include\instance\osc32kctrl.h + + + compile + include\instance\oscctrl.h + + + compile + include\instance\pac.h + + + compile + include\instance\pm.h + + + compile + include\instance\port.h + + + compile + include\instance\rstc.h + + + compile + include\instance\rtc.h + + + compile + include\instance\sercom0.h + + + compile + include\instance\sercom1.h + + + compile + include\instance\sercom2.h + + + compile + include\instance\sercom3.h + + + compile + include\instance\sercom4.h + + + compile + include\instance\sercom5.h + + + compile + include\instance\slcd.h + + + compile + include\instance\supc.h + + + compile + include\instance\tal.h + + + compile + include\instance\tc0.h + + + compile + include\instance\tc1.h + + + compile + include\instance\tc2.h + + + compile + include\instance\tc3.h + + + compile + include\instance\tcc0.h + + + compile + include\instance\trng.h + + + compile + include\instance\usb.h + + + compile + include\instance\wdt.h + + + compile + include\pio\saml22g16a.h + + + compile + include\pio\saml22g17a.h + + + compile + include\pio\saml22g18a.h + + + compile + include\pio\saml22j16a.h + + + compile + include\pio\saml22j17a.h + + + compile + include\pio\saml22j18a.h + + + compile + include\pio\saml22n16a.h + + + compile + include\pio\saml22n17a.h + + + compile + include\pio\saml22n18a.h + + + compile + include\core_cm0plus.h + + + compile + include\core_cmFunc.h + + + compile + include\core_cmInstr.h + + + compile + include\q + + + compile + include\saml22.h + + + compile + include\saml22g16a.h + + + compile + include\saml22g17a.h + + + compile + include\saml22g18a.h + + + compile + include\saml22j16a.h + + + compile + include\saml22j17a.h + + + compile + include\saml22j18a.h + + + compile + include\saml22n16a.h + + + compile + include\saml22n17a.h + + + compile + include\saml22n18a.h + + + compile + startup_saml22.c + + + compile + main.c + + + compile + hal_gpio.h + + + + + + + + + + \ No newline at end of file diff --git a/Sensor Watch Starter Project/hal_gpio.h b/Sensor Watch Starter Project/hal_gpio.h new file mode 100755 index 00000000..821a7a9b --- /dev/null +++ b/Sensor Watch Starter Project/hal_gpio.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2014-2016, Alex Taradov + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _HAL_GPIO_H_ +#define _HAL_GPIO_H_ + +/*- Definitions -------------------------------------------------------------*/ +#define HAL_GPIO_PORTA 0 +#define HAL_GPIO_PORTB 1 +#define HAL_GPIO_PORTC 2 + +#define HAL_GPIO_PMUX_A 0 +#define HAL_GPIO_PMUX_B 1 +#define HAL_GPIO_PMUX_C 2 +#define HAL_GPIO_PMUX_D 3 +#define HAL_GPIO_PMUX_E 4 +#define HAL_GPIO_PMUX_F 5 +#define HAL_GPIO_PMUX_G 6 +#define HAL_GPIO_PMUX_H 7 +#define HAL_GPIO_PMUX_I 8 + +#define HAL_GPIO_PIN(name, port, pin) \ + static inline void HAL_GPIO_##name##_set(void) \ + { \ + PORT->Group[HAL_GPIO_PORT##port].OUTSET.reg = (1 << pin); \ + (void)HAL_GPIO_##name##_set; \ + } \ + \ + static inline void HAL_GPIO_##name##_clr(void) \ + { \ + PORT->Group[HAL_GPIO_PORT##port].OUTCLR.reg = (1 << pin); \ + (void)HAL_GPIO_##name##_clr; \ + } \ + \ + static inline void HAL_GPIO_##name##_toggle(void) \ + { \ + PORT->Group[HAL_GPIO_PORT##port].OUTTGL.reg = (1 << pin); \ + (void)HAL_GPIO_##name##_toggle; \ + } \ + \ + static inline void HAL_GPIO_##name##_write(int value) \ + { \ + if (value) \ + PORT->Group[HAL_GPIO_PORT##port].OUTSET.reg = (1 << pin); \ + else \ + PORT->Group[HAL_GPIO_PORT##port].OUTCLR.reg = (1 << pin); \ + (void)HAL_GPIO_##name##_write; \ + } \ + \ + static inline void HAL_GPIO_##name##_in(void) \ + { \ + PORT->Group[HAL_GPIO_PORT##port].DIRCLR.reg = (1 << pin); \ + PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_INEN; \ + PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg &= ~PORT_PINCFG_PULLEN; \ + (void)HAL_GPIO_##name##_in; \ + } \ + \ + static inline void HAL_GPIO_##name##_out(void) \ + { \ + PORT->Group[HAL_GPIO_PORT##port].DIRSET.reg = (1 << pin); \ + PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_INEN; \ + (void)HAL_GPIO_##name##_out; \ + } \ + \ + static inline void HAL_GPIO_##name##_pullup(void) \ + { \ + PORT->Group[HAL_GPIO_PORT##port].OUTSET.reg = (1 << pin); \ + PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_PULLEN; \ + (void)HAL_GPIO_##name##_pullup; \ + } \ + \ + static inline int HAL_GPIO_##name##_read(void) \ + { \ + return (PORT->Group[HAL_GPIO_PORT##port].IN.reg & (1 << pin)) != 0; \ + (void)HAL_GPIO_##name##_read; \ + } \ + \ + static inline int HAL_GPIO_##name##_state(void) \ + { \ + return (PORT->Group[HAL_GPIO_PORT##port].DIR.reg & (1 << pin)) != 0; \ + (void)HAL_GPIO_##name##_state; \ + } \ + \ + static inline void HAL_GPIO_##name##_pmuxen(int mux) \ + { \ + PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_PMUXEN; \ + if (pin & 1) \ + PORT->Group[HAL_GPIO_PORT##port].PMUX[pin>>1].bit.PMUXO = mux; \ + else \ + PORT->Group[HAL_GPIO_PORT##port].PMUX[pin>>1].bit.PMUXE = mux; \ + (void)HAL_GPIO_##name##_pmuxen; \ + } \ + \ + static inline void HAL_GPIO_##name##_pmuxdis(void) \ + { \ + PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg &= ~PORT_PINCFG_PMUXEN; \ + (void)HAL_GPIO_##name##_pmuxdis; \ + } \ + +#endif // _HAL_GPIO_H_ + diff --git a/Sensor Watch Starter Project/include/component/ac.h b/Sensor Watch Starter Project/include/component/ac.h new file mode 100755 index 00000000..9d1ad91d --- /dev/null +++ b/Sensor Watch Starter Project/include/component/ac.h @@ -0,0 +1,600 @@ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_AC_COMPONENT_ +#define _SAML22_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAML22_AC Analog Comparators */ +/*@{*/ + +#define AC_U2245 +#define REV_AC 0x101 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK 0x03ul /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ + uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ +#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ +#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI0 (1 << AC_EVCTRL_INVEI0_Pos) +#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI1 (1 << AC_EVCTRL_INVEI1_Pos) +#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (0x3ul << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) +#define AC_EVCTRL_MASK 0x3313ul /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_MASK 0x03ul /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ +#define AC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (AC_DBGCTRL reset_value) Debug Control */ + +#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ +#define AC_DBGCTRL_DBGRUN (0x1ul << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK 0x01ul /**< \brief (AC_DBGCTRL) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ + uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t OUT:2; /*!< bit: 28..29 Output */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ +#define AC_COMPCTRL_RUNSTDBY (0x1ul << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (0x7ul << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val 0x4ul /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_MEDLOW_Val 0x1ul /**< \brief (AC_COMPCTRL) Medium low speed */ +#define AC_COMPCTRL_SPEED_MEDHIGH_Val 0x2ul /**< \brief (AC_COMPCTRL) Medium high speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val 0x3ul /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_MEDLOW (AC_COMPCTRL_SPEED_MEDLOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_MEDHIGH (AC_COMPCTRL_SPEED_MEDHIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYSTEN (0x1ul << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ +#define AC_COMPCTRL_HYST_Msk (0x3ul << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) +#define AC_COMPCTRL_HYST_HYST50_Val 0x0ul /**< \brief (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST70_Val 0x1ul /**< \brief (AC_COMPCTRL) 70mV */ +#define AC_COMPCTRL_HYST_HYST90_Val 0x2ul /**< \brief (AC_COMPCTRL) 90mV */ +#define AC_COMPCTRL_HYST_HYST110_Val 0x3ul /**< \brief (AC_COMPCTRL) 110mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST70 (AC_COMPCTRL_HYST_HYST70_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST90 (AC_COMPCTRL_HYST_HYST90_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST110 (AC_COMPCTRL_HYST_HYST110_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_MASK 0x373BF75Eul /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ + uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ + uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :3; /*!< bit: 0.. 2 Reserved */ + uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} AC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ + +#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ +#define AC_SYNCBUSY_SWRST (0x1ul << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ +#define AC_SYNCBUSY_ENABLE (0x1ul << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ +#define AC_SYNCBUSY_WINCTRL (0x1ul << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL0 (1 << AC_SYNCBUSY_COMPCTRL0_Pos) +#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL1 (1 << AC_SYNCBUSY_COMPCTRL1_Pos) +#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (0x3ul << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) +#define AC_SYNCBUSY_MASK 0x0000001Ful /**< \brief (AC_SYNCBUSY) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ + __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ + RoReg8 Reserved1[0x1]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ + RoReg8 Reserved2[0x2]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved3[0x8]; + __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML22_AC_COMPONENT_ */ diff --git a/Sensor Watch Starter Project/include/component/adc.h b/Sensor Watch Starter Project/include/component/adc.h new file mode 100755 index 00000000..419620d4 --- /dev/null +++ b/Sensor Watch Starter Project/include/component/adc.h @@ -0,0 +1,763 @@ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_ADC_COMPONENT_ +#define _SAML22_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAML22_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2247 +#define REV_ADC 0x210 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :3; /*!< bit: 2.. 4 Reserved */ + uint8_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run During Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ +#define ADC_CTRLA_SLAVEEN (0x1ul << ADC_CTRLA_SLAVEEN_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run During Standby */ +#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ +#define ADC_CTRLA_ONDEMAND (0x1ul << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_MASK 0xE3ul /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE 0x00ul /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */ +#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) +#define ADC_CTRLB_PRESCALER_DIV2_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */ +#define ADC_CTRLB_PRESCALER_DIV4_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ +#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_MASK 0x07ul /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val 0x0ul /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC2_Val 0x5ul /**< \brief (ADC_REFCTRL) VCCANA */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ + uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ + uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ + uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ +#define ADC_EVCTRL_FLUSHEI (0x1ul << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ +#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ +#define ADC_EVCTRL_FLUSHINV (0x1ul << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */ +#define ADC_EVCTRL_STARTINV (0x1ul << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK 0x3Ful /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ +#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ +#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ +#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK 0x07ul /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK 0x07ul /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ +#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ +#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ +#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK 0x07ul /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SEQSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */ +#define ADC_SEQSTATUS_RESETVALUE 0x00ul /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */ + +#define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */ +#define ADC_SEQSTATUS_SEQSTATE_Msk (0x1Ful << ADC_SEQSTATUS_SEQSTATE_Pos) +#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos)) +#define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */ +#define ADC_SEQSTATUS_SEQBUSY (0x1ul << ADC_SEQSTATUS_SEQBUSY_Pos) +#define ADC_SEQSTATUS_MASK 0x9Ful /**< \brief (ADC_SEQSTATUS) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE 0x0000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val 0x1Dul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val 0x1Eul /**< \brief (ADC_INPUTCTRL) CTAT output */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MASK 0x1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :1; /*!< bit: 6 Reserved */ + uint16_t R2R:1; /*!< bit: 7 Rail-to-Rail mode enable */ + uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t DUALSEL:2; /*!< bit: 12..13 Dual Mode Trigger Selection */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */ +#define ADC_CTRLC_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLC reset_value) Control C */ + +#define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */ +#define ADC_CTRLC_DIFFMODE (0x1ul << ADC_CTRLC_DIFFMODE_Pos) +#define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */ +#define ADC_CTRLC_LEFTADJ (0x1ul << ADC_CTRLC_LEFTADJ_Pos) +#define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */ +#define ADC_CTRLC_FREERUN (0x1ul << ADC_CTRLC_FREERUN_Pos) +#define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */ +#define ADC_CTRLC_CORREN (0x1ul << ADC_CTRLC_CORREN_Pos) +#define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */ +#define ADC_CTRLC_RESSEL_Msk (0x3ul << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos)) +#define ADC_CTRLC_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLC) 12-bit result */ +#define ADC_CTRLC_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLC) For averaging mode output */ +#define ADC_CTRLC_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLC) 10-bit result */ +#define ADC_CTRLC_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLC) 8-bit result */ +#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_R2R_Pos 7 /**< \brief (ADC_CTRLC) Rail-to-Rail mode enable */ +#define ADC_CTRLC_R2R (0x1ul << ADC_CTRLC_R2R_Pos) +#define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */ +#define ADC_CTRLC_WINMODE_Msk (0x7ul << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos)) +#define ADC_CTRLC_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_CTRLC) No window mode (default) */ +#define ADC_CTRLC_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_CTRLC) RESULT > WINLT */ +#define ADC_CTRLC_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_CTRLC) RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_DUALSEL_Pos 12 /**< \brief (ADC_CTRLC) Dual Mode Trigger Selection */ +#define ADC_CTRLC_DUALSEL_Msk (0x3ul << ADC_CTRLC_DUALSEL_Pos) +#define ADC_CTRLC_DUALSEL(value) (ADC_CTRLC_DUALSEL_Msk & ((value) << ADC_CTRLC_DUALSEL_Pos)) +#define ADC_CTRLC_DUALSEL_BOTH_Val 0x0ul /**< \brief (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLC_DUALSEL_INTERLEAVE_Val 0x1ul /**< \brief (ADC_CTRLC) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLC_DUALSEL_BOTH (ADC_CTRLC_DUALSEL_BOTH_Val << ADC_CTRLC_DUALSEL_Pos) +#define ADC_CTRLC_DUALSEL_INTERLEAVE (ADC_CTRLC_DUALSEL_INTERLEAVE_Val << ADC_CTRLC_DUALSEL_Pos) +#define ADC_CTRLC_MASK 0x37BFul /**< \brief (ADC_CTRLC) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ +#define ADC_SAMPCTRL_OFFCOMP (0x1ul << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK 0xBFul /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */ + uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */ +#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ +#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */ + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ + uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ + uint16_t INPUTCTRL:1; /*!< bit: 2 INPUTCTRL Synchronization Busy */ + uint16_t CTRLC:1; /*!< bit: 3 CTRLC Synchronization Busy */ + uint16_t AVGCTRL:1; /*!< bit: 4 AVGCTRL Synchronization Busy */ + uint16_t SAMPCTRL:1; /*!< bit: 5 SAMPCTRL Synchronization Busy */ + uint16_t WINLT:1; /*!< bit: 6 WINLT Synchronization Busy */ + uint16_t WINUT:1; /*!< bit: 7 WINUT Synchronization Busy */ + uint16_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */ + uint16_t OFFSETCORR:1; /*!< bit: 9 OFFSETCTRL Synchronization Busy */ + uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE 0x0000ul /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ + +#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ +#define ADC_SYNCBUSY_SWRST (0x1ul << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ +#define ADC_SYNCBUSY_ENABLE (0x1ul << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_INPUTCTRL (0x1ul << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_CTRLC_Pos 3 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */ +#define ADC_SYNCBUSY_CTRLC (0x1ul << ADC_SYNCBUSY_CTRLC_Pos) +#define ADC_SYNCBUSY_AVGCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_AVGCTRL (0x1ul << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_SAMPCTRL (0x1ul << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_WINLT_Pos 6 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */ +#define ADC_SYNCBUSY_WINLT (0x1ul << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINUT_Pos 7 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */ +#define ADC_SYNCBUSY_WINUT (0x1ul << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */ +#define ADC_SYNCBUSY_GAINCORR (0x1ul << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_OFFSETCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_OFFSETCORR (0x1ul << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */ +#define ADC_SYNCBUSY_SWTRIG (0x1ul << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK 0x07FFul /**< \brief (ADC_SYNCBUSY) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */ +#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */ +#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */ +#define ADC_SEQCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */ + +#define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */ +#define ADC_SEQCTRL_SEQEN_Msk (0xFFFFFFFFul << ADC_SEQCTRL_SEQEN_Pos) +#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos)) +#define ADC_SEQCTRL_MASK 0xFFFFFFFFul /**< \brief (ADC_SEQCTRL) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ +#define ADC_CALIB_BIASCOMP_Msk (0x7ul << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ +#define ADC_CALIB_BIASREFBUF_Msk (0x7ul << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_MASK 0x0707ul /**< \brief (ADC_CALIB) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */ + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */ + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */ + __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */ + RoReg8 Reserved1[0x2]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */ + RoReg8 Reserved2[0x3]; + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */ + RoReg8 Reserved3[0x3]; + __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */ + RoReg8 Reserved4[0x2]; + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */ + RoReg8 Reserved5[0x2]; + __IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML22_ADC_COMPONENT_ */ diff --git a/Sensor Watch Starter Project/include/component/aes.h b/Sensor Watch Starter Project/include/component/aes.h new file mode 100755 index 00000000..6704c9cb --- /dev/null +++ b/Sensor Watch Starter Project/include/component/aes.h @@ -0,0 +1,347 @@ +/** + * \file + * + * \brief Component description for AES + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_AES_COMPONENT_ +#define _SAML22_AES_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AES */ +/* ========================================================================== */ +/** \addtogroup SAML22_AES Advanced Encryption Standard */ +/*@{*/ + +#define AES_U2238 +#define REV_AES 0x210 + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ + uint32_t CFBS:3; /*!< bit: 5.. 7 CFB Types */ + uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Keysize */ + uint32_t CIPHER:1; /*!< bit: 10 Cipher mode */ + uint32_t STARTMODE:1; /*!< bit: 11 Start mode */ + uint32_t LOD:1; /*!< bit: 12 LOD Enable */ + uint32_t KEYGEN:1; /*!< bit: 13 Last key generation */ + uint32_t XORKEY:1; /*!< bit: 14 Xor Key operation */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CTYPE:4; /*!< bit: 16..19 Counter measure types */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AES_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ +#define AES_CTRLA_RESETVALUE 0x00000000ul /**< \brief (AES_CTRLA reset_value) Control A */ + +#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ +#define AES_CTRLA_SWRST (0x1ul << AES_CTRLA_SWRST_Pos) +#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ +#define AES_CTRLA_ENABLE (0x1ul << AES_CTRLA_ENABLE_Pos) +#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ +#define AES_CTRLA_AESMODE_Msk (0x7ul << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) +#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) CFB Types */ +#define AES_CTRLA_CFBS_Msk (0x7ul << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) +#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Keysize */ +#define AES_CTRLA_KEYSIZE_Msk (0x3ul << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) +#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher mode */ +#define AES_CTRLA_CIPHER (0x1ul << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start mode */ +#define AES_CTRLA_STARTMODE (0x1ul << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) LOD Enable */ +#define AES_CTRLA_LOD (0x1ul << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last key generation */ +#define AES_CTRLA_KEYGEN (0x1ul << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) Xor Key operation */ +#define AES_CTRLA_XORKEY (0x1ul << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter measure types */ +#define AES_CTRLA_CTYPE_Msk (0xFul << AES_CTRLA_CTYPE_Pos) +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) +#define AES_CTRLA_MASK 0x000F7FFFul /**< \brief (AES_CTRLA) MASK Register */ + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START:1; /*!< bit: 0 Manual Start */ + uint8_t NEWMSG:1; /*!< bit: 1 New message */ + uint8_t EOM:1; /*!< bit: 2 End of message */ + uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ +#define AES_CTRLB_RESETVALUE 0x00ul /**< \brief (AES_CTRLB reset_value) Control B */ + +#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Manual Start */ +#define AES_CTRLB_START (0x1ul << AES_CTRLB_START_Pos) +#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ +#define AES_CTRLB_NEWMSG (0x1ul << AES_CTRLB_NEWMSG_Pos) +#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ +#define AES_CTRLB_EOM (0x1ul << AES_CTRLB_EOM_Pos) +#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ +#define AES_CTRLB_GFMUL (0x1ul << AES_CTRLB_GFMUL_Pos) +#define AES_CTRLB_MASK 0x0Ful /**< \brief (AES_CTRLB) MASK Register */ + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ +#define AES_INTENCLR_RESETVALUE 0x00ul /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete */ +#define AES_INTENCLR_ENCCMP (0x1ul << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_ENCCMP_0_Val 0x0ul /**< \brief (AES_INTENCLR) 1 (no division) */ +#define AES_INTENCLR_ENCCMP_1_Val 0x1ul /**< \brief (AES_INTENCLR) 2 */ +#define AES_INTENCLR_ENCCMP_2_Val 0x2ul /**< \brief (AES_INTENCLR) 4 */ +#define AES_INTENCLR_ENCCMP_3_Val 0x3ul /**< \brief (AES_INTENCLR) 8 */ +#define AES_INTENCLR_ENCCMP_0 (AES_INTENCLR_ENCCMP_0_Val << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_ENCCMP_1 (AES_INTENCLR_ENCCMP_1_Val << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_ENCCMP_2 (AES_INTENCLR_ENCCMP_2_Val << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_ENCCMP_3 (AES_INTENCLR_ENCCMP_3_Val << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete */ +#define AES_INTENCLR_GFMCMP (0x1ul << AES_INTENCLR_GFMCMP_Pos) +#define AES_INTENCLR_MASK 0x03ul /**< \brief (AES_INTENCLR) MASK Register */ + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ +#define AES_INTENSET_RESETVALUE 0x00ul /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ + +#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete */ +#define AES_INTENSET_ENCCMP (0x1ul << AES_INTENSET_ENCCMP_Pos) +#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete */ +#define AES_INTENSET_GFMCMP (0x1ul << AES_INTENSET_GFMCMP_Pos) +#define AES_INTENSET_MASK 0x03ul /**< \brief (AES_INTENSET) MASK Register */ + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ +#define AES_INTFLAG_RESETVALUE 0x00ul /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ + +#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ +#define AES_INTFLAG_ENCCMP (0x1ul << AES_INTFLAG_ENCCMP_Pos) +#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ +#define AES_INTFLAG_GFMCMP (0x1ul << AES_INTFLAG_GFMCMP_Pos) +#define AES_INTFLAG_MASK 0x03ul /**< \brief (AES_INTFLAG) MASK Register */ + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DATABUFPTR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ +#define AES_DATABUFPTR_RESETVALUE 0x00ul /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ + +#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ +#define AES_DATABUFPTR_INDATAPTR_Msk (0x3ul << AES_DATABUFPTR_INDATAPTR_Pos) +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) +#define AES_DATABUFPTR_MASK 0x03ul /**< \brief (AES_DATABUFPTR) MASK Register */ + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W 8) Debug control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ +#define AES_DBGCTRL_RESETVALUE 0x00ul /**< \brief (AES_DBGCTRL reset_value) Debug control */ + +#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ +#define AES_DBGCTRL_DBGRUN (0x1ul << AES_DBGCTRL_DBGRUN_Pos) +#define AES_DBGCTRL_MASK 0x01ul /**< \brief (AES_DBGCTRL) MASK Register */ + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_KEYWORD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ +#define AES_KEYWORD_RESETVALUE 0x00000000ul /**< \brief (AES_KEYWORD reset_value) Keyword n */ +#define AES_KEYWORD_MASK 0xFFFFFFFFul /**< \brief (AES_KEYWORD) MASK Register */ + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ +#define AES_INDATA_RESETVALUE 0x00000000ul /**< \brief (AES_INDATA reset_value) Indata */ +#define AES_INDATA_MASK 0xFFFFFFFFul /**< \brief (AES_INDATA) MASK Register */ + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INTVECTV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ +#define AES_INTVECTV_RESETVALUE 0x00000000ul /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ +#define AES_INTVECTV_MASK 0xFFFFFFFFul /**< \brief (AES_INTVECTV) MASK Register */ + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_HASHKEY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ +#define AES_HASHKEY_RESETVALUE 0x00000000ul /**< \brief (AES_HASHKEY reset_value) Hash key n */ +#define AES_HASHKEY_MASK 0xFFFFFFFFul /**< \brief (AES_HASHKEY) MASK Register */ + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_GHASH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ +#define AES_GHASH_RESETVALUE 0x00000000ul /**< \brief (AES_GHASH reset_value) Galois Hash n */ +#define AES_GHASH_MASK 0xFFFFFFFFul /**< \brief (AES_GHASH) MASK Register */ + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_CIPLEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ +#define AES_CIPLEN_RESETVALUE 0x00000000ul /**< \brief (AES_CIPLEN reset_value) Cipher Length */ +#define AES_CIPLEN_MASK 0xFFFFFFFFul /**< \brief (AES_CIPLEN) MASK Register */ + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_RANDSEED_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ +#define AES_RANDSEED_RESETVALUE 0x00000000ul /**< \brief (AES_RANDSEED reset_value) Random Seed */ +#define AES_RANDSEED_MASK 0xFFFFFFFFul /**< \brief (AES_RANDSEED) MASK Register */ + +/** \brief AES hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ + __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ + __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */ + RoReg8 Reserved1[0x2]; + __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ + RoReg8 Reserved2[0xC]; + __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ + __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ + RoReg8 Reserved3[0x10]; + __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ + __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ + RoReg8 Reserved4[0x4]; + __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ + __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML22_AES_COMPONENT_ */ diff --git a/Sensor Watch Starter Project/include/component/ccl.h b/Sensor Watch Starter Project/include/component/ccl.h new file mode 100755 index 00000000..750ae3ba --- /dev/null +++ b/Sensor Watch Starter Project/include/component/ccl.h @@ -0,0 +1,202 @@ +/** + * \file + * + * \brief Component description for CCL + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_CCL_COMPONENT_ +#define _SAML22_CCL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CCL */ +/* ========================================================================== */ +/** \addtogroup SAML22_CCL Configurable Custom Logic */ +/*@{*/ + +#define CCL_U2225 +#define REV_CCL 0x101 + +/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ +#define CCL_CTRL_RESETVALUE 0x00ul /**< \brief (CCL_CTRL reset_value) Control */ + +#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ +#define CCL_CTRL_SWRST (0x1ul << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ +#define CCL_CTRL_ENABLE (0x1ul << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ +#define CCL_CTRL_RUNSTDBY (0x1ul << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK 0x43ul /**< \brief (CCL_CTRL) MASK Register */ + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE 0x00ul /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ + +#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ +#define CCL_SEQCTRL_SEQSEL_Msk (0xFul << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val 0x0ul /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val 0x1ul /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val 0x2ul /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val 0x3ul /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val 0x4ul /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_MASK 0x0Ful /**< \brief (CCL_SEQCTRL) MASK Register */ + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ + uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ + uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ + uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ + uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ + uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ + uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CCL_LUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE 0x00000000ul /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ + +#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ +#define CCL_LUTCTRL_ENABLE (0x1ul << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ +#define CCL_LUTCTRL_FILTSEL_Msk (0x3ul << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val 0x0ul /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val 0x1ul /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val 0x2ul /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ +#define CCL_LUTCTRL_EDGESEL (0x1ul << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ +#define CCL_LUTCTRL_INSEL0_Msk (0xFul << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val 0x0ul /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val 0x1ul /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val 0x2ul /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val 0x3ul /**< \brief (CCL_LUTCTRL) Event in put source */ +#define CCL_LUTCTRL_INSEL0_IO_Val 0x4ul /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val 0x5ul /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val 0x6ul /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val 0x7ul /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val 0x8ul /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val 0x9ul /**< \brief (CCL_LUTCTRL) SERCOM inout source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ +#define CCL_LUTCTRL_INSEL1_Msk (0xFul << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ +#define CCL_LUTCTRL_INSEL2_Msk (0xFul << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ +#define CCL_LUTCTRL_INVEI (0x1ul << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ +#define CCL_LUTCTRL_LUTEI (0x1ul << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ +#define CCL_LUTCTRL_LUTEO (0x1ul << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ +#define CCL_LUTCTRL_TRUTH_Msk (0xFFul << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_MASK 0xFF7FFFB2ul /**< \brief (CCL_LUTCTRL) MASK Register */ + +/** \brief CCL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ + RoReg8 Reserved2[0x2]; + __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ +} Ccl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML22_CCL_COMPONENT_ */ diff --git a/Sensor Watch Starter Project/include/component/dmac.h b/Sensor Watch Starter Project/include/component/dmac.h new file mode 100755 index 00000000..5a2c06b5 --- /dev/null +++ b/Sensor Watch Starter Project/include/component/dmac.h @@ -0,0 +1,1079 @@ +/** + * \file + * + * \brief Component description for DMAC + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_DMAC_COMPONENT_ +#define _SAML22_DMAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DMAC */ +/* ========================================================================== */ +/** \addtogroup SAML22_DMAC Direct Memory Access Controller */ +/*@{*/ + +#define DMAC_U2223 +#define REV_DMAC 0x221 + +/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ +#define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */ + +#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ +#define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos) +#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ +#define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos) +#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ +#define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos) +#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ +#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) +#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ +#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) +#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ +#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) +#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ +#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) +#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ +#define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos) +#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) +#define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */ + +/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CRCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ +#define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ + +#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ +#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ +#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) +#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ +#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) +#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */ +#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */ +#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */ + +/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCDATAIN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ +#define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ + +#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ +#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos) +#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) +#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */ + +/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCCHKSUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ +#define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ + +#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ +#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) +#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) +#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */ + +/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CRCSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ +#define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ + +#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ +#define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos) +#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ +#define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos) +#define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */ + +/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ +#define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ + +#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ +#define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos) +#define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */ + +/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ + uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ + uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ + uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:16; /*!< bit: 0..15 Channel x Software Trigger */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_SWTRIGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ +#define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ + +#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG12 (1 << DMAC_SWTRIGCTRL_SWTRIG12_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG13 (1 << DMAC_SWTRIGCTRL_SWTRIG13_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG14 (1 << DMAC_SWTRIGCTRL_SWTRIG14_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG15 (1 << DMAC_SWTRIGCTRL_SWTRIG15_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) +#define DMAC_SWTRIGCTRL_MASK 0x0000FFFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ + +/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ + uint32_t :3; /*!< bit: 4.. 6 Reserved */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ + uint32_t :3; /*!< bit: 20..22 Reserved */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ + uint32_t :3; /*!< bit: 28..30 Reserved */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PRICTRL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ +#define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ + +#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos) +#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) +#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos) +#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos) +#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) +#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos) +#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos) +#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) +#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos) +#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos) +#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) +#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos) +#define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */ + +/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :2; /*!< bit: 11..12 Reserved */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_INTPEND_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ +#define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ + +#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ +#define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos) +#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) +#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ +#define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos) +#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ +#define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos) +#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ +#define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos) +#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ +#define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos) +#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ +#define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos) +#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ +#define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos) +#define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */ + +/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ + uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ + uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ + uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:16; /*!< bit: 0..15 Channel x Pending Interrupt */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ +#define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ + +#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) +#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) +#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) +#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) +#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) +#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) +#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) +#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) +#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) +#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) +#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) +#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) +#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT12 (1 << DMAC_INTSTATUS_CHINT12_Pos) +#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT13 (1 << DMAC_INTSTATUS_CHINT13_Pos) +#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT14 (1 << DMAC_INTSTATUS_CHINT14_Pos) +#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT15 (1 << DMAC_INTSTATUS_CHINT15_Pos) +#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT_Msk (0xFFFFul << DMAC_INTSTATUS_CHINT_Pos) +#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) +#define DMAC_INTSTATUS_MASK 0x0000FFFFul /**< \brief (DMAC_INTSTATUS) MASK Register */ + +/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ + uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ + uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ + uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:16; /*!< bit: 0..15 Busy Channel x */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BUSYCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ +#define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ + +#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ +#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) +#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ +#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) +#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ +#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) +#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ +#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) +#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ +#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) +#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ +#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) +#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ +#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) +#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ +#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) +#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ +#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) +#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ +#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) +#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ +#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) +#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ +#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) +#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ +#define DMAC_BUSYCH_BUSYCH12 (1 << DMAC_BUSYCH_BUSYCH12_Pos) +#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ +#define DMAC_BUSYCH_BUSYCH13 (1 << DMAC_BUSYCH_BUSYCH13_Pos) +#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ +#define DMAC_BUSYCH_BUSYCH14 (1 << DMAC_BUSYCH_BUSYCH14_Pos) +#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ +#define DMAC_BUSYCH_BUSYCH15 (1 << DMAC_BUSYCH_BUSYCH15_Pos) +#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ +#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFFul << DMAC_BUSYCH_BUSYCH_Pos) +#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) +#define DMAC_BUSYCH_MASK 0x0000FFFFul /**< \brief (DMAC_BUSYCH) MASK Register */ + +/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ + uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ + uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ + uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:16; /*!< bit: 0..15 Pending Channel x */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PENDCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ +#define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ + +#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ +#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) +#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ +#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) +#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ +#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) +#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ +#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) +#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ +#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) +#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ +#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) +#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ +#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) +#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ +#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) +#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ +#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) +#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ +#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) +#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ +#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) +#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ +#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) +#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ +#define DMAC_PENDCH_PENDCH12 (1 << DMAC_PENDCH_PENDCH12_Pos) +#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ +#define DMAC_PENDCH_PENDCH13 (1 << DMAC_PENDCH_PENDCH13_Pos) +#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ +#define DMAC_PENDCH_PENDCH14 (1 << DMAC_PENDCH_PENDCH14_Pos) +#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ +#define DMAC_PENDCH_PENDCH15 (1 << DMAC_PENDCH_PENDCH15_Pos) +#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ +#define DMAC_PENDCH_PENDCH_Msk (0xFFFFul << DMAC_PENDCH_PENDCH_Pos) +#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) +#define DMAC_PENDCH_MASK 0x0000FFFFul /**< \brief (DMAC_PENDCH) MASK Register */ + +/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_ACTIVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ +#define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ + +#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) +#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) +#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) +#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) +#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos) +#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) +#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ +#define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos) +#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) +#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ +#define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos) +#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ +#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos) +#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) +#define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */ + +/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BASEADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ +#define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ + +#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ +#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos) +#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) +#define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */ + +/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_WRBADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ +#define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ + +#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ +#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos) +#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) +#define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */ + +/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHID_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ +#define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */ + +#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ +#define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos) +#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) +#define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */ + +/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Channel run in standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ +#define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ + +#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ +#define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos) +#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ +#define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos) +#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel run in standby */ +#define DMAC_CHCTRLA_RUNSTDBY (0x1ul << DMAC_CHCTRLA_RUNSTDBY_Pos) +#define DMAC_CHCTRLA_MASK 0x43ul /**< \brief (DMAC_CHCTRLA) MASK Register */ + +/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ + uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ + uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ + uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ + uint32_t :8; /*!< bit: 14..21 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ + uint32_t CMD:2; /*!< bit: 24..25 Software Command */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ +#define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ + +#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ +#define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) +#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ +#define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ +#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ +#define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos) +#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ +#define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos) +#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ +#define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) +#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ +#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) +#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ +#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ +#define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) +#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ +#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ +#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ +#define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) +#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */ + +/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ +#define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ + +#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos) +#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos) +#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos) +#define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */ + +/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ +#define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ + +#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos) +#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos) +#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos) +#define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */ + +/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ + __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ + __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ +#define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ + +#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ +#define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos) +#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ +#define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos) +#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ +#define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos) +#define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */ + +/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ +#define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ + +#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ +#define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos) +#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ +#define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos) +#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ +#define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos) +#define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_BTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ +#define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ + +#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ +#define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos) +#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ +#define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ +#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ +#define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ +#define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ +#define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos) +#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ +#define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos) +#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ +#define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ +#define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) +#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Sensor Watch Starter Project/include/core_cmFunc.h b/Sensor Watch Starter Project/include/core_cmFunc.h new file mode 100755 index 00000000..a1bd88c2 --- /dev/null +++ b/Sensor Watch Starter Project/include/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/Sensor Watch Starter Project/include/core_cmInstr.h b/Sensor Watch Starter Project/include/core_cmInstr.h new file mode 100755 index 00000000..cfdea144 --- /dev/null +++ b/Sensor Watch Starter Project/include/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300)) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/Sensor Watch Starter Project/include/instance/ac.h b/Sensor Watch Starter Project/include/instance/ac.h new file mode 100755 index 00000000..1ee7fac6 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/ac.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Instance description for AC + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_AC_INSTANCE_ +#define _SAML22_AC_INSTANCE_ + +/* ========== Register definition for AC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AC_CTRLA (0x42003400U) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (0x42003401U) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (0x42003402U) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (0x42003404U) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (0x42003405U) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (0x42003406U) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (0x42003407U) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (0x42003408U) /**< \brief (AC) Status B */ +#define REG_AC_DBGCTRL (0x42003409U) /**< \brief (AC) Debug Control */ +#define REG_AC_WINCTRL (0x4200340AU) /**< \brief (AC) Window Control */ +#define REG_AC_SCALER0 (0x4200340CU) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (0x4200340DU) /**< \brief (AC) Scaler 1 */ +#define REG_AC_COMPCTRL0 (0x42003410U) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (0x42003414U) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SYNCBUSY (0x42003420U) /**< \brief (AC) Synchronization Busy */ +#else +#define REG_AC_CTRLA (*(RwReg8 *)0x42003400U) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (*(WoReg8 *)0x42003401U) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (*(RwReg16*)0x42003402U) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (*(RwReg8 *)0x42003404U) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (*(RwReg8 *)0x42003405U) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (*(RwReg8 *)0x42003406U) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (*(RoReg8 *)0x42003407U) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (*(RoReg8 *)0x42003408U) /**< \brief (AC) Status B */ +#define REG_AC_DBGCTRL (*(RwReg8 *)0x42003409U) /**< \brief (AC) Debug Control */ +#define REG_AC_WINCTRL (*(RwReg8 *)0x4200340AU) /**< \brief (AC) Window Control */ +#define REG_AC_SCALER0 (*(RwReg8 *)0x4200340CU) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (*(RwReg8 *)0x4200340DU) /**< \brief (AC) Scaler 1 */ +#define REG_AC_COMPCTRL0 (*(RwReg *)0x42003410U) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (*(RwReg *)0x42003414U) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SYNCBUSY (*(RoReg *)0x42003420U) /**< \brief (AC) Synchronization Busy */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for AC peripheral ========== */ +#define AC_COMPCTRL_MUXNEG_OPAMP 7 // OPAMP selection for MUXNEG +#define AC_GCLK_ID 26 // Index of Generic Clock +#define AC_NUM_CMP 2 // Number of comparators +#define AC_PAIRS 1 // Number of pairs of comparators + +#endif /* _SAML22_AC_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/adc.h b/Sensor Watch Starter Project/include/instance/adc.h new file mode 100755 index 00000000..418a3e93 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/adc.h @@ -0,0 +1,103 @@ +/** + * \file + * + * \brief Instance description for ADC + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_ADC_INSTANCE_ +#define _SAML22_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CTRLA (0x42003000U) /**< \brief (ADC) Control A */ +#define REG_ADC_CTRLB (0x42003001U) /**< \brief (ADC) Control B */ +#define REG_ADC_REFCTRL (0x42003002U) /**< \brief (ADC) Reference Control */ +#define REG_ADC_EVCTRL (0x42003003U) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (0x42003004U) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (0x42003005U) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (0x42003006U) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_SEQSTATUS (0x42003007U) /**< \brief (ADC) Sequence Status */ +#define REG_ADC_INPUTCTRL (0x42003008U) /**< \brief (ADC) Input Control */ +#define REG_ADC_CTRLC (0x4200300AU) /**< \brief (ADC) Control C */ +#define REG_ADC_AVGCTRL (0x4200300CU) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (0x4200300DU) /**< \brief (ADC) Sample Time Control */ +#define REG_ADC_WINLT (0x4200300EU) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (0x42003010U) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (0x42003012U) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (0x42003014U) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_SWTRIG (0x42003018U) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_DBGCTRL (0x4200301CU) /**< \brief (ADC) Debug Control */ +#define REG_ADC_SYNCBUSY (0x42003020U) /**< \brief (ADC) Synchronization Busy */ +#define REG_ADC_RESULT (0x42003024U) /**< \brief (ADC) Result */ +#define REG_ADC_SEQCTRL (0x42003028U) /**< \brief (ADC) Sequence Control */ +#define REG_ADC_CALIB (0x4200302CU) /**< \brief (ADC) Calibration */ +#else +#define REG_ADC_CTRLA (*(RwReg8 *)0x42003000U) /**< \brief (ADC) Control A */ +#define REG_ADC_CTRLB (*(RwReg8 *)0x42003001U) /**< \brief (ADC) Control B */ +#define REG_ADC_REFCTRL (*(RwReg8 *)0x42003002U) /**< \brief (ADC) Reference Control */ +#define REG_ADC_EVCTRL (*(RwReg8 *)0x42003003U) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (*(RwReg8 *)0x42003004U) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (*(RwReg8 *)0x42003005U) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (*(RwReg8 *)0x42003006U) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_SEQSTATUS (*(RoReg8 *)0x42003007U) /**< \brief (ADC) Sequence Status */ +#define REG_ADC_INPUTCTRL (*(RwReg16*)0x42003008U) /**< \brief (ADC) Input Control */ +#define REG_ADC_CTRLC (*(RwReg16*)0x4200300AU) /**< \brief (ADC) Control C */ +#define REG_ADC_AVGCTRL (*(RwReg8 *)0x4200300CU) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x4200300DU) /**< \brief (ADC) Sample Time Control */ +#define REG_ADC_WINLT (*(RwReg16*)0x4200300EU) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (*(RwReg16*)0x42003010U) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (*(RwReg16*)0x42003012U) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42003014U) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_SWTRIG (*(RwReg8 *)0x42003018U) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200301CU) /**< \brief (ADC) Debug Control */ +#define REG_ADC_SYNCBUSY (*(RoReg16*)0x42003020U) /**< \brief (ADC) Synchronization Busy */ +#define REG_ADC_RESULT (*(RoReg16*)0x42003024U) /**< \brief (ADC) Result */ +#define REG_ADC_SEQCTRL (*(RwReg *)0x42003028U) /**< \brief (ADC) Sequence Control */ +#define REG_ADC_CALIB (*(RwReg16*)0x4200302CU) /**< \brief (ADC) Calibration */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for ADC peripheral ========== */ +#define ADC_DMAC_ID_RESRDY 31 // index of DMA RESRDY trigger +#define ADC_EXTCHANNEL_MSB 19 // Number of external channels +#define ADC_GCLK_ID 25 // index of Generic Clock +#define ADC_INT_CH30 2 // Select OPAMP or CTAT on Channel 30 +#define ADC_MASTER_SLAVE_MODE 0 // ADC Master/Slave Mode + +#endif /* _SAML22_ADC_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/aes.h b/Sensor Watch Starter Project/include/instance/aes.h new file mode 100755 index 00000000..93105182 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/aes.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief Instance description for AES + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_AES_INSTANCE_ +#define _SAML22_AES_INSTANCE_ + +/* ========== Register definition for AES peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AES_CTRLA (0x42004000U) /**< \brief (AES) Control A */ +#define REG_AES_CTRLB (0x42004004U) /**< \brief (AES) Control B */ +#define REG_AES_INTENCLR (0x42004005U) /**< \brief (AES) Interrupt Enable Clear */ +#define REG_AES_INTENSET (0x42004006U) /**< \brief (AES) Interrupt Enable Set */ +#define REG_AES_INTFLAG (0x42004007U) /**< \brief (AES) Interrupt Flag Status */ +#define REG_AES_DATABUFPTR (0x42004008U) /**< \brief (AES) Data buffer pointer */ +#define REG_AES_DBGCTRL (0x42004009U) /**< \brief (AES) Debug control */ +#define REG_AES_KEYWORD0 (0x4200400CU) /**< \brief (AES) Keyword 0 */ +#define REG_AES_KEYWORD1 (0x42004010U) /**< \brief (AES) Keyword 1 */ +#define REG_AES_KEYWORD2 (0x42004014U) /**< \brief (AES) Keyword 2 */ +#define REG_AES_KEYWORD3 (0x42004018U) /**< \brief (AES) Keyword 3 */ +#define REG_AES_KEYWORD4 (0x4200401CU) /**< \brief (AES) Keyword 4 */ +#define REG_AES_KEYWORD5 (0x42004020U) /**< \brief (AES) Keyword 5 */ +#define REG_AES_KEYWORD6 (0x42004024U) /**< \brief (AES) Keyword 6 */ +#define REG_AES_KEYWORD7 (0x42004028U) /**< \brief (AES) Keyword 7 */ +#define REG_AES_INDATA (0x42004038U) /**< \brief (AES) Indata */ +#define REG_AES_INTVECTV0 (0x4200403CU) /**< \brief (AES) Initialisation Vector 0 */ +#define REG_AES_INTVECTV1 (0x42004040U) /**< \brief (AES) Initialisation Vector 1 */ +#define REG_AES_INTVECTV2 (0x42004044U) /**< \brief (AES) Initialisation Vector 2 */ +#define REG_AES_INTVECTV3 (0x42004048U) /**< \brief (AES) Initialisation Vector 3 */ +#define REG_AES_HASHKEY0 (0x4200405CU) /**< \brief (AES) Hash key 0 */ +#define REG_AES_HASHKEY1 (0x42004060U) /**< \brief (AES) Hash key 1 */ +#define REG_AES_HASHKEY2 (0x42004064U) /**< \brief (AES) Hash key 2 */ +#define REG_AES_HASHKEY3 (0x42004068U) /**< \brief (AES) Hash key 3 */ +#define REG_AES_GHASH0 (0x4200406CU) /**< \brief (AES) Galois Hash 0 */ +#define REG_AES_GHASH1 (0x42004070U) /**< \brief (AES) Galois Hash 1 */ +#define REG_AES_GHASH2 (0x42004074U) /**< \brief (AES) Galois Hash 2 */ +#define REG_AES_GHASH3 (0x42004078U) /**< \brief (AES) Galois Hash 3 */ +#define REG_AES_CIPLEN (0x42004080U) /**< \brief (AES) Cipher Length */ +#define REG_AES_RANDSEED (0x42004084U) /**< \brief (AES) Random Seed */ +#else +#define REG_AES_CTRLA (*(RwReg *)0x42004000U) /**< \brief (AES) Control A */ +#define REG_AES_CTRLB (*(RwReg8 *)0x42004004U) /**< \brief (AES) Control B */ +#define REG_AES_INTENCLR (*(RwReg8 *)0x42004005U) /**< \brief (AES) Interrupt Enable Clear */ +#define REG_AES_INTENSET (*(RwReg8 *)0x42004006U) /**< \brief (AES) Interrupt Enable Set */ +#define REG_AES_INTFLAG (*(RwReg8 *)0x42004007U) /**< \brief (AES) Interrupt Flag Status */ +#define REG_AES_DATABUFPTR (*(RwReg8 *)0x42004008U) /**< \brief (AES) Data buffer pointer */ +#define REG_AES_DBGCTRL (*(WoReg8 *)0x42004009U) /**< \brief (AES) Debug control */ +#define REG_AES_KEYWORD0 (*(WoReg *)0x4200400CU) /**< \brief (AES) Keyword 0 */ +#define REG_AES_KEYWORD1 (*(WoReg *)0x42004010U) /**< \brief (AES) Keyword 1 */ +#define REG_AES_KEYWORD2 (*(WoReg *)0x42004014U) /**< \brief (AES) Keyword 2 */ +#define REG_AES_KEYWORD3 (*(WoReg *)0x42004018U) /**< \brief (AES) Keyword 3 */ +#define REG_AES_KEYWORD4 (*(WoReg *)0x4200401CU) /**< \brief (AES) Keyword 4 */ +#define REG_AES_KEYWORD5 (*(WoReg *)0x42004020U) /**< \brief (AES) Keyword 5 */ +#define REG_AES_KEYWORD6 (*(WoReg *)0x42004024U) /**< \brief (AES) Keyword 6 */ +#define REG_AES_KEYWORD7 (*(WoReg *)0x42004028U) /**< \brief (AES) Keyword 7 */ +#define REG_AES_INDATA (*(RwReg *)0x42004038U) /**< \brief (AES) Indata */ +#define REG_AES_INTVECTV0 (*(WoReg *)0x4200403CU) /**< \brief (AES) Initialisation Vector 0 */ +#define REG_AES_INTVECTV1 (*(WoReg *)0x42004040U) /**< \brief (AES) Initialisation Vector 1 */ +#define REG_AES_INTVECTV2 (*(WoReg *)0x42004044U) /**< \brief (AES) Initialisation Vector 2 */ +#define REG_AES_INTVECTV3 (*(WoReg *)0x42004048U) /**< \brief (AES) Initialisation Vector 3 */ +#define REG_AES_HASHKEY0 (*(RwReg *)0x4200405CU) /**< \brief (AES) Hash key 0 */ +#define REG_AES_HASHKEY1 (*(RwReg *)0x42004060U) /**< \brief (AES) Hash key 1 */ +#define REG_AES_HASHKEY2 (*(RwReg *)0x42004064U) /**< \brief (AES) Hash key 2 */ +#define REG_AES_HASHKEY3 (*(RwReg *)0x42004068U) /**< \brief (AES) Hash key 3 */ +#define REG_AES_GHASH0 (*(RwReg *)0x4200406CU) /**< \brief (AES) Galois Hash 0 */ +#define REG_AES_GHASH1 (*(RwReg *)0x42004070U) /**< \brief (AES) Galois Hash 1 */ +#define REG_AES_GHASH2 (*(RwReg *)0x42004074U) /**< \brief (AES) Galois Hash 2 */ +#define REG_AES_GHASH3 (*(RwReg *)0x42004078U) /**< \brief (AES) Galois Hash 3 */ +#define REG_AES_CIPLEN (*(RwReg *)0x42004080U) /**< \brief (AES) Cipher Length */ +#define REG_AES_RANDSEED (*(RwReg *)0x42004084U) /**< \brief (AES) Random Seed */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for AES peripheral ========== */ +#define AES_DMAC_ID_RD 36 // DMA DATA Read trigger +#define AES_DMAC_ID_WR 35 // DMA DATA Write trigger + +#endif /* _SAML22_AES_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/ccl.h b/Sensor Watch Starter Project/include/instance/ccl.h new file mode 100755 index 00000000..d5dfb386 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/ccl.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief Instance description for CCL + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_CCL_INSTANCE_ +#define _SAML22_CCL_INSTANCE_ + +/* ========== Register definition for CCL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CCL_CTRL (0x42004800U) /**< \brief (CCL) Control */ +#define REG_CCL_SEQCTRL0 (0x42004804U) /**< \brief (CCL) SEQ Control x 0 */ +#define REG_CCL_SEQCTRL1 (0x42004805U) /**< \brief (CCL) SEQ Control x 1 */ +#define REG_CCL_LUTCTRL0 (0x42004808U) /**< \brief (CCL) LUT Control x 0 */ +#define REG_CCL_LUTCTRL1 (0x4200480CU) /**< \brief (CCL) LUT Control x 1 */ +#define REG_CCL_LUTCTRL2 (0x42004810U) /**< \brief (CCL) LUT Control x 2 */ +#define REG_CCL_LUTCTRL3 (0x42004814U) /**< \brief (CCL) LUT Control x 3 */ +#else +#define REG_CCL_CTRL (*(RwReg8 *)0x42004800U) /**< \brief (CCL) Control */ +#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42004804U) /**< \brief (CCL) SEQ Control x 0 */ +#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42004805U) /**< \brief (CCL) SEQ Control x 1 */ +#define REG_CCL_LUTCTRL0 (*(RwReg *)0x42004808U) /**< \brief (CCL) LUT Control x 0 */ +#define REG_CCL_LUTCTRL1 (*(RwReg *)0x4200480CU) /**< \brief (CCL) LUT Control x 1 */ +#define REG_CCL_LUTCTRL2 (*(RwReg *)0x42004810U) /**< \brief (CCL) LUT Control x 2 */ +#define REG_CCL_LUTCTRL3 (*(RwReg *)0x42004814U) /**< \brief (CCL) LUT Control x 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for CCL peripheral ========== */ +#define CCL_GCLK_ID 28 // GCLK index for CCL +#define CCL_IO_NUM 12 // Numer of input pins +#define CCL_LUT_NUM 4 // Number of LUT in a CCL +#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL + +#endif /* _SAML22_CCL_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/dmac.h b/Sensor Watch Starter Project/include/instance/dmac.h new file mode 100755 index 00000000..3bb38f19 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/dmac.h @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief Instance description for DMAC + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_DMAC_INSTANCE_ +#define _SAML22_DMAC_INSTANCE_ + +/* ========== Register definition for DMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC_CTRL (0x41008000U) /**< \brief (DMAC) Control */ +#define REG_DMAC_CRCCTRL (0x41008002U) /**< \brief (DMAC) CRC Control */ +#define REG_DMAC_CRCDATAIN (0x41008004U) /**< \brief (DMAC) CRC Data Input */ +#define REG_DMAC_CRCCHKSUM (0x41008008U) /**< \brief (DMAC) CRC Checksum */ +#define REG_DMAC_CRCSTATUS (0x4100800CU) /**< \brief (DMAC) CRC Status */ +#define REG_DMAC_DBGCTRL (0x4100800DU) /**< \brief (DMAC) Debug Control */ +#define REG_DMAC_SWTRIGCTRL (0x41008010U) /**< \brief (DMAC) Software Trigger Control */ +#define REG_DMAC_PRICTRL0 (0x41008014U) /**< \brief (DMAC) Priority Control 0 */ +#define REG_DMAC_INTPEND (0x41008020U) /**< \brief (DMAC) Interrupt Pending */ +#define REG_DMAC_INTSTATUS (0x41008024U) /**< \brief (DMAC) Interrupt Status */ +#define REG_DMAC_BUSYCH (0x41008028U) /**< \brief (DMAC) Busy Channels */ +#define REG_DMAC_PENDCH (0x4100802CU) /**< \brief (DMAC) Pending Channels */ +#define REG_DMAC_ACTIVE (0x41008030U) /**< \brief (DMAC) Active Channel and Levels */ +#define REG_DMAC_BASEADDR (0x41008034U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ +#define REG_DMAC_WRBADDR (0x41008038U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ +#define REG_DMAC_CHID (0x4100803FU) /**< \brief (DMAC) Channel ID */ +#define REG_DMAC_CHCTRLA (0x41008040U) /**< \brief (DMAC) Channel Control A */ +#define REG_DMAC_CHCTRLB (0x41008044U) /**< \brief (DMAC) Channel Control B */ +#define REG_DMAC_CHINTENCLR (0x4100804CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ +#define REG_DMAC_CHINTENSET (0x4100804DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ +#define REG_DMAC_CHINTFLAG (0x4100804EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ +#define REG_DMAC_CHSTATUS (0x4100804FU) /**< \brief (DMAC) Channel Status */ +#else +#define REG_DMAC_CTRL (*(RwReg16*)0x41008000U) /**< \brief (DMAC) Control */ +#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41008002U) /**< \brief (DMAC) CRC Control */ +#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41008004U) /**< \brief (DMAC) CRC Data Input */ +#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41008008U) /**< \brief (DMAC) CRC Checksum */ +#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100800CU) /**< \brief (DMAC) CRC Status */ +#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100800DU) /**< \brief (DMAC) Debug Control */ +#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41008010U) /**< \brief (DMAC) Software Trigger Control */ +#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41008014U) /**< \brief (DMAC) Priority Control 0 */ +#define REG_DMAC_INTPEND (*(RwReg16*)0x41008020U) /**< \brief (DMAC) Interrupt Pending */ +#define REG_DMAC_INTSTATUS (*(RoReg *)0x41008024U) /**< \brief (DMAC) Interrupt Status */ +#define REG_DMAC_BUSYCH (*(RoReg *)0x41008028U) /**< \brief (DMAC) Busy Channels */ +#define REG_DMAC_PENDCH (*(RoReg *)0x4100802CU) /**< \brief (DMAC) Pending Channels */ +#define REG_DMAC_ACTIVE (*(RoReg *)0x41008030U) /**< \brief (DMAC) Active Channel and Levels */ +#define REG_DMAC_BASEADDR (*(RwReg *)0x41008034U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ +#define REG_DMAC_WRBADDR (*(RwReg *)0x41008038U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ +#define REG_DMAC_CHID (*(RwReg8 *)0x4100803FU) /**< \brief (DMAC) Channel ID */ +#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41008040U) /**< \brief (DMAC) Channel Control A */ +#define REG_DMAC_CHCTRLB (*(RwReg *)0x41008044U) /**< \brief (DMAC) Channel Control B */ +#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100804CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ +#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100804DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ +#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100804EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ +#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100804FU) /**< \brief (DMAC) Channel Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DMAC peripheral ========== */ +#define DMAC_CH_BITS 4 // Number of bits to select channel +#define DMAC_CH_NUM 16 // Number of channels +#define DMAC_CLK_AHB_ID 3 // AHB clock index +#define DMAC_EVIN_NUM 4 // Number of input events +#define DMAC_EVOUT_NUM 4 // Number of output events +#define DMAC_LVL_BITS 2 // Number of bit to select level priority +#define DMAC_LVL_NUM 4 // Enable priority level number +#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value +#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value +#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value +#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source +#define DMAC_TRIG_NUM 40 // Number of peripheral triggers + +#endif /* _SAML22_DMAC_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/dsu.h b/Sensor Watch Starter Project/include/instance/dsu.h new file mode 100755 index 00000000..0706711f --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/dsu.h @@ -0,0 +1,109 @@ +/** + * \file + * + * \brief Instance description for DSU + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_DSU_INSTANCE_ +#define _SAML22_DSU_INSTANCE_ + +/* ========== Register definition for DSU peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */ +#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */ +#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */ +#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */ +#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */ +#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */ +#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ +#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ +#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */ +#define REG_DSU_DCFG0 (0x410020F0U) /**< \brief (DSU) Device Configuration 0 */ +#define REG_DSU_DCFG1 (0x410020F4U) /**< \brief (DSU) Device Configuration 1 */ +#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ +#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ +#define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ +#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ +#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ +#define REG_DSU_PID5 (0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */ +#define REG_DSU_PID6 (0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */ +#define REG_DSU_PID7 (0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */ +#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ +#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ +#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ +#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ +#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ +#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ +#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ +#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ +#else +#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */ +#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */ +#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */ +#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */ +#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */ +#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */ +#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ +#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ +#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */ +#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0U) /**< \brief (DSU) Device Configuration 0 */ +#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4U) /**< \brief (DSU) Device Configuration 1 */ +#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ +#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ +#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ +#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ +#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ +#define REG_DSU_PID5 (*(RoReg *)0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */ +#define REG_DSU_PID6 (*(RoReg *)0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */ +#define REG_DSU_PID7 (*(RoReg *)0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */ +#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ +#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ +#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ +#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ +#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ +#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ +#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ +#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DSU peripheral ========== */ +#define DSU_CLK_AHB_ID 5 + +#endif /* _SAML22_DSU_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/eic.h b/Sensor Watch Starter Project/include/instance/eic.h new file mode 100755 index 00000000..5c5b2b10 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/eic.h @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief Instance description for EIC + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_EIC_INSTANCE_ +#define _SAML22_EIC_INSTANCE_ + +/* ========== Register definition for EIC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EIC_CTRLA (0x40002800U) /**< \brief (EIC) Control */ +#define REG_EIC_NMICTRL (0x40002801U) /**< \brief (EIC) NMI Control */ +#define REG_EIC_NMIFLAG (0x40002802U) /**< \brief (EIC) NMI Interrupt Flag */ +#define REG_EIC_SYNCBUSY (0x40002804U) /**< \brief (EIC) Syncbusy register */ +#define REG_EIC_EVCTRL (0x40002808U) /**< \brief (EIC) Event Control */ +#define REG_EIC_INTENCLR (0x4000280CU) /**< \brief (EIC) Interrupt Enable Clear */ +#define REG_EIC_INTENSET (0x40002810U) /**< \brief (EIC) Interrupt Enable Set */ +#define REG_EIC_INTFLAG (0x40002814U) /**< \brief (EIC) Interrupt Flag Status and Clear */ +#define REG_EIC_ASYNCH (0x40002818U) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ +#define REG_EIC_CONFIG0 (0x4000281CU) /**< \brief (EIC) Configuration 0 */ +#define REG_EIC_CONFIG1 (0x40002820U) /**< \brief (EIC) Configuration 1 */ +#else +#define REG_EIC_CTRLA (*(RwReg8 *)0x40002800U) /**< \brief (EIC) Control */ +#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801U) /**< \brief (EIC) NMI Control */ +#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802U) /**< \brief (EIC) NMI Interrupt Flag */ +#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804U) /**< \brief (EIC) Syncbusy register */ +#define REG_EIC_EVCTRL (*(RwReg *)0x40002808U) /**< \brief (EIC) Event Control */ +#define REG_EIC_INTENCLR (*(RwReg *)0x4000280CU) /**< \brief (EIC) Interrupt Enable Clear */ +#define REG_EIC_INTENSET (*(RwReg *)0x40002810U) /**< \brief (EIC) Interrupt Enable Set */ +#define REG_EIC_INTFLAG (*(RwReg *)0x40002814U) /**< \brief (EIC) Interrupt Flag Status and Clear */ +#define REG_EIC_ASYNCH (*(RwReg *)0x40002818U) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ +#define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CU) /**< \brief (EIC) Configuration 0 */ +#define REG_EIC_CONFIG1 (*(RwReg *)0x40002820U) /**< \brief (EIC) Configuration 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EIC peripheral ========== */ +#define EIC_EXTINT_NUM 16 +#define EIC_GCLK_ID 3 +#define EIC_NUMBER_OF_CONFIG_REGS 2 +#define EIC_NUMBER_OF_INTERRUPTS 16 + +#endif /* _SAML22_EIC_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/evsys.h b/Sensor Watch Starter Project/include/instance/evsys.h new file mode 100755 index 00000000..a3d62079 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/evsys.h @@ -0,0 +1,269 @@ +/** + * \file + * + * \brief Instance description for EVSYS + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_EVSYS_INSTANCE_ +#define _SAML22_EVSYS_INSTANCE_ + +/* ========== Register definition for EVSYS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EVSYS_CTRLA (0x42000000U) /**< \brief (EVSYS) Control */ +#define REG_EVSYS_CHSTATUS (0x4200000CU) /**< \brief (EVSYS) Channel Status */ +#define REG_EVSYS_INTENCLR (0x42000010U) /**< \brief (EVSYS) Interrupt Enable Clear */ +#define REG_EVSYS_INTENSET (0x42000014U) /**< \brief (EVSYS) Interrupt Enable Set */ +#define REG_EVSYS_INTFLAG (0x42000018U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ +#define REG_EVSYS_SWEVT (0x4200001CU) /**< \brief (EVSYS) Software Event */ +#define REG_EVSYS_CHANNEL0 (0x42000020U) /**< \brief (EVSYS) Channel 0 */ +#define REG_EVSYS_CHANNEL1 (0x42000024U) /**< \brief (EVSYS) Channel 1 */ +#define REG_EVSYS_CHANNEL2 (0x42000028U) /**< \brief (EVSYS) Channel 2 */ +#define REG_EVSYS_CHANNEL3 (0x4200002CU) /**< \brief (EVSYS) Channel 3 */ +#define REG_EVSYS_CHANNEL4 (0x42000030U) /**< \brief (EVSYS) Channel 4 */ +#define REG_EVSYS_CHANNEL5 (0x42000034U) /**< \brief (EVSYS) Channel 5 */ +#define REG_EVSYS_CHANNEL6 (0x42000038U) /**< \brief (EVSYS) Channel 6 */ +#define REG_EVSYS_CHANNEL7 (0x4200003CU) /**< \brief (EVSYS) Channel 7 */ +#define REG_EVSYS_USER0 (0x42000080U) /**< \brief (EVSYS) User Multiplexer 0 */ +#define REG_EVSYS_USER1 (0x42000084U) /**< \brief (EVSYS) User Multiplexer 1 */ +#define REG_EVSYS_USER2 (0x42000088U) /**< \brief (EVSYS) User Multiplexer 2 */ +#define REG_EVSYS_USER3 (0x4200008CU) /**< \brief (EVSYS) User Multiplexer 3 */ +#define REG_EVSYS_USER4 (0x42000090U) /**< \brief (EVSYS) User Multiplexer 4 */ +#define REG_EVSYS_USER5 (0x42000094U) /**< \brief (EVSYS) User Multiplexer 5 */ +#define REG_EVSYS_USER6 (0x42000098U) /**< \brief (EVSYS) User Multiplexer 6 */ +#define REG_EVSYS_USER7 (0x4200009CU) /**< \brief (EVSYS) User Multiplexer 7 */ +#define REG_EVSYS_USER8 (0x420000A0U) /**< \brief (EVSYS) User Multiplexer 8 */ +#define REG_EVSYS_USER9 (0x420000A4U) /**< \brief (EVSYS) User Multiplexer 9 */ +#define REG_EVSYS_USER10 (0x420000A8U) /**< \brief (EVSYS) User Multiplexer 10 */ +#define REG_EVSYS_USER11 (0x420000ACU) /**< \brief (EVSYS) User Multiplexer 11 */ +#define REG_EVSYS_USER12 (0x420000B0U) /**< \brief (EVSYS) User Multiplexer 12 */ +#define REG_EVSYS_USER13 (0x420000B4U) /**< \brief (EVSYS) User Multiplexer 13 */ +#define REG_EVSYS_USER14 (0x420000B8U) /**< \brief (EVSYS) User Multiplexer 14 */ +#define REG_EVSYS_USER15 (0x420000BCU) /**< \brief (EVSYS) User Multiplexer 15 */ +#define REG_EVSYS_USER16 (0x420000C0U) /**< \brief (EVSYS) User Multiplexer 16 */ +#define REG_EVSYS_USER17 (0x420000C4U) /**< \brief (EVSYS) User Multiplexer 17 */ +#define REG_EVSYS_USER18 (0x420000C8U) /**< \brief (EVSYS) User Multiplexer 18 */ +#define REG_EVSYS_USER19 (0x420000CCU) /**< \brief (EVSYS) User Multiplexer 19 */ +#define REG_EVSYS_USER20 (0x420000D0U) /**< \brief (EVSYS) User Multiplexer 20 */ +#define REG_EVSYS_USER21 (0x420000D4U) /**< \brief (EVSYS) User Multiplexer 21 */ +#define REG_EVSYS_USER22 (0x420000D8U) /**< \brief (EVSYS) User Multiplexer 22 */ +#define REG_EVSYS_USER23 (0x420000DCU) /**< \brief (EVSYS) User Multiplexer 23 */ +#define REG_EVSYS_USER24 (0x420000E0U) /**< \brief (EVSYS) User Multiplexer 24 */ +#define REG_EVSYS_USER25 (0x420000E4U) /**< \brief (EVSYS) User Multiplexer 25 */ +#define REG_EVSYS_USER26 (0x420000E8U) /**< \brief (EVSYS) User Multiplexer 26 */ +#define REG_EVSYS_USER27 (0x420000ECU) /**< \brief (EVSYS) User Multiplexer 27 */ +#define REG_EVSYS_USER28 (0x420000F0U) /**< \brief (EVSYS) User Multiplexer 28 */ +#define REG_EVSYS_USER29 (0x420000F4U) /**< \brief (EVSYS) User Multiplexer 29 */ +#define REG_EVSYS_USER30 (0x420000F8U) /**< \brief (EVSYS) User Multiplexer 30 */ +#else +#define REG_EVSYS_CTRLA (*(RwReg8 *)0x42000000U) /**< \brief (EVSYS) Control */ +#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200000CU) /**< \brief (EVSYS) Channel Status */ +#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000010U) /**< \brief (EVSYS) Interrupt Enable Clear */ +#define REG_EVSYS_INTENSET (*(RwReg *)0x42000014U) /**< \brief (EVSYS) Interrupt Enable Set */ +#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000018U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ +#define REG_EVSYS_SWEVT (*(WoReg *)0x4200001CU) /**< \brief (EVSYS) Software Event */ +#define REG_EVSYS_CHANNEL0 (*(RwReg *)0x42000020U) /**< \brief (EVSYS) Channel 0 */ +#define REG_EVSYS_CHANNEL1 (*(RwReg *)0x42000024U) /**< \brief (EVSYS) Channel 1 */ +#define REG_EVSYS_CHANNEL2 (*(RwReg *)0x42000028U) /**< \brief (EVSYS) Channel 2 */ +#define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4200002CU) /**< \brief (EVSYS) Channel 3 */ +#define REG_EVSYS_CHANNEL4 (*(RwReg *)0x42000030U) /**< \brief (EVSYS) Channel 4 */ +#define REG_EVSYS_CHANNEL5 (*(RwReg *)0x42000034U) /**< \brief (EVSYS) Channel 5 */ +#define REG_EVSYS_CHANNEL6 (*(RwReg *)0x42000038U) /**< \brief (EVSYS) Channel 6 */ +#define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4200003CU) /**< \brief (EVSYS) Channel 7 */ +#define REG_EVSYS_USER0 (*(RwReg *)0x42000080U) /**< \brief (EVSYS) User Multiplexer 0 */ +#define REG_EVSYS_USER1 (*(RwReg *)0x42000084U) /**< \brief (EVSYS) User Multiplexer 1 */ +#define REG_EVSYS_USER2 (*(RwReg *)0x42000088U) /**< \brief (EVSYS) User Multiplexer 2 */ +#define REG_EVSYS_USER3 (*(RwReg *)0x4200008CU) /**< \brief (EVSYS) User Multiplexer 3 */ +#define REG_EVSYS_USER4 (*(RwReg *)0x42000090U) /**< \brief (EVSYS) User Multiplexer 4 */ +#define REG_EVSYS_USER5 (*(RwReg *)0x42000094U) /**< \brief (EVSYS) User Multiplexer 5 */ +#define REG_EVSYS_USER6 (*(RwReg *)0x42000098U) /**< \brief (EVSYS) User Multiplexer 6 */ +#define REG_EVSYS_USER7 (*(RwReg *)0x4200009CU) /**< \brief (EVSYS) User Multiplexer 7 */ +#define REG_EVSYS_USER8 (*(RwReg *)0x420000A0U) /**< \brief (EVSYS) User Multiplexer 8 */ +#define REG_EVSYS_USER9 (*(RwReg *)0x420000A4U) /**< \brief (EVSYS) User Multiplexer 9 */ +#define REG_EVSYS_USER10 (*(RwReg *)0x420000A8U) /**< \brief (EVSYS) User Multiplexer 10 */ +#define REG_EVSYS_USER11 (*(RwReg *)0x420000ACU) /**< \brief (EVSYS) User Multiplexer 11 */ +#define REG_EVSYS_USER12 (*(RwReg *)0x420000B0U) /**< \brief (EVSYS) User Multiplexer 12 */ +#define REG_EVSYS_USER13 (*(RwReg *)0x420000B4U) /**< \brief (EVSYS) User Multiplexer 13 */ +#define REG_EVSYS_USER14 (*(RwReg *)0x420000B8U) /**< \brief (EVSYS) User Multiplexer 14 */ +#define REG_EVSYS_USER15 (*(RwReg *)0x420000BCU) /**< \brief (EVSYS) User Multiplexer 15 */ +#define REG_EVSYS_USER16 (*(RwReg *)0x420000C0U) /**< \brief (EVSYS) User Multiplexer 16 */ +#define REG_EVSYS_USER17 (*(RwReg *)0x420000C4U) /**< \brief (EVSYS) User Multiplexer 17 */ +#define REG_EVSYS_USER18 (*(RwReg *)0x420000C8U) /**< \brief (EVSYS) User Multiplexer 18 */ +#define REG_EVSYS_USER19 (*(RwReg *)0x420000CCU) /**< \brief (EVSYS) User Multiplexer 19 */ +#define REG_EVSYS_USER20 (*(RwReg *)0x420000D0U) /**< \brief (EVSYS) User Multiplexer 20 */ +#define REG_EVSYS_USER21 (*(RwReg *)0x420000D4U) /**< \brief (EVSYS) User Multiplexer 21 */ +#define REG_EVSYS_USER22 (*(RwReg *)0x420000D8U) /**< \brief (EVSYS) User Multiplexer 22 */ +#define REG_EVSYS_USER23 (*(RwReg *)0x420000DCU) /**< \brief (EVSYS) User Multiplexer 23 */ +#define REG_EVSYS_USER24 (*(RwReg *)0x420000E0U) /**< \brief (EVSYS) User Multiplexer 24 */ +#define REG_EVSYS_USER25 (*(RwReg *)0x420000E4U) /**< \brief (EVSYS) User Multiplexer 25 */ +#define REG_EVSYS_USER26 (*(RwReg *)0x420000E8U) /**< \brief (EVSYS) User Multiplexer 26 */ +#define REG_EVSYS_USER27 (*(RwReg *)0x420000ECU) /**< \brief (EVSYS) User Multiplexer 27 */ +#define REG_EVSYS_USER28 (*(RwReg *)0x420000F0U) /**< \brief (EVSYS) User Multiplexer 28 */ +#define REG_EVSYS_USER29 (*(RwReg *)0x420000F4U) /**< \brief (EVSYS) User Multiplexer 29 */ +#define REG_EVSYS_USER30 (*(RwReg *)0x420000F8U) /**< \brief (EVSYS) User Multiplexer 30 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EVSYS peripheral ========== */ +#define EVSYS_CHANNELS 8 // Number of Channels +#define EVSYS_CHANNELS_BITS 3 // Number of bits to select Channel +#define EVSYS_CHANNELS_MSB 7 // Number of Channels - 1 +#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators +#define EVSYS_GCLK_ID_0 7 +#define EVSYS_GCLK_ID_1 8 +#define EVSYS_GCLK_ID_2 9 +#define EVSYS_GCLK_ID_3 10 +#define EVSYS_GCLK_ID_4 11 +#define EVSYS_GCLK_ID_5 12 +#define EVSYS_GCLK_ID_6 13 +#define EVSYS_GCLK_ID_7 14 +#define EVSYS_GCLK_ID_LSB 7 +#define EVSYS_GCLK_ID_MSB 14 +#define EVSYS_GCLK_ID_SIZE 8 +#define EVSYS_GENERATORS 71 // Total Number of Event Generators +#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator +#define EVSYS_USERS 31 // Total Number of Event Users +#define EVSYS_USERS_BITS 5 // Number of bits to select Event User + +// GENERATORS +#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL 1 +#define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 2 +#define EVSYS_ID_GEN_RTC_CMP_0 3 +#define EVSYS_ID_GEN_RTC_CMP_1 4 +#define EVSYS_ID_GEN_RTC_TAMPER 5 +#define EVSYS_ID_GEN_RTC_OVF 6 +#define EVSYS_ID_GEN_RTC_PER_0 7 +#define EVSYS_ID_GEN_RTC_PER_1 8 +#define EVSYS_ID_GEN_RTC_PER_2 9 +#define EVSYS_ID_GEN_RTC_PER_3 10 +#define EVSYS_ID_GEN_RTC_PER_4 11 +#define EVSYS_ID_GEN_RTC_PER_5 12 +#define EVSYS_ID_GEN_RTC_PER_6 13 +#define EVSYS_ID_GEN_RTC_PER_7 14 +#define EVSYS_ID_GEN_EIC_EXTINT_0 15 +#define EVSYS_ID_GEN_EIC_EXTINT_1 16 +#define EVSYS_ID_GEN_EIC_EXTINT_2 17 +#define EVSYS_ID_GEN_EIC_EXTINT_3 18 +#define EVSYS_ID_GEN_EIC_EXTINT_4 19 +#define EVSYS_ID_GEN_EIC_EXTINT_5 20 +#define EVSYS_ID_GEN_EIC_EXTINT_6 21 +#define EVSYS_ID_GEN_EIC_EXTINT_7 22 +#define EVSYS_ID_GEN_EIC_EXTINT_8 23 +#define EVSYS_ID_GEN_EIC_EXTINT_9 24 +#define EVSYS_ID_GEN_EIC_EXTINT_10 25 +#define EVSYS_ID_GEN_EIC_EXTINT_11 26 +#define EVSYS_ID_GEN_EIC_EXTINT_12 27 +#define EVSYS_ID_GEN_EIC_EXTINT_13 28 +#define EVSYS_ID_GEN_EIC_EXTINT_14 29 +#define EVSYS_ID_GEN_EIC_EXTINT_15 30 +#define EVSYS_ID_GEN_DMAC_CH_0 31 +#define EVSYS_ID_GEN_DMAC_CH_1 32 +#define EVSYS_ID_GEN_DMAC_CH_2 33 +#define EVSYS_ID_GEN_DMAC_CH_3 34 +#define EVSYS_ID_GEN_TCC0_OVF 35 +#define EVSYS_ID_GEN_TCC0_TRG 36 +#define EVSYS_ID_GEN_TCC0_CNT 37 +#define EVSYS_ID_GEN_TCC0_MCX_0 38 +#define EVSYS_ID_GEN_TCC0_MCX_1 39 +#define EVSYS_ID_GEN_TCC0_MCX_2 40 +#define EVSYS_ID_GEN_TCC0_MCX_3 41 +#define EVSYS_ID_GEN_TC0_OVF 42 +#define EVSYS_ID_GEN_TC0_MCX_0 43 +#define EVSYS_ID_GEN_TC0_MCX_1 44 +#define EVSYS_ID_GEN_TC1_OVF 45 +#define EVSYS_ID_GEN_TC1_MCX_0 46 +#define EVSYS_ID_GEN_TC1_MCX_1 47 +#define EVSYS_ID_GEN_TC2_OVF 48 +#define EVSYS_ID_GEN_TC2_MCX_0 49 +#define EVSYS_ID_GEN_TC2_MCX_1 50 +#define EVSYS_ID_GEN_TC3_OVF 51 +#define EVSYS_ID_GEN_TC3_MCX_0 52 +#define EVSYS_ID_GEN_TC3_MCX_1 53 +#define EVSYS_ID_GEN_ADC_RESRDY 54 +#define EVSYS_ID_GEN_ADC_WINMON 55 +#define EVSYS_ID_GEN_AC_COMP_0 56 +#define EVSYS_ID_GEN_AC_COMP_1 57 +#define EVSYS_ID_GEN_AC_WIN_0 58 +#define EVSYS_ID_GEN_PTC_EOC 59 +#define EVSYS_ID_GEN_PTC_WCOMP 60 +#define EVSYS_ID_GEN_SLCD_FC0OVERFLOW 61 +#define EVSYS_ID_GEN_SLCD_FC1OVERFLOW 62 +#define EVSYS_ID_GEN_SLCD_FC2OVERFLOW 63 +#define EVSYS_ID_GEN_SLCD_DT 64 +#define EVSYS_ID_GEN_TRNG_READY 65 +#define EVSYS_ID_GEN_CCL_LUTOUT_0 66 +#define EVSYS_ID_GEN_CCL_LUTOUT_1 67 +#define EVSYS_ID_GEN_CCL_LUTOUT_2 68 +#define EVSYS_ID_GEN_CCL_LUTOUT_3 69 +#define EVSYS_ID_GEN_PAC_ACCERR 70 +#define EVSYS_ID_GEN_TAL_BRK 71 + +// USERS +#define EVSYS_ID_USER_RTC_TAMPER 0 +#define EVSYS_ID_USER_PORT_EV_0 1 +#define EVSYS_ID_USER_PORT_EV_1 2 +#define EVSYS_ID_USER_PORT_EV_2 3 +#define EVSYS_ID_USER_PORT_EV_3 4 +#define EVSYS_ID_USER_DMAC_CH_0 5 +#define EVSYS_ID_USER_DMAC_CH_1 6 +#define EVSYS_ID_USER_DMAC_CH_2 7 +#define EVSYS_ID_USER_DMAC_CH_3 8 +#define EVSYS_ID_USER_TCC0_EV_0 9 +#define EVSYS_ID_USER_TCC0_EV_1 10 +#define EVSYS_ID_USER_TCC0_MC_0 11 +#define EVSYS_ID_USER_TCC0_MC_1 12 +#define EVSYS_ID_USER_TCC0_MC_2 13 +#define EVSYS_ID_USER_TCC0_MC_3 14 +#define EVSYS_ID_USER_TC0_EVU 15 +#define EVSYS_ID_USER_TC1_EVU 16 +#define EVSYS_ID_USER_TC2_EVU 17 +#define EVSYS_ID_USER_TC3_EVU 18 +#define EVSYS_ID_USER_ADC_START 19 +#define EVSYS_ID_USER_ADC_SYNC 20 +#define EVSYS_ID_USER_AC_SOC_0 21 +#define EVSYS_ID_USER_AC_SOC_1 22 +#define EVSYS_ID_USER_PTC_STCONV 23 +#define EVSYS_ID_USER_CCL_LUTIN_0 24 +#define EVSYS_ID_USER_CCL_LUTIN_1 25 +#define EVSYS_ID_USER_CCL_LUTIN_2 26 +#define EVSYS_ID_USER_CCL_LUTIN_3 27 +#define EVSYS_ID_USER_TAL_BRK 28 +#define EVSYS_ID_USER_MTB_START 29 +#define EVSYS_ID_USER_MTB_STOP 30 + +#endif /* _SAML22_EVSYS_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/freqm.h b/Sensor Watch Starter Project/include/instance/freqm.h new file mode 100755 index 00000000..63b21c17 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/freqm.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Instance description for FREQM + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_FREQM_INSTANCE_ +#define _SAML22_FREQM_INSTANCE_ + +/* ========== Register definition for FREQM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FREQM_CTRLA (0x40002C00U) /**< \brief (FREQM) Control A Register */ +#define REG_FREQM_CTRLB (0x40002C01U) /**< \brief (FREQM) Control B Register */ +#define REG_FREQM_CFGA (0x40002C02U) /**< \brief (FREQM) Config A register */ +#define REG_FREQM_INTENCLR (0x40002C08U) /**< \brief (FREQM) Interrupt Enable Clear Register */ +#define REG_FREQM_INTENSET (0x40002C09U) /**< \brief (FREQM) Interrupt Enable Set Register */ +#define REG_FREQM_INTFLAG (0x40002C0AU) /**< \brief (FREQM) Interrupt Flag Register */ +#define REG_FREQM_STATUS (0x40002C0BU) /**< \brief (FREQM) Status Register */ +#define REG_FREQM_SYNCBUSY (0x40002C0CU) /**< \brief (FREQM) Synchronization Busy Register */ +#define REG_FREQM_VALUE (0x40002C10U) /**< \brief (FREQM) Count Value Register */ +#else +#define REG_FREQM_CTRLA (*(RwReg8 *)0x40002C00U) /**< \brief (FREQM) Control A Register */ +#define REG_FREQM_CTRLB (*(WoReg8 *)0x40002C01U) /**< \brief (FREQM) Control B Register */ +#define REG_FREQM_CFGA (*(RwReg16*)0x40002C02U) /**< \brief (FREQM) Config A register */ +#define REG_FREQM_INTENCLR (*(RwReg8 *)0x40002C08U) /**< \brief (FREQM) Interrupt Enable Clear Register */ +#define REG_FREQM_INTENSET (*(RwReg8 *)0x40002C09U) /**< \brief (FREQM) Interrupt Enable Set Register */ +#define REG_FREQM_INTFLAG (*(RwReg8 *)0x40002C0AU) /**< \brief (FREQM) Interrupt Flag Register */ +#define REG_FREQM_STATUS (*(RwReg8 *)0x40002C0BU) /**< \brief (FREQM) Status Register */ +#define REG_FREQM_SYNCBUSY (*(RoReg *)0x40002C0CU) /**< \brief (FREQM) Synchronization Busy Register */ +#define REG_FREQM_VALUE (*(RoReg *)0x40002C10U) /**< \brief (FREQM) Count Value Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for FREQM peripheral ========== */ +#define FREQM_GCLK_ID_MSR 4 // Index of measure generic clock +#define FREQM_GCLK_ID_REF 5 // Index of reference generic clock + +#endif /* _SAML22_FREQM_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/gclk.h b/Sensor Watch Starter Project/include/instance/gclk.h new file mode 100755 index 00000000..7453e366 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/gclk.h @@ -0,0 +1,144 @@ +/** + * \file + * + * \brief Instance description for GCLK + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_GCLK_INSTANCE_ +#define _SAML22_GCLK_INSTANCE_ + +/* ========== Register definition for GCLK peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GCLK_CTRLA (0x40001C00U) /**< \brief (GCLK) Control */ +#define REG_GCLK_SYNCBUSY (0x40001C04U) /**< \brief (GCLK) Synchronization Busy */ +#define REG_GCLK_GENCTRL0 (0x40001C20U) /**< \brief (GCLK) Generic Clock Generator Control 0 */ +#define REG_GCLK_GENCTRL1 (0x40001C24U) /**< \brief (GCLK) Generic Clock Generator Control 1 */ +#define REG_GCLK_GENCTRL2 (0x40001C28U) /**< \brief (GCLK) Generic Clock Generator Control 2 */ +#define REG_GCLK_GENCTRL3 (0x40001C2CU) /**< \brief (GCLK) Generic Clock Generator Control 3 */ +#define REG_GCLK_GENCTRL4 (0x40001C30U) /**< \brief (GCLK) Generic Clock Generator Control 4 */ +#define REG_GCLK_PCHCTRL0 (0x40001C80U) /**< \brief (GCLK) Peripheral Clock Control 0 */ +#define REG_GCLK_PCHCTRL1 (0x40001C84U) /**< \brief (GCLK) Peripheral Clock Control 1 */ +#define REG_GCLK_PCHCTRL2 (0x40001C88U) /**< \brief (GCLK) Peripheral Clock Control 2 */ +#define REG_GCLK_PCHCTRL3 (0x40001C8CU) /**< \brief (GCLK) Peripheral Clock Control 3 */ +#define REG_GCLK_PCHCTRL4 (0x40001C90U) /**< \brief (GCLK) Peripheral Clock Control 4 */ +#define REG_GCLK_PCHCTRL5 (0x40001C94U) /**< \brief (GCLK) Peripheral Clock Control 5 */ +#define REG_GCLK_PCHCTRL6 (0x40001C98U) /**< \brief (GCLK) Peripheral Clock Control 6 */ +#define REG_GCLK_PCHCTRL7 (0x40001C9CU) /**< \brief (GCLK) Peripheral Clock Control 7 */ +#define REG_GCLK_PCHCTRL8 (0x40001CA0U) /**< \brief (GCLK) Peripheral Clock Control 8 */ +#define REG_GCLK_PCHCTRL9 (0x40001CA4U) /**< \brief (GCLK) Peripheral Clock Control 9 */ +#define REG_GCLK_PCHCTRL10 (0x40001CA8U) /**< \brief (GCLK) Peripheral Clock Control 10 */ +#define REG_GCLK_PCHCTRL11 (0x40001CACU) /**< \brief (GCLK) Peripheral Clock Control 11 */ +#define REG_GCLK_PCHCTRL12 (0x40001CB0U) /**< \brief (GCLK) Peripheral Clock Control 12 */ +#define REG_GCLK_PCHCTRL13 (0x40001CB4U) /**< \brief (GCLK) Peripheral Clock Control 13 */ +#define REG_GCLK_PCHCTRL14 (0x40001CB8U) /**< \brief (GCLK) Peripheral Clock Control 14 */ +#define REG_GCLK_PCHCTRL15 (0x40001CBCU) /**< \brief (GCLK) Peripheral Clock Control 15 */ +#define REG_GCLK_PCHCTRL16 (0x40001CC0U) /**< \brief (GCLK) Peripheral Clock Control 16 */ +#define REG_GCLK_PCHCTRL17 (0x40001CC4U) /**< \brief (GCLK) Peripheral Clock Control 17 */ +#define REG_GCLK_PCHCTRL18 (0x40001CC8U) /**< \brief (GCLK) Peripheral Clock Control 18 */ +#define REG_GCLK_PCHCTRL19 (0x40001CCCU) /**< \brief (GCLK) Peripheral Clock Control 19 */ +#define REG_GCLK_PCHCTRL20 (0x40001CD0U) /**< \brief (GCLK) Peripheral Clock Control 20 */ +#define REG_GCLK_PCHCTRL21 (0x40001CD4U) /**< \brief (GCLK) Peripheral Clock Control 21 */ +#define REG_GCLK_PCHCTRL22 (0x40001CD8U) /**< \brief (GCLK) Peripheral Clock Control 22 */ +#define REG_GCLK_PCHCTRL23 (0x40001CDCU) /**< \brief (GCLK) Peripheral Clock Control 23 */ +#define REG_GCLK_PCHCTRL24 (0x40001CE0U) /**< \brief (GCLK) Peripheral Clock Control 24 */ +#define REG_GCLK_PCHCTRL25 (0x40001CE4U) /**< \brief (GCLK) Peripheral Clock Control 25 */ +#define REG_GCLK_PCHCTRL26 (0x40001CE8U) /**< \brief (GCLK) Peripheral Clock Control 26 */ +#define REG_GCLK_PCHCTRL27 (0x40001CECU) /**< \brief (GCLK) Peripheral Clock Control 27 */ +#define REG_GCLK_PCHCTRL28 (0x40001CF0U) /**< \brief (GCLK) Peripheral Clock Control 28 */ +#define REG_GCLK_PCHCTRL29 (0x40001CF4U) /**< \brief (GCLK) Peripheral Clock Control 29 */ +#else +#define REG_GCLK_CTRLA (*(RwReg8 *)0x40001C00U) /**< \brief (GCLK) Control */ +#define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001C04U) /**< \brief (GCLK) Synchronization Busy */ +#define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001C20U) /**< \brief (GCLK) Generic Clock Generator Control 0 */ +#define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001C24U) /**< \brief (GCLK) Generic Clock Generator Control 1 */ +#define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001C28U) /**< \brief (GCLK) Generic Clock Generator Control 2 */ +#define REG_GCLK_GENCTRL3 (*(RwReg *)0x40001C2CU) /**< \brief (GCLK) Generic Clock Generator Control 3 */ +#define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001C30U) /**< \brief (GCLK) Generic Clock Generator Control 4 */ +#define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001C80U) /**< \brief (GCLK) Peripheral Clock Control 0 */ +#define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001C84U) /**< \brief (GCLK) Peripheral Clock Control 1 */ +#define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001C88U) /**< \brief (GCLK) Peripheral Clock Control 2 */ +#define REG_GCLK_PCHCTRL3 (*(RwReg *)0x40001C8CU) /**< \brief (GCLK) Peripheral Clock Control 3 */ +#define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001C90U) /**< \brief (GCLK) Peripheral Clock Control 4 */ +#define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001C94U) /**< \brief (GCLK) Peripheral Clock Control 5 */ +#define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001C98U) /**< \brief (GCLK) Peripheral Clock Control 6 */ +#define REG_GCLK_PCHCTRL7 (*(RwReg *)0x40001C9CU) /**< \brief (GCLK) Peripheral Clock Control 7 */ +#define REG_GCLK_PCHCTRL8 (*(RwReg *)0x40001CA0U) /**< \brief (GCLK) Peripheral Clock Control 8 */ +#define REG_GCLK_PCHCTRL9 (*(RwReg *)0x40001CA4U) /**< \brief (GCLK) Peripheral Clock Control 9 */ +#define REG_GCLK_PCHCTRL10 (*(RwReg *)0x40001CA8U) /**< \brief (GCLK) Peripheral Clock Control 10 */ +#define REG_GCLK_PCHCTRL11 (*(RwReg *)0x40001CACU) /**< \brief (GCLK) Peripheral Clock Control 11 */ +#define REG_GCLK_PCHCTRL12 (*(RwReg *)0x40001CB0U) /**< \brief (GCLK) Peripheral Clock Control 12 */ +#define REG_GCLK_PCHCTRL13 (*(RwReg *)0x40001CB4U) /**< \brief (GCLK) Peripheral Clock Control 13 */ +#define REG_GCLK_PCHCTRL14 (*(RwReg *)0x40001CB8U) /**< \brief (GCLK) Peripheral Clock Control 14 */ +#define REG_GCLK_PCHCTRL15 (*(RwReg *)0x40001CBCU) /**< \brief (GCLK) Peripheral Clock Control 15 */ +#define REG_GCLK_PCHCTRL16 (*(RwReg *)0x40001CC0U) /**< \brief (GCLK) Peripheral Clock Control 16 */ +#define REG_GCLK_PCHCTRL17 (*(RwReg *)0x40001CC4U) /**< \brief (GCLK) Peripheral Clock Control 17 */ +#define REG_GCLK_PCHCTRL18 (*(RwReg *)0x40001CC8U) /**< \brief (GCLK) Peripheral Clock Control 18 */ +#define REG_GCLK_PCHCTRL19 (*(RwReg *)0x40001CCCU) /**< \brief (GCLK) Peripheral Clock Control 19 */ +#define REG_GCLK_PCHCTRL20 (*(RwReg *)0x40001CD0U) /**< \brief (GCLK) Peripheral Clock Control 20 */ +#define REG_GCLK_PCHCTRL21 (*(RwReg *)0x40001CD4U) /**< \brief (GCLK) Peripheral Clock Control 21 */ +#define REG_GCLK_PCHCTRL22 (*(RwReg *)0x40001CD8U) /**< \brief (GCLK) Peripheral Clock Control 22 */ +#define REG_GCLK_PCHCTRL23 (*(RwReg *)0x40001CDCU) /**< \brief (GCLK) Peripheral Clock Control 23 */ +#define REG_GCLK_PCHCTRL24 (*(RwReg *)0x40001CE0U) /**< \brief (GCLK) Peripheral Clock Control 24 */ +#define REG_GCLK_PCHCTRL25 (*(RwReg *)0x40001CE4U) /**< \brief (GCLK) Peripheral Clock Control 25 */ +#define REG_GCLK_PCHCTRL26 (*(RwReg *)0x40001CE8U) /**< \brief (GCLK) Peripheral Clock Control 26 */ +#define REG_GCLK_PCHCTRL27 (*(RwReg *)0x40001CECU) /**< \brief (GCLK) Peripheral Clock Control 27 */ +#define REG_GCLK_PCHCTRL28 (*(RwReg *)0x40001CF0U) /**< \brief (GCLK) Peripheral Clock Control 28 */ +#define REG_GCLK_PCHCTRL29 (*(RwReg *)0x40001CF4U) /**< \brief (GCLK) Peripheral Clock Control 29 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for GCLK peripheral ========== */ +#define GCLK_GENDIV_BITS 16 +#define GCLK_GEN_BITS 3 +#define GCLK_GEN_NUM 5 // Number of Generic Clock Generators +#define GCLK_GEN_NUM_MSB 4 // Number of Generic Clock Generators - 1 +#define GCLK_GEN_SOURCE_NUM_MSB 7 // Number of Generic Clock Sources - 1 +#define GCLK_NUM 30 // Number of Generic Clock Users +#define GCLK_SOURCE_BITS 3 +#define GCLK_SOURCE_DFLL48M 6 +#define GCLK_SOURCE_FDPLL 7 +#define GCLK_SOURCE_GCLKGEN1 2 +#define GCLK_SOURCE_GCLKIN 1 +#define GCLK_SOURCE_NUM 8 // Number of Generic Clock Sources +#define GCLK_SOURCE_OSCULP32K 3 +#define GCLK_SOURCE_OSC16M 5 +#define GCLK_SOURCE_XOSC 0 +#define GCLK_SOURCE_XOSC32K 4 + +#endif /* _SAML22_GCLK_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/mclk.h b/Sensor Watch Starter Project/include/instance/mclk.h new file mode 100755 index 00000000..25115a05 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/mclk.h @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief Instance description for MCLK + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_MCLK_INSTANCE_ +#define _SAML22_MCLK_INSTANCE_ + +/* ========== Register definition for MCLK peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MCLK_INTENCLR (0x40000801U) /**< \brief (MCLK) Interrupt Enable Clear */ +#define REG_MCLK_INTENSET (0x40000802U) /**< \brief (MCLK) Interrupt Enable Set */ +#define REG_MCLK_INTFLAG (0x40000803U) /**< \brief (MCLK) Interrupt Flag Status and Clear */ +#define REG_MCLK_CPUDIV (0x40000804U) /**< \brief (MCLK) CPU Clock Division */ +#define REG_MCLK_BUPDIV (0x40000806U) /**< \brief (MCLK) Backup Clock Division */ +#define REG_MCLK_AHBMASK (0x40000810U) /**< \brief (MCLK) AHB Mask */ +#define REG_MCLK_APBAMASK (0x40000814U) /**< \brief (MCLK) APBA Mask */ +#define REG_MCLK_APBBMASK (0x40000818U) /**< \brief (MCLK) APBB Mask */ +#define REG_MCLK_APBCMASK (0x4000081CU) /**< \brief (MCLK) APBC Mask */ +#else +#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000801U) /**< \brief (MCLK) Interrupt Enable Clear */ +#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000802U) /**< \brief (MCLK) Interrupt Enable Set */ +#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000803U) /**< \brief (MCLK) Interrupt Flag Status and Clear */ +#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804U) /**< \brief (MCLK) CPU Clock Division */ +#define REG_MCLK_BUPDIV (*(RwReg8 *)0x40000806U) /**< \brief (MCLK) Backup Clock Division */ +#define REG_MCLK_AHBMASK (*(RwReg *)0x40000810U) /**< \brief (MCLK) AHB Mask */ +#define REG_MCLK_APBAMASK (*(RwReg *)0x40000814U) /**< \brief (MCLK) APBA Mask */ +#define REG_MCLK_APBBMASK (*(RwReg *)0x40000818U) /**< \brief (MCLK) APBB Mask */ +#define REG_MCLK_APBCMASK (*(RwReg *)0x4000081CU) /**< \brief (MCLK) APBC Mask */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for MCLK peripheral ========== */ +#define MCLK_BUPDIV_IMPLEMENTED 1 +#define MCLK_CTRLA_MCSEL_GCLK 1 +#define MCLK_CTRLA_MCSEL_OSC8M 0 +#define MCLK_MCLK_CLK_APB_NUM 3 + +#endif /* _SAML22_MCLK_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/mtb.h b/Sensor Watch Starter Project/include/instance/mtb.h new file mode 100755 index 00000000..09851e4e --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/mtb.h @@ -0,0 +1,103 @@ +/** + * \file + * + * \brief Instance description for MTB + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_MTB_INSTANCE_ +#define _SAML22_MTB_INSTANCE_ + +/* ========== Register definition for MTB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MTB_POSITION (0x4100A000U) /**< \brief (MTB) MTB Position */ +#define REG_MTB_MASTER (0x4100A004U) /**< \brief (MTB) MTB Master */ +#define REG_MTB_FLOW (0x4100A008U) /**< \brief (MTB) MTB Flow */ +#define REG_MTB_BASE (0x4100A00CU) /**< \brief (MTB) MTB Base */ +#define REG_MTB_ITCTRL (0x4100AF00U) /**< \brief (MTB) MTB Integration Mode Control */ +#define REG_MTB_CLAIMSET (0x4100AFA0U) /**< \brief (MTB) MTB Claim Set */ +#define REG_MTB_CLAIMCLR (0x4100AFA4U) /**< \brief (MTB) MTB Claim Clear */ +#define REG_MTB_LOCKACCESS (0x4100AFB0U) /**< \brief (MTB) MTB Lock Access */ +#define REG_MTB_LOCKSTATUS (0x4100AFB4U) /**< \brief (MTB) MTB Lock Status */ +#define REG_MTB_AUTHSTATUS (0x4100AFB8U) /**< \brief (MTB) MTB Authentication Status */ +#define REG_MTB_DEVARCH (0x4100AFBCU) /**< \brief (MTB) MTB Device Architecture */ +#define REG_MTB_DEVID (0x4100AFC8U) /**< \brief (MTB) MTB Device Configuration */ +#define REG_MTB_DEVTYPE (0x4100AFCCU) /**< \brief (MTB) MTB Device Type */ +#define REG_MTB_PID4 (0x4100AFD0U) /**< \brief (MTB) Peripheral Identification 4 */ +#define REG_MTB_PID5 (0x4100AFD4U) /**< \brief (MTB) Peripheral Identification 5 */ +#define REG_MTB_PID6 (0x4100AFD8U) /**< \brief (MTB) Peripheral Identification 6 */ +#define REG_MTB_PID7 (0x4100AFDCU) /**< \brief (MTB) Peripheral Identification 7 */ +#define REG_MTB_PID0 (0x4100AFE0U) /**< \brief (MTB) Peripheral Identification 0 */ +#define REG_MTB_PID1 (0x4100AFE4U) /**< \brief (MTB) Peripheral Identification 1 */ +#define REG_MTB_PID2 (0x4100AFE8U) /**< \brief (MTB) Peripheral Identification 2 */ +#define REG_MTB_PID3 (0x4100AFECU) /**< \brief (MTB) Peripheral Identification 3 */ +#define REG_MTB_CID0 (0x4100AFF0U) /**< \brief (MTB) Component Identification 0 */ +#define REG_MTB_CID1 (0x4100AFF4U) /**< \brief (MTB) Component Identification 1 */ +#define REG_MTB_CID2 (0x4100AFF8U) /**< \brief (MTB) Component Identification 2 */ +#define REG_MTB_CID3 (0x4100AFFCU) /**< \brief (MTB) Component Identification 3 */ +#else +#define REG_MTB_POSITION (*(RwReg *)0x4100A000U) /**< \brief (MTB) MTB Position */ +#define REG_MTB_MASTER (*(RwReg *)0x4100A004U) /**< \brief (MTB) MTB Master */ +#define REG_MTB_FLOW (*(RwReg *)0x4100A008U) /**< \brief (MTB) MTB Flow */ +#define REG_MTB_BASE (*(RoReg *)0x4100A00CU) /**< \brief (MTB) MTB Base */ +#define REG_MTB_ITCTRL (*(RwReg *)0x4100AF00U) /**< \brief (MTB) MTB Integration Mode Control */ +#define REG_MTB_CLAIMSET (*(RwReg *)0x4100AFA0U) /**< \brief (MTB) MTB Claim Set */ +#define REG_MTB_CLAIMCLR (*(RwReg *)0x4100AFA4U) /**< \brief (MTB) MTB Claim Clear */ +#define REG_MTB_LOCKACCESS (*(RwReg *)0x4100AFB0U) /**< \brief (MTB) MTB Lock Access */ +#define REG_MTB_LOCKSTATUS (*(RoReg *)0x4100AFB4U) /**< \brief (MTB) MTB Lock Status */ +#define REG_MTB_AUTHSTATUS (*(RoReg *)0x4100AFB8U) /**< \brief (MTB) MTB Authentication Status */ +#define REG_MTB_DEVARCH (*(RoReg *)0x4100AFBCU) /**< \brief (MTB) MTB Device Architecture */ +#define REG_MTB_DEVID (*(RoReg *)0x4100AFC8U) /**< \brief (MTB) MTB Device Configuration */ +#define REG_MTB_DEVTYPE (*(RoReg *)0x4100AFCCU) /**< \brief (MTB) MTB Device Type */ +#define REG_MTB_PID4 (*(RoReg *)0x4100AFD0U) /**< \brief (MTB) Peripheral Identification 4 */ +#define REG_MTB_PID5 (*(RoReg *)0x4100AFD4U) /**< \brief (MTB) Peripheral Identification 5 */ +#define REG_MTB_PID6 (*(RoReg *)0x4100AFD8U) /**< \brief (MTB) Peripheral Identification 6 */ +#define REG_MTB_PID7 (*(RoReg *)0x4100AFDCU) /**< \brief (MTB) Peripheral Identification 7 */ +#define REG_MTB_PID0 (*(RoReg *)0x4100AFE0U) /**< \brief (MTB) Peripheral Identification 0 */ +#define REG_MTB_PID1 (*(RoReg *)0x4100AFE4U) /**< \brief (MTB) Peripheral Identification 1 */ +#define REG_MTB_PID2 (*(RoReg *)0x4100AFE8U) /**< \brief (MTB) Peripheral Identification 2 */ +#define REG_MTB_PID3 (*(RoReg *)0x4100AFECU) /**< \brief (MTB) Peripheral Identification 3 */ +#define REG_MTB_CID0 (*(RoReg *)0x4100AFF0U) /**< \brief (MTB) Component Identification 0 */ +#define REG_MTB_CID1 (*(RoReg *)0x4100AFF4U) /**< \brief (MTB) Component Identification 1 */ +#define REG_MTB_CID2 (*(RoReg *)0x4100AFF8U) /**< \brief (MTB) Component Identification 2 */ +#define REG_MTB_CID3 (*(RoReg *)0x4100AFFCU) /**< \brief (MTB) Component Identification 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAML22_MTB_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/nvmctrl.h b/Sensor Watch Starter Project/include/instance/nvmctrl.h new file mode 100755 index 00000000..6c3257b0 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/nvmctrl.h @@ -0,0 +1,94 @@ +/** + * \file + * + * \brief Instance description for NVMCTRL + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_NVMCTRL_INSTANCE_ +#define _SAML22_NVMCTRL_INSTANCE_ + +/* ========== Register definition for NVMCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */ +#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */ +#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ +#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ +#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ +#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ +#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */ +#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */ +#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */ +#else +#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */ +#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */ +#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ +#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ +#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ +#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ +#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */ +#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */ +#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for NVMCTRL peripheral ========== */ +#define NVMCTRL_AUX0_ADDRESS 0x00804000 +#define NVMCTRL_AUX1_ADDRESS 0x00806000 +#define NVMCTRL_AUX2_ADDRESS 0x00808000 +#define NVMCTRL_AUX3_ADDRESS 0x0080A000 +#define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register +#define NVMCTRL_CLK_AHB_ID_PICACHU 10 // Index of PICACHU AHB Clock +#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF +#define NVMCTRL_FLASH_SIZE 262144 +#define NVMCTRL_GCLK_ID 29 // Index of Generic Clock for test +#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 +#define NVMCTRL_USER_PAGE_OFFSET 0x00800000 +#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF +#define NVMCTRL_RWWEE_PAGES 128 +#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area + +#endif /* _SAML22_NVMCTRL_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/osc32kctrl.h b/Sensor Watch Starter Project/include/instance/osc32kctrl.h new file mode 100755 index 00000000..13660423 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/osc32kctrl.h @@ -0,0 +1,75 @@ +/** + * \file + * + * \brief Instance description for OSC32KCTRL + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_OSC32KCTRL_INSTANCE_ +#define _SAML22_OSC32KCTRL_INSTANCE_ + +/* ========== Register definition for OSC32KCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_OSC32KCTRL_INTENCLR (0x40001400U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ +#define REG_OSC32KCTRL_INTENSET (0x40001404U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ +#define REG_OSC32KCTRL_INTFLAG (0x40001408U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ +#define REG_OSC32KCTRL_STATUS (0x4000140CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */ +#define REG_OSC32KCTRL_RTCCTRL (0x40001410U) /**< \brief (OSC32KCTRL) RTC Clock Selection */ +#define REG_OSC32KCTRL_SLCDCTRL (0x40001411U) /**< \brief (OSC32KCTRL) SLCD Clock Selection */ +#define REG_OSC32KCTRL_XOSC32K (0x40001414U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_OSC32KCTRL_CFDCTRL (0x40001416U) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */ +#define REG_OSC32KCTRL_EVCTRL (0x40001417U) /**< \brief (OSC32KCTRL) Event Control */ +#define REG_OSC32KCTRL_OSCULP32K (0x4000141CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#else +#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001400U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ +#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001404U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ +#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001408U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ +#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000140CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */ +#define REG_OSC32KCTRL_RTCCTRL (*(RwReg8 *)0x40001410U) /**< \brief (OSC32KCTRL) RTC Clock Selection */ +#define REG_OSC32KCTRL_SLCDCTRL (*(RwReg8 *)0x40001411U) /**< \brief (OSC32KCTRL) SLCD Clock Selection */ +#define REG_OSC32KCTRL_XOSC32K (*(RwReg16*)0x40001414U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_OSC32KCTRL_CFDCTRL (*(RwReg8 *)0x40001416U) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */ +#define REG_OSC32KCTRL_EVCTRL (*(RwReg8 *)0x40001417U) /**< \brief (OSC32KCTRL) Event Control */ +#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000141CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for OSC32KCTRL peripheral ========== */ +#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6 + +#endif /* _SAML22_OSC32KCTRL_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/oscctrl.h b/Sensor Watch Starter Project/include/instance/oscctrl.h new file mode 100755 index 00000000..c0bd0b5e --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/oscctrl.h @@ -0,0 +1,100 @@ +/** + * \file + * + * \brief Instance description for OSCCTRL + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_OSCCTRL_INSTANCE_ +#define _SAML22_OSCCTRL_INSTANCE_ + +/* ========== Register definition for OSCCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_OSCCTRL_INTENCLR (0x40001000U) /**< \brief (OSCCTRL) Interrupt Enable Clear */ +#define REG_OSCCTRL_INTENSET (0x40001004U) /**< \brief (OSCCTRL) Interrupt Enable Set */ +#define REG_OSCCTRL_INTFLAG (0x40001008U) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ +#define REG_OSCCTRL_STATUS (0x4000100CU) /**< \brief (OSCCTRL) Power and Clocks Status */ +#define REG_OSCCTRL_XOSCCTRL (0x40001010U) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_OSCCTRL_CFDPRESC (0x40001012U) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */ +#define REG_OSCCTRL_EVCTRL (0x40001013U) /**< \brief (OSCCTRL) Event Control */ +#define REG_OSCCTRL_OSC16MCTRL (0x40001014U) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ +#define REG_OSCCTRL_DFLLCTRL (0x40001018U) /**< \brief (OSCCTRL) DFLL48M Control */ +#define REG_OSCCTRL_DFLLVAL (0x4000101CU) /**< \brief (OSCCTRL) DFLL48M Value */ +#define REG_OSCCTRL_DFLLMUL (0x40001020U) /**< \brief (OSCCTRL) DFLL48M Multiplier */ +#define REG_OSCCTRL_DFLLSYNC (0x40001024U) /**< \brief (OSCCTRL) DFLL48M Synchronization */ +#define REG_OSCCTRL_DPLLCTRLA (0x40001028U) /**< \brief (OSCCTRL) DPLL Control */ +#define REG_OSCCTRL_DPLLRATIO (0x4000102CU) /**< \brief (OSCCTRL) DPLL Ratio Control */ +#define REG_OSCCTRL_DPLLCTRLB (0x40001030U) /**< \brief (OSCCTRL) Digital Core Configuration */ +#define REG_OSCCTRL_DPLLPRESC (0x40001034U) /**< \brief (OSCCTRL) DPLL Prescaler */ +#define REG_OSCCTRL_DPLLSYNCBUSY (0x40001038U) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ +#define REG_OSCCTRL_DPLLSTATUS (0x4000103CU) /**< \brief (OSCCTRL) DPLL Status */ +#else +#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001000U) /**< \brief (OSCCTRL) Interrupt Enable Clear */ +#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001004U) /**< \brief (OSCCTRL) Interrupt Enable Set */ +#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40001008U) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ +#define REG_OSCCTRL_STATUS (*(RoReg *)0x4000100CU) /**< \brief (OSCCTRL) Power and Clocks Status */ +#define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40001010U) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_OSCCTRL_CFDPRESC (*(RwReg8 *)0x40001012U) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */ +#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001013U) /**< \brief (OSCCTRL) Event Control */ +#define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40001014U) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ +#define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40001018U) /**< \brief (OSCCTRL) DFLL48M Control */ +#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x4000101CU) /**< \brief (OSCCTRL) DFLL48M Value */ +#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001020U) /**< \brief (OSCCTRL) DFLL48M Multiplier */ +#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40001024U) /**< \brief (OSCCTRL) DFLL48M Synchronization */ +#define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40001028U) /**< \brief (OSCCTRL) DPLL Control */ +#define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x4000102CU) /**< \brief (OSCCTRL) DPLL Ratio Control */ +#define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40001030U) /**< \brief (OSCCTRL) Digital Core Configuration */ +#define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40001034U) /**< \brief (OSCCTRL) DPLL Prescaler */ +#define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40001038U) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ +#define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x4000103CU) /**< \brief (OSCCTRL) DPLL Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for OSCCTRL peripheral ========== */ +#define OSCCTRL_DFLL48M_COARSE_MSB 5 +#define OSCCTRL_DFLL48M_FINE_MSB 9 +#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 +#define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL +#define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K +#define OSCCTRL_CFD_VERSION 0x100 +#define OSCCTRL_DFLL48M_VERSION 0x320 +#define OSCCTRL_FDPLL_VERSION 0x211 +#define OSCCTRL_OSC16M_VERSION 0x101 +#define OSCCTRL_XOSC_VERSION 0x201 + +#endif /* _SAML22_OSCCTRL_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/pac.h b/Sensor Watch Starter Project/include/instance/pac.h new file mode 100755 index 00000000..22593a03 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/pac.h @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief Instance description for PAC + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_PAC_INSTANCE_ +#define _SAML22_PAC_INSTANCE_ + +/* ========== Register definition for PAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC_WRCTRL (0x40000000U) /**< \brief (PAC) Write control */ +#define REG_PAC_EVCTRL (0x40000004U) /**< \brief (PAC) Event control */ +#define REG_PAC_INTENCLR (0x40000008U) /**< \brief (PAC) Interrupt enable clear */ +#define REG_PAC_INTENSET (0x40000009U) /**< \brief (PAC) Interrupt enable set */ +#define REG_PAC_INTFLAGAHB (0x40000010U) /**< \brief (PAC) Bridge interrupt flag status */ +#define REG_PAC_INTFLAGA (0x40000014U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ +#define REG_PAC_INTFLAGB (0x40000018U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ +#define REG_PAC_INTFLAGC (0x4000001CU) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ +#define REG_PAC_STATUSA (0x40000034U) /**< \brief (PAC) Peripheral write protection status - Bridge A */ +#define REG_PAC_STATUSB (0x40000038U) /**< \brief (PAC) Peripheral write protection status - Bridge B */ +#define REG_PAC_STATUSC (0x4000003CU) /**< \brief (PAC) Peripheral write protection status - Bridge C */ +#else +#define REG_PAC_WRCTRL (*(RwReg *)0x40000000U) /**< \brief (PAC) Write control */ +#define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004U) /**< \brief (PAC) Event control */ +#define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008U) /**< \brief (PAC) Interrupt enable clear */ +#define REG_PAC_INTENSET (*(RwReg8 *)0x40000009U) /**< \brief (PAC) Interrupt enable set */ +#define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010U) /**< \brief (PAC) Bridge interrupt flag status */ +#define REG_PAC_INTFLAGA (*(RwReg *)0x40000014U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ +#define REG_PAC_INTFLAGB (*(RwReg *)0x40000018U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ +#define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CU) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ +#define REG_PAC_STATUSA (*(RoReg *)0x40000034U) /**< \brief (PAC) Peripheral write protection status - Bridge A */ +#define REG_PAC_STATUSB (*(RoReg *)0x40000038U) /**< \brief (PAC) Peripheral write protection status - Bridge B */ +#define REG_PAC_STATUSC (*(RoReg *)0x4000003CU) /**< \brief (PAC) Peripheral write protection status - Bridge C */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC peripheral ========== */ +#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock +#define PAC_CLK_AHB_ID 7 // AHB clock index +#define PAC_HPB_NUM 3 // Number of bridges AHB/APB +#define PAC_INTFLAG_NUM 4 // Number of intflag registers + +#endif /* _SAML22_PAC_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/pm.h b/Sensor Watch Starter Project/include/instance/pm.h new file mode 100755 index 00000000..e3637a45 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/pm.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Instance description for PM + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_PM_INSTANCE_ +#define _SAML22_PM_INSTANCE_ + +/* ========== Register definition for PM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PM_CTRLA (0x40000400U) /**< \brief (PM) Control A */ +#define REG_PM_SLEEPCFG (0x40000401U) /**< \brief (PM) Sleep Configuration */ +#define REG_PM_PLCFG (0x40000402U) /**< \brief (PM) Performance Level Configuration */ +#define REG_PM_INTENCLR (0x40000404U) /**< \brief (PM) Interrupt Enable Clear */ +#define REG_PM_INTENSET (0x40000405U) /**< \brief (PM) Interrupt Enable Set */ +#define REG_PM_INTFLAG (0x40000406U) /**< \brief (PM) Interrupt Flag Status and Clear */ +#define REG_PM_STDBYCFG (0x40000408U) /**< \brief (PM) Standby Configuration */ +#else +#define REG_PM_CTRLA (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control A */ +#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Configuration */ +#define REG_PM_PLCFG (*(RwReg8 *)0x40000402U) /**< \brief (PM) Performance Level Configuration */ +#define REG_PM_INTENCLR (*(RwReg8 *)0x40000404U) /**< \brief (PM) Interrupt Enable Clear */ +#define REG_PM_INTENSET (*(RwReg8 *)0x40000405U) /**< \brief (PM) Interrupt Enable Set */ +#define REG_PM_INTFLAG (*(RwReg8 *)0x40000406U) /**< \brief (PM) Interrupt Flag Status and Clear */ +#define REG_PM_STDBYCFG (*(RwReg16*)0x40000408U) /**< \brief (PM) Standby Configuration */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PM peripheral ========== */ +#define PM_BIAS_RAM_HS 1 // one if RAM HS can be back biased +#define PM_PD_NUM 0 // Number of switchable Power Domain + +#endif /* _SAML22_PM_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/port.h b/Sensor Watch Starter Project/include/instance/port.h new file mode 100755 index 00000000..95a50484 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/port.h @@ -0,0 +1,169 @@ +/** + * \file + * + * \brief Instance description for PORT + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_PORT_INSTANCE_ +#define _SAML22_PORT_INSTANCE_ + +/* ========== Register definition for PORT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PORT_DIR0 (0x41006000U) /**< \brief (PORT) Data Direction 0 */ +#define REG_PORT_DIRCLR0 (0x41006004U) /**< \brief (PORT) Data Direction Clear 0 */ +#define REG_PORT_DIRSET0 (0x41006008U) /**< \brief (PORT) Data Direction Set 0 */ +#define REG_PORT_DIRTGL0 (0x4100600CU) /**< \brief (PORT) Data Direction Toggle 0 */ +#define REG_PORT_OUT0 (0x41006010U) /**< \brief (PORT) Data Output Value 0 */ +#define REG_PORT_OUTCLR0 (0x41006014U) /**< \brief (PORT) Data Output Value Clear 0 */ +#define REG_PORT_OUTSET0 (0x41006018U) /**< \brief (PORT) Data Output Value Set 0 */ +#define REG_PORT_OUTTGL0 (0x4100601CU) /**< \brief (PORT) Data Output Value Toggle 0 */ +#define REG_PORT_IN0 (0x41006020U) /**< \brief (PORT) Data Input Value 0 */ +#define REG_PORT_CTRL0 (0x41006024U) /**< \brief (PORT) Control 0 */ +#define REG_PORT_WRCONFIG0 (0x41006028U) /**< \brief (PORT) Write Configuration 0 */ +#define REG_PORT_EVCTRL0 (0x4100602CU) /**< \brief (PORT) Event Input Control 0 */ +#define REG_PORT_PMUX0 (0x41006030U) /**< \brief (PORT) Peripheral Multiplexing 0 */ +#define REG_PORT_PINCFG0 (0x41006040U) /**< \brief (PORT) Pin Configuration 0 */ +#define REG_PORT_DIR1 (0x41006080U) /**< \brief (PORT) Data Direction 1 */ +#define REG_PORT_DIRCLR1 (0x41006084U) /**< \brief (PORT) Data Direction Clear 1 */ +#define REG_PORT_DIRSET1 (0x41006088U) /**< \brief (PORT) Data Direction Set 1 */ +#define REG_PORT_DIRTGL1 (0x4100608CU) /**< \brief (PORT) Data Direction Toggle 1 */ +#define REG_PORT_OUT1 (0x41006090U) /**< \brief (PORT) Data Output Value 1 */ +#define REG_PORT_OUTCLR1 (0x41006094U) /**< \brief (PORT) Data Output Value Clear 1 */ +#define REG_PORT_OUTSET1 (0x41006098U) /**< \brief (PORT) Data Output Value Set 1 */ +#define REG_PORT_OUTTGL1 (0x4100609CU) /**< \brief (PORT) Data Output Value Toggle 1 */ +#define REG_PORT_IN1 (0x410060A0U) /**< \brief (PORT) Data Input Value 1 */ +#define REG_PORT_CTRL1 (0x410060A4U) /**< \brief (PORT) Control 1 */ +#define REG_PORT_WRCONFIG1 (0x410060A8U) /**< \brief (PORT) Write Configuration 1 */ +#define REG_PORT_EVCTRL1 (0x410060ACU) /**< \brief (PORT) Event Input Control 1 */ +#define REG_PORT_PMUX1 (0x410060B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */ +#define REG_PORT_PINCFG1 (0x410060C0U) /**< \brief (PORT) Pin Configuration 1 */ +#define REG_PORT_DIR2 (0x41006100U) /**< \brief (PORT) Data Direction 2 */ +#define REG_PORT_DIRCLR2 (0x41006104U) /**< \brief (PORT) Data Direction Clear 2 */ +#define REG_PORT_DIRSET2 (0x41006108U) /**< \brief (PORT) Data Direction Set 2 */ +#define REG_PORT_DIRTGL2 (0x4100610CU) /**< \brief (PORT) Data Direction Toggle 2 */ +#define REG_PORT_OUT2 (0x41006110U) /**< \brief (PORT) Data Output Value 2 */ +#define REG_PORT_OUTCLR2 (0x41006114U) /**< \brief (PORT) Data Output Value Clear 2 */ +#define REG_PORT_OUTSET2 (0x41006118U) /**< \brief (PORT) Data Output Value Set 2 */ +#define REG_PORT_OUTTGL2 (0x4100611CU) /**< \brief (PORT) Data Output Value Toggle 2 */ +#define REG_PORT_IN2 (0x41006120U) /**< \brief (PORT) Data Input Value 2 */ +#define REG_PORT_CTRL2 (0x41006124U) /**< \brief (PORT) Control 2 */ +#define REG_PORT_WRCONFIG2 (0x41006128U) /**< \brief (PORT) Write Configuration 2 */ +#define REG_PORT_EVCTRL2 (0x4100612CU) /**< \brief (PORT) Event Input Control 2 */ +#define REG_PORT_PMUX2 (0x41006130U) /**< \brief (PORT) Peripheral Multiplexing 2 */ +#define REG_PORT_PINCFG2 (0x41006140U) /**< \brief (PORT) Pin Configuration 2 */ +#else +#define REG_PORT_DIR0 (*(RwReg *)0x41006000U) /**< \brief (PORT) Data Direction 0 */ +#define REG_PORT_DIRCLR0 (*(RwReg *)0x41006004U) /**< \brief (PORT) Data Direction Clear 0 */ +#define REG_PORT_DIRSET0 (*(RwReg *)0x41006008U) /**< \brief (PORT) Data Direction Set 0 */ +#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100600CU) /**< \brief (PORT) Data Direction Toggle 0 */ +#define REG_PORT_OUT0 (*(RwReg *)0x41006010U) /**< \brief (PORT) Data Output Value 0 */ +#define REG_PORT_OUTCLR0 (*(RwReg *)0x41006014U) /**< \brief (PORT) Data Output Value Clear 0 */ +#define REG_PORT_OUTSET0 (*(RwReg *)0x41006018U) /**< \brief (PORT) Data Output Value Set 0 */ +#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100601CU) /**< \brief (PORT) Data Output Value Toggle 0 */ +#define REG_PORT_IN0 (*(RoReg *)0x41006020U) /**< \brief (PORT) Data Input Value 0 */ +#define REG_PORT_CTRL0 (*(RwReg *)0x41006024U) /**< \brief (PORT) Control 0 */ +#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41006028U) /**< \brief (PORT) Write Configuration 0 */ +#define REG_PORT_EVCTRL0 (*(RwReg *)0x4100602CU) /**< \brief (PORT) Event Input Control 0 */ +#define REG_PORT_PMUX0 (*(RwReg *)0x41006030U) /**< \brief (PORT) Peripheral Multiplexing 0 */ +#define REG_PORT_PINCFG0 (*(RwReg *)0x41006040U) /**< \brief (PORT) Pin Configuration 0 */ +#define REG_PORT_DIR1 (*(RwReg *)0x41006080U) /**< \brief (PORT) Data Direction 1 */ +#define REG_PORT_DIRCLR1 (*(RwReg *)0x41006084U) /**< \brief (PORT) Data Direction Clear 1 */ +#define REG_PORT_DIRSET1 (*(RwReg *)0x41006088U) /**< \brief (PORT) Data Direction Set 1 */ +#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100608CU) /**< \brief (PORT) Data Direction Toggle 1 */ +#define REG_PORT_OUT1 (*(RwReg *)0x41006090U) /**< \brief (PORT) Data Output Value 1 */ +#define REG_PORT_OUTCLR1 (*(RwReg *)0x41006094U) /**< \brief (PORT) Data Output Value Clear 1 */ +#define REG_PORT_OUTSET1 (*(RwReg *)0x41006098U) /**< \brief (PORT) Data Output Value Set 1 */ +#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100609CU) /**< \brief (PORT) Data Output Value Toggle 1 */ +#define REG_PORT_IN1 (*(RoReg *)0x410060A0U) /**< \brief (PORT) Data Input Value 1 */ +#define REG_PORT_CTRL1 (*(RwReg *)0x410060A4U) /**< \brief (PORT) Control 1 */ +#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410060A8U) /**< \brief (PORT) Write Configuration 1 */ +#define REG_PORT_EVCTRL1 (*(RwReg *)0x410060ACU) /**< \brief (PORT) Event Input Control 1 */ +#define REG_PORT_PMUX1 (*(RwReg *)0x410060B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */ +#define REG_PORT_PINCFG1 (*(RwReg *)0x410060C0U) /**< \brief (PORT) Pin Configuration 1 */ +#define REG_PORT_DIR2 (*(RwReg *)0x41006100U) /**< \brief (PORT) Data Direction 2 */ +#define REG_PORT_DIRCLR2 (*(RwReg *)0x41006104U) /**< \brief (PORT) Data Direction Clear 2 */ +#define REG_PORT_DIRSET2 (*(RwReg *)0x41006108U) /**< \brief (PORT) Data Direction Set 2 */ +#define REG_PORT_DIRTGL2 (*(RwReg *)0x4100610CU) /**< \brief (PORT) Data Direction Toggle 2 */ +#define REG_PORT_OUT2 (*(RwReg *)0x41006110U) /**< \brief (PORT) Data Output Value 2 */ +#define REG_PORT_OUTCLR2 (*(RwReg *)0x41006114U) /**< \brief (PORT) Data Output Value Clear 2 */ +#define REG_PORT_OUTSET2 (*(RwReg *)0x41006118U) /**< \brief (PORT) Data Output Value Set 2 */ +#define REG_PORT_OUTTGL2 (*(RwReg *)0x4100611CU) /**< \brief (PORT) Data Output Value Toggle 2 */ +#define REG_PORT_IN2 (*(RoReg *)0x41006120U) /**< \brief (PORT) Data Input Value 2 */ +#define REG_PORT_CTRL2 (*(RwReg *)0x41006124U) /**< \brief (PORT) Control 2 */ +#define REG_PORT_WRCONFIG2 (*(WoReg *)0x41006128U) /**< \brief (PORT) Write Configuration 2 */ +#define REG_PORT_EVCTRL2 (*(RwReg *)0x4100612CU) /**< \brief (PORT) Event Input Control 2 */ +#define REG_PORT_PMUX2 (*(RwReg *)0x41006130U) /**< \brief (PORT) Peripheral Multiplexing 2 */ +#define REG_PORT_PINCFG2 (*(RwReg *)0x41006140U) /**< \brief (PORT) Pin Configuration 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PORT peripheral ========== */ +#define PORT_BITS 93 +#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_DIR_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_DRVSTR 1 // DRVSTR supported +#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_DRVSTR_IMPLEMENTED { 0xC8FFFFFF, 0xC3FFFBFF, 0x1F3FF0EF } +#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F03F0EF } +#define PORT_EV_NUM 4 +#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_INEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_ODRAIN 0 // ODRAIN supported +#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_OUT_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_PIN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_PMUXBIT0_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } +#define PORT_PMUXBIT1_IMPLEMENTED { 0xCBFFFFF7, 0xC3FFFB0F, 0x1B003C03 } +#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } +#define PORT_PMUXBIT2_IMPLEMENTED { 0x4BFFFF34, 0xC3FFFB0F, 0x1F000003 } +#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_PMUXBIT3_IMPLEMENTED { 0xC3CF0FF0, 0x00C3CBC7, 0x18300000 } +#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } +#define PORT_PMUXEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_PULLEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_SLEWLIM 0 // SLEWLIM supported +#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } + +#endif /* _SAML22_PORT_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/rstc.h b/Sensor Watch Starter Project/include/instance/rstc.h new file mode 100755 index 00000000..8ab6a147 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/rstc.h @@ -0,0 +1,60 @@ +/** + * \file + * + * \brief Instance description for RSTC + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_RSTC_INSTANCE_ +#define _SAML22_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RSTC_RCAUSE (0x40000C00U) /**< \brief (RSTC) Reset Cause */ +#define REG_RSTC_BKUPEXIT (0x40000C02U) /**< \brief (RSTC) Backup Exit Source */ +#else +#define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000C00U) /**< \brief (RSTC) Reset Cause */ +#define REG_RSTC_BKUPEXIT (*(RoReg8 *)0x40000C02U) /**< \brief (RSTC) Backup Exit Source */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for RSTC peripheral ========== */ +#define RSTC_BACKUP_IMPLEMENTED 1 +#define RSTC_NUMBER_OF_EXTWAKE 0 // number of external wakeup line + +#endif /* _SAML22_RSTC_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/rtc.h b/Sensor Watch Starter Project/include/instance/rtc.h new file mode 100755 index 00000000..b1e3a0d4 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/rtc.h @@ -0,0 +1,156 @@ +/** + * \file + * + * \brief Instance description for RTC + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_RTC_INSTANCE_ +#define _SAML22_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_DBGCTRL (0x4000240EU) /**< \brief (RTC) Debug Control */ +#define REG_RTC_FREQCORR (0x40002414U) /**< \brief (RTC) Frequency Correction */ +#define REG_RTC_GP0 (0x40002440U) /**< \brief (RTC) General Purpose 0 */ +#define REG_RTC_GP1 (0x40002444U) /**< \brief (RTC) General Purpose 1 */ +#define REG_RTC_TAMPCTRL (0x40002460U) /**< \brief (RTC) Tamper Control */ +#define REG_RTC_TAMPID (0x40002468U) /**< \brief (RTC) Tamper ID */ +#define REG_RTC_BKUP0 (0x40002480U) /**< \brief (RTC) Backup 0 */ +#define REG_RTC_BKUP1 (0x40002484U) /**< \brief (RTC) Backup 1 */ +#define REG_RTC_BKUP2 (0x40002488U) /**< \brief (RTC) Backup 2 */ +#define REG_RTC_BKUP3 (0x4000248CU) /**< \brief (RTC) Backup 3 */ +#define REG_RTC_BKUP4 (0x40002490U) /**< \brief (RTC) Backup 4 */ +#define REG_RTC_BKUP5 (0x40002494U) /**< \brief (RTC) Backup 5 */ +#define REG_RTC_BKUP6 (0x40002498U) /**< \brief (RTC) Backup 6 */ +#define REG_RTC_BKUP7 (0x4000249CU) /**< \brief (RTC) Backup 7 */ +#define REG_RTC_MODE0_CTRLA (0x40002400U) /**< \brief (RTC) MODE0 Control A */ +#define REG_RTC_MODE0_CTRLB (0x40002402U) /**< \brief (RTC) MODE0 Control B */ +#define REG_RTC_MODE0_EVCTRL (0x40002404U) /**< \brief (RTC) MODE0 Event Control */ +#define REG_RTC_MODE0_INTENCLR (0x40002408U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ +#define REG_RTC_MODE0_INTENSET (0x4000240AU) /**< \brief (RTC) MODE0 Interrupt Enable Set */ +#define REG_RTC_MODE0_INTFLAG (0x4000240CU) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE0_SYNCBUSY (0x40002410U) /**< \brief (RTC) MODE0 Synchronization Busy Status */ +#define REG_RTC_MODE0_COUNT (0x40002418U) /**< \brief (RTC) MODE0 Counter Value */ +#define REG_RTC_MODE0_COMP0 (0x40002420U) /**< \brief (RTC) MODE0 Compare 0 Value */ +#define REG_RTC_MODE0_TIMESTAMP (0x40002464U) /**< \brief (RTC) MODE0 Timestamp */ +#define REG_RTC_MODE1_CTRLA (0x40002400U) /**< \brief (RTC) MODE1 Control A */ +#define REG_RTC_MODE1_CTRLB (0x40002402U) /**< \brief (RTC) MODE1 Control B */ +#define REG_RTC_MODE1_EVCTRL (0x40002404U) /**< \brief (RTC) MODE1 Event Control */ +#define REG_RTC_MODE1_INTENCLR (0x40002408U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ +#define REG_RTC_MODE1_INTENSET (0x4000240AU) /**< \brief (RTC) MODE1 Interrupt Enable Set */ +#define REG_RTC_MODE1_INTFLAG (0x4000240CU) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE1_SYNCBUSY (0x40002410U) /**< \brief (RTC) MODE1 Synchronization Busy Status */ +#define REG_RTC_MODE1_COUNT (0x40002418U) /**< \brief (RTC) MODE1 Counter Value */ +#define REG_RTC_MODE1_PER (0x4000241CU) /**< \brief (RTC) MODE1 Counter Period */ +#define REG_RTC_MODE1_COMP0 (0x40002420U) /**< \brief (RTC) MODE1 Compare 0 Value */ +#define REG_RTC_MODE1_COMP1 (0x40002422U) /**< \brief (RTC) MODE1 Compare 1 Value */ +#define REG_RTC_MODE1_TIMESTAMP (0x40002464U) /**< \brief (RTC) MODE1 Timestamp */ +#define REG_RTC_MODE2_CTRLA (0x40002400U) /**< \brief (RTC) MODE2 Control A */ +#define REG_RTC_MODE2_CTRLB (0x40002402U) /**< \brief (RTC) MODE2 Control B */ +#define REG_RTC_MODE2_EVCTRL (0x40002404U) /**< \brief (RTC) MODE2 Event Control */ +#define REG_RTC_MODE2_INTENCLR (0x40002408U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ +#define REG_RTC_MODE2_INTENSET (0x4000240AU) /**< \brief (RTC) MODE2 Interrupt Enable Set */ +#define REG_RTC_MODE2_INTFLAG (0x4000240CU) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE2_SYNCBUSY (0x40002410U) /**< \brief (RTC) MODE2 Synchronization Busy Status */ +#define REG_RTC_MODE2_CLOCK (0x40002418U) /**< \brief (RTC) MODE2 Clock Value */ +#define REG_RTC_MODE2_TIMESTAMP (0x40002464U) /**< \brief (RTC) MODE2 Timestamp */ +#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ +#define REG_RTC_MODE2_ALARM_MASK0 (0x40002424U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ +#else +#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EU) /**< \brief (RTC) Debug Control */ +#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414U) /**< \brief (RTC) Frequency Correction */ +#define REG_RTC_GP0 (*(RwReg *)0x40002440U) /**< \brief (RTC) General Purpose 0 */ +#define REG_RTC_GP1 (*(RwReg *)0x40002444U) /**< \brief (RTC) General Purpose 1 */ +#define REG_RTC_TAMPCTRL (*(RwReg *)0x40002460U) /**< \brief (RTC) Tamper Control */ +#define REG_RTC_TAMPID (*(RwReg *)0x40002468U) /**< \brief (RTC) Tamper ID */ +#define REG_RTC_BKUP0 (*(RwReg *)0x40002480U) /**< \brief (RTC) Backup 0 */ +#define REG_RTC_BKUP1 (*(RwReg *)0x40002484U) /**< \brief (RTC) Backup 1 */ +#define REG_RTC_BKUP2 (*(RwReg *)0x40002488U) /**< \brief (RTC) Backup 2 */ +#define REG_RTC_BKUP3 (*(RwReg *)0x4000248CU) /**< \brief (RTC) Backup 3 */ +#define REG_RTC_BKUP4 (*(RwReg *)0x40002490U) /**< \brief (RTC) Backup 4 */ +#define REG_RTC_BKUP5 (*(RwReg *)0x40002494U) /**< \brief (RTC) Backup 5 */ +#define REG_RTC_BKUP6 (*(RwReg *)0x40002498U) /**< \brief (RTC) Backup 6 */ +#define REG_RTC_BKUP7 (*(RwReg *)0x4000249CU) /**< \brief (RTC) Backup 7 */ +#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400U) /**< \brief (RTC) MODE0 Control A */ +#define REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402U) /**< \brief (RTC) MODE0 Control B */ +#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404U) /**< \brief (RTC) MODE0 Event Control */ +#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ +#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AU) /**< \brief (RTC) MODE0 Interrupt Enable Set */ +#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CU) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410U) /**< \brief (RTC) MODE0 Synchronization Busy Status */ +#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418U) /**< \brief (RTC) MODE0 Counter Value */ +#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420U) /**< \brief (RTC) MODE0 Compare 0 Value */ +#define REG_RTC_MODE0_TIMESTAMP (*(RoReg *)0x40002464U) /**< \brief (RTC) MODE0 Timestamp */ +#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400U) /**< \brief (RTC) MODE1 Control A */ +#define REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402U) /**< \brief (RTC) MODE1 Control B */ +#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404U) /**< \brief (RTC) MODE1 Event Control */ +#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ +#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AU) /**< \brief (RTC) MODE1 Interrupt Enable Set */ +#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CU) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410U) /**< \brief (RTC) MODE1 Synchronization Busy Status */ +#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418U) /**< \brief (RTC) MODE1 Counter Value */ +#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CU) /**< \brief (RTC) MODE1 Counter Period */ +#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420U) /**< \brief (RTC) MODE1 Compare 0 Value */ +#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422U) /**< \brief (RTC) MODE1 Compare 1 Value */ +#define REG_RTC_MODE1_TIMESTAMP (*(RoReg *)0x40002464U) /**< \brief (RTC) MODE1 Timestamp */ +#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400U) /**< \brief (RTC) MODE2 Control A */ +#define REG_RTC_MODE2_CTRLB (*(RwReg16*)0x40002402U) /**< \brief (RTC) MODE2 Control B */ +#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404U) /**< \brief (RTC) MODE2 Event Control */ +#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ +#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AU) /**< \brief (RTC) MODE2 Interrupt Enable Set */ +#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CU) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410U) /**< \brief (RTC) MODE2 Synchronization Busy Status */ +#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418U) /**< \brief (RTC) MODE2 Clock Value */ +#define REG_RTC_MODE2_TIMESTAMP (*(RoReg *)0x40002464U) /**< \brief (RTC) MODE2 Timestamp */ +#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ +#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x40002424U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for RTC peripheral ========== */ +#define RTC_ALARM_NUM 1 // Number of Alarms +#define RTC_BKUP_NUM 8 // Number of Backup Registers +#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators +#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators +#define RTC_DMAC_ID_TIMESTAMP 1 // DMA RTC timestamp trigger +#define RTC_GPR_NUM 2 // Number of General-Purpose Registers +#define RTC_PER_NUM 8 // Number of Periodic Intervals +#define RTC_TAMPER_NUM 5 // Number of Tamper Inputs + +#endif /* _SAML22_RTC_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/sercom0.h b/Sensor Watch Starter Project/include/instance/sercom0.h new file mode 100755 index 00000000..0eb9f52b --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom0.h @@ -0,0 +1,156 @@ +/** + * \file + * + * \brief Instance description for SERCOM0 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM0_INSTANCE_ +#define _SAML22_SERCOM0_INSTANCE_ + +/* ========== Register definition for SERCOM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM0_I2CM_CTRLA (0x42000400U) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (0x42000404U) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (0x4200040CU) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (0x42000414U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (0x42000416U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (0x42000418U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (0x4200041AU) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */ +#define REG_SERCOM0_I2CM_ADDR (0x42000424U) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (0x42000428U) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (0x42000430U) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (0x42000400U) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (0x42000404U) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (0x42000414U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (0x42000416U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (0x42000418U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (0x4200041AU) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */ +#define REG_SERCOM0_I2CS_ADDR (0x42000424U) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (0x42000428U) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (0x42000400U) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (0x42000404U) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (0x4200040CU) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (0x42000414U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (0x42000416U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (0x42000418U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (0x4200041AU) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM0) SPI Synchronization Busy */ +#define REG_SERCOM0_SPI_ADDR (0x42000424U) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (0x42000428U) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (0x42000430U) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (0x42000400U) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (0x42000404U) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_CTRLC (0x42000408U) /**< \brief (SERCOM0) USART Control C */ +#define REG_SERCOM0_USART_BAUD (0x4200040CU) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (0x4200040EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (0x42000414U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (0x42000416U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (0x42000418U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (0x4200041AU) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM0) USART Synchronization Busy */ +#define REG_SERCOM0_USART_RXERRCNT (0x42000420U) /**< \brief (SERCOM0) USART Receive Error Count */ +#define REG_SERCOM0_USART_DATA (0x42000428U) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (0x42000430U) /**< \brief (SERCOM0) USART Debug Control */ +#else +#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200040CU) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */ +#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000428U) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */ +#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000428U) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200040CU) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM0) SPI Synchronization Busy */ +#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000428U) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_CTRLC (*(RwReg *)0x42000408U) /**< \brief (SERCOM0) USART Control C */ +#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200040CU) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200040EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM0) USART Synchronization Busy */ +#define REG_SERCOM0_USART_RXERRCNT (*(RoReg8 *)0x42000420U) /**< \brief (SERCOM0) USART Receive Error Count */ +#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000428U) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM0) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM0 peripheral ========== */ +#define SERCOM0_DMAC_ID_RX 2 // Index of DMA RX trigger +#define SERCOM0_DMAC_ID_TX 3 // Index of DMA TX trigger +#define SERCOM0_GCLK_ID_CORE 16 +#define SERCOM0_GCLK_ID_SLOW 15 +#define SERCOM0_INT_MSB 6 +#define SERCOM0_PMSB 3 +#define SERCOM0_SPI 1 // SPI mode implemented? +#define SERCOM0_TWIM 0 // TWI Master mode implemented? +#define SERCOM0_TWIS 0 // TWI Slave mode implemented? +#define SERCOM0_TWI_HSMODE 0 // TWI HighSpeed mode implemented? +#define SERCOM0_USART 1 // USART mode implemented? +#define SERCOM0_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM0_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM0_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM0_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/sercom1.h b/Sensor Watch Starter Project/include/instance/sercom1.h new file mode 100755 index 00000000..85ad084b --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom1.h @@ -0,0 +1,156 @@ +/** + * \file + * + * \brief Instance description for SERCOM1 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM1_INSTANCE_ +#define _SAML22_SERCOM1_INSTANCE_ + +/* ========== Register definition for SERCOM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM1_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */ +#define REG_SERCOM1_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (0x42000828U) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */ +#define REG_SERCOM1_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (0x42000828U) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM1) SPI Synchronization Busy */ +#define REG_SERCOM1_SPI_ADDR (0x42000824U) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (0x42000828U) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (0x42000800U) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (0x42000804U) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_CTRLC (0x42000808U) /**< \brief (SERCOM1) USART Control C */ +#define REG_SERCOM1_USART_BAUD (0x4200080CU) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (0x4200080EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (0x42000816U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (0x4200081AU) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM1) USART Synchronization Busy */ +#define REG_SERCOM1_USART_RXERRCNT (0x42000820U) /**< \brief (SERCOM1) USART Receive Error Count */ +#define REG_SERCOM1_USART_DATA (0x42000828U) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM1) USART Debug Control */ +#else +#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */ +#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */ +#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM1) SPI Synchronization Busy */ +#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x42000808U) /**< \brief (SERCOM1) USART Control C */ +#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM1) USART Synchronization Busy */ +#define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x42000820U) /**< \brief (SERCOM1) USART Receive Error Count */ +#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM1) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM1 peripheral ========== */ +#define SERCOM1_DMAC_ID_RX 4 // Index of DMA RX trigger +#define SERCOM1_DMAC_ID_TX 5 // Index of DMA TX trigger +#define SERCOM1_GCLK_ID_CORE 17 +#define SERCOM1_GCLK_ID_SLOW 15 +#define SERCOM1_INT_MSB 6 +#define SERCOM1_PMSB 3 +#define SERCOM1_SPI 1 // SPI mode implemented? +#define SERCOM1_TWIM 1 // TWI Master mode implemented? +#define SERCOM1_TWIS 1 // TWI Slave mode implemented? +#define SERCOM1_TWI_HSMODE 1 // TWI HighSpeed mode implemented? +#define SERCOM1_USART 1 // USART mode implemented? +#define SERCOM1_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM1_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM1_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM1_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/sercom2.h b/Sensor Watch Starter Project/include/instance/sercom2.h new file mode 100755 index 00000000..da68d71f --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom2.h @@ -0,0 +1,156 @@ +/** + * \file + * + * \brief Instance description for SERCOM2 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM2_INSTANCE_ +#define _SAML22_SERCOM2_INSTANCE_ + +/* ========== Register definition for SERCOM2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM2_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (0x42000C0CU) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (0x42000C14U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */ +#define REG_SERCOM2_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (0x42000C14U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */ +#define REG_SERCOM2_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (0x42000C0CU) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (0x42000C14U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM2) SPI Synchronization Busy */ +#define REG_SERCOM2_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (0x42000C28U) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_CTRLC (0x42000C08U) /**< \brief (SERCOM2) USART Control C */ +#define REG_SERCOM2_USART_BAUD (0x42000C0CU) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (0x42000C0EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM2) USART Synchronization Busy */ +#define REG_SERCOM2_USART_RXERRCNT (0x42000C20U) /**< \brief (SERCOM2) USART Receive Error Count */ +#define REG_SERCOM2_USART_DATA (0x42000C28U) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM2) USART Debug Control */ +#else +#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x42000C0CU) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */ +#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */ +#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM2) SPI Synchronization Busy */ +#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_CTRLC (*(RwReg *)0x42000C08U) /**< \brief (SERCOM2) USART Control C */ +#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM2) USART Synchronization Busy */ +#define REG_SERCOM2_USART_RXERRCNT (*(RoReg8 *)0x42000C20U) /**< \brief (SERCOM2) USART Receive Error Count */ +#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM2) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM2 peripheral ========== */ +#define SERCOM2_DMAC_ID_RX 6 // Index of DMA RX trigger +#define SERCOM2_DMAC_ID_TX 7 // Index of DMA TX trigger +#define SERCOM2_GCLK_ID_CORE 18 +#define SERCOM2_GCLK_ID_SLOW 15 +#define SERCOM2_INT_MSB 6 +#define SERCOM2_PMSB 3 +#define SERCOM2_SPI 1 // SPI mode implemented? +#define SERCOM2_TWIM 1 // TWI Master mode implemented? +#define SERCOM2_TWIS 1 // TWI Slave mode implemented? +#define SERCOM2_TWI_HSMODE 0 // TWI HighSpeed mode implemented? +#define SERCOM2_USART 1 // USART mode implemented? +#define SERCOM2_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM2_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM2_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM2_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/sercom3.h b/Sensor Watch Starter Project/include/instance/sercom3.h new file mode 100755 index 00000000..2d310a73 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom3.h @@ -0,0 +1,156 @@ +/** + * \file + * + * \brief Instance description for SERCOM3 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM3_INSTANCE_ +#define _SAML22_SERCOM3_INSTANCE_ + +/* ========== Register definition for SERCOM3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM3_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */ +#define REG_SERCOM3_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (0x42001028U) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */ +#define REG_SERCOM3_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (0x42001028U) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM3) SPI Synchronization Busy */ +#define REG_SERCOM3_SPI_ADDR (0x42001024U) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (0x42001028U) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (0x42001000U) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (0x42001004U) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_CTRLC (0x42001008U) /**< \brief (SERCOM3) USART Control C */ +#define REG_SERCOM3_USART_BAUD (0x4200100CU) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (0x4200100EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (0x42001016U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (0x4200101AU) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM3) USART Synchronization Busy */ +#define REG_SERCOM3_USART_RXERRCNT (0x42001020U) /**< \brief (SERCOM3) USART Receive Error Count */ +#define REG_SERCOM3_USART_DATA (0x42001028U) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM3) USART Debug Control */ +#else +#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */ +#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */ +#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM3) SPI Synchronization Busy */ +#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_CTRLC (*(RwReg *)0x42001008U) /**< \brief (SERCOM3) USART Control C */ +#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM3) USART Synchronization Busy */ +#define REG_SERCOM3_USART_RXERRCNT (*(RoReg8 *)0x42001020U) /**< \brief (SERCOM3) USART Receive Error Count */ +#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM3) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM3 peripheral ========== */ +#define SERCOM3_DMAC_ID_RX 8 // Index of DMA RX trigger +#define SERCOM3_DMAC_ID_TX 9 // Index of DMA TX trigger +#define SERCOM3_GCLK_ID_CORE 19 +#define SERCOM3_GCLK_ID_SLOW 15 +#define SERCOM3_INT_MSB 6 +#define SERCOM3_PMSB 3 +#define SERCOM3_SPI 1 // SPI mode implemented? +#define SERCOM3_TWIM 1 // TWI Master mode implemented? +#define SERCOM3_TWIS 1 // TWI Slave mode implemented? +#define SERCOM3_TWI_HSMODE 0 // TWI HighSpeed mode implemented? +#define SERCOM3_USART 1 // USART mode implemented? +#define SERCOM3_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM3_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM3_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM3_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/sercom4.h b/Sensor Watch Starter Project/include/instance/sercom4.h new file mode 100755 index 00000000..ce53d4f2 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom4.h @@ -0,0 +1,156 @@ +/** + * \file + * + * \brief Instance description for SERCOM4 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM4_INSTANCE_ +#define _SAML22_SERCOM4_INSTANCE_ + +/* ========== Register definition for SERCOM4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM4_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */ +#define REG_SERCOM4_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (0x42001428U) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */ +#define REG_SERCOM4_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (0x42001428U) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM4) SPI Synchronization Busy */ +#define REG_SERCOM4_SPI_ADDR (0x42001424U) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (0x42001428U) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (0x42001400U) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (0x42001404U) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_CTRLC (0x42001408U) /**< \brief (SERCOM4) USART Control C */ +#define REG_SERCOM4_USART_BAUD (0x4200140CU) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (0x4200140EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (0x42001416U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (0x4200141AU) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM4) USART Synchronization Busy */ +#define REG_SERCOM4_USART_RXERRCNT (0x42001420U) /**< \brief (SERCOM4) USART Receive Error Count */ +#define REG_SERCOM4_USART_DATA (0x42001428U) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM4) USART Debug Control */ +#else +#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */ +#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */ +#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM4) SPI Synchronization Busy */ +#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_CTRLC (*(RwReg *)0x42001408U) /**< \brief (SERCOM4) USART Control C */ +#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM4) USART Synchronization Busy */ +#define REG_SERCOM4_USART_RXERRCNT (*(RoReg8 *)0x42001420U) /**< \brief (SERCOM4) USART Receive Error Count */ +#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM4) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM4 peripheral ========== */ +#define SERCOM4_DMAC_ID_RX 10 // Index of DMA RX trigger +#define SERCOM4_DMAC_ID_TX 11 // Index of DMA TX trigger +#define SERCOM4_GCLK_ID_CORE 20 +#define SERCOM4_GCLK_ID_SLOW 15 +#define SERCOM4_INT_MSB 6 +#define SERCOM4_PMSB 3 +#define SERCOM4_SPI 1 // SPI mode implemented? +#define SERCOM4_TWIM 1 // TWI Master mode implemented? +#define SERCOM4_TWIS 1 // TWI Slave mode implemented? +#define SERCOM4_TWI_HSMODE 0 // TWI HighSpeed mode implemented? +#define SERCOM4_USART 1 // USART mode implemented? +#define SERCOM4_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM4_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM4_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM4_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/sercom5.h b/Sensor Watch Starter Project/include/instance/sercom5.h new file mode 100755 index 00000000..6aabf3a8 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom5.h @@ -0,0 +1,156 @@ +/** + * \file + * + * \brief Instance description for SERCOM5 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM5_INSTANCE_ +#define _SAML22_SERCOM5_INSTANCE_ + +/* ========== Register definition for SERCOM5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM5_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (0x4200180CU) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (0x42001814U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */ +#define REG_SERCOM5_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (0x42001828U) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (0x42001814U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */ +#define REG_SERCOM5_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (0x42001828U) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (0x4200180CU) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (0x42001814U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM5) SPI Synchronization Busy */ +#define REG_SERCOM5_SPI_ADDR (0x42001824U) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (0x42001828U) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (0x42001800U) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (0x42001804U) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_CTRLC (0x42001808U) /**< \brief (SERCOM5) USART Control C */ +#define REG_SERCOM5_USART_BAUD (0x4200180CU) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (0x4200180EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (0x42001816U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (0x4200181AU) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM5) USART Synchronization Busy */ +#define REG_SERCOM5_USART_RXERRCNT (0x42001820U) /**< \brief (SERCOM5) USART Receive Error Count */ +#define REG_SERCOM5_USART_DATA (0x42001828U) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM5) USART Debug Control */ +#else +#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4200180CU) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */ +#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */ +#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM5) SPI Synchronization Busy */ +#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_CTRLC (*(RwReg *)0x42001808U) /**< \brief (SERCOM5) USART Control C */ +#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM5) USART Synchronization Busy */ +#define REG_SERCOM5_USART_RXERRCNT (*(RoReg8 *)0x42001820U) /**< \brief (SERCOM5) USART Receive Error Count */ +#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM5) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM5 peripheral ========== */ +#define SERCOM5_DMAC_ID_RX 12 // Index of DMA RX trigger +#define SERCOM5_DMAC_ID_TX 13 // Index of DMA TX trigger +#define SERCOM5_GCLK_ID_CORE 21 +#define SERCOM5_GCLK_ID_SLOW 15 +#define SERCOM5_INT_MSB 3 +#define SERCOM5_PMSB 3 +#define SERCOM5_SPI 1 // SPI mode implemented? +#define SERCOM5_TWIM 1 // TWI Master mode implemented? +#define SERCOM5_TWIS 1 // TWI Slave mode implemented? +#define SERCOM5_TWI_HSMODE 1 // TWI HighSpeed mode implemented? +#define SERCOM5_USART 1 // USART mode implemented? +#define SERCOM5_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM5_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM5_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM5_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/slcd.h b/Sensor Watch Starter Project/include/instance/slcd.h new file mode 100755 index 00000000..6899f87b --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/slcd.h @@ -0,0 +1,140 @@ +/** + * \file + * + * \brief Instance description for SLCD + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SLCD_INSTANCE_ +#define _SAML22_SLCD_INSTANCE_ + +/* ========== Register definition for SLCD peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SLCD_CTRLA (0x42003C00U) /**< \brief (SLCD) Control A */ +#define REG_SLCD_CTRLB (0x42003C04U) /**< \brief (SLCD) Control B */ +#define REG_SLCD_CTRLC (0x42003C06U) /**< \brief (SLCD) Control C */ +#define REG_SLCD_CTRLD (0x42003C08U) /**< \brief (SLCD) Control D */ +#define REG_SLCD_EVCTRL (0x42003C0CU) /**< \brief (SLCD) Event Control */ +#define REG_SLCD_INTENCLR (0x42003C0DU) /**< \brief (SLCD) Interrupt Enable Clear */ +#define REG_SLCD_INTENSET (0x42003C0EU) /**< \brief (SLCD) Interrupt Enable Set */ +#define REG_SLCD_INTFLAG (0x42003C0FU) /**< \brief (SLCD) Interrupt Flag Status and Clear */ +#define REG_SLCD_STATUS (0x42003C10U) /**< \brief (SLCD) Status */ +#define REG_SLCD_SYNCBUSY (0x42003C14U) /**< \brief (SLCD) Synchronization Busy */ +#define REG_SLCD_FC0 (0x42003C18U) /**< \brief (SLCD) Frame Counter 0 Configuration */ +#define REG_SLCD_FC1 (0x42003C19U) /**< \brief (SLCD) Frame Counter 1 Configuration */ +#define REG_SLCD_FC2 (0x42003C1AU) /**< \brief (SLCD) Frame Counter 2 Configuration */ +#define REG_SLCD_LPENL (0x42003C1CU) /**< \brief (SLCD) LCD Pin Enable Low */ +#define REG_SLCD_LPENH (0x42003C20U) /**< \brief (SLCD) LCD Pin Enable High */ +#define REG_SLCD_SDATAL0 (0x42003C24U) /**< \brief (SLCD) Segments Data Low for COM0 Line */ +#define REG_SLCD_SDATAH0 (0x42003C28U) /**< \brief (SLCD) Segments Data High for COM0 Line */ +#define REG_SLCD_SDATAL1 (0x42003C2CU) /**< \brief (SLCD) Segments Data Low for COM1 Line */ +#define REG_SLCD_SDATAH1 (0x42003C30U) /**< \brief (SLCD) Segments Data High for COM1 Line */ +#define REG_SLCD_SDATAL2 (0x42003C34U) /**< \brief (SLCD) Segments Data Low for COM2 Line */ +#define REG_SLCD_SDATAH2 (0x42003C38U) /**< \brief (SLCD) Segments Data High for COM2 Line */ +#define REG_SLCD_SDATAL3 (0x42003C3CU) /**< \brief (SLCD) Segments Data Low for COM3 Line */ +#define REG_SLCD_SDATAH3 (0x42003C40U) /**< \brief (SLCD) Segments Data High for COM3 Line */ +#define REG_SLCD_SDATAL4 (0x42003C44U) /**< \brief (SLCD) Segments Data Low for COM4 Line */ +#define REG_SLCD_SDATAH4 (0x42003C48U) /**< \brief (SLCD) Segments Data High for COM4 Line */ +#define REG_SLCD_SDATAL5 (0x42003C4CU) /**< \brief (SLCD) Segments Data Low for COM5 Line */ +#define REG_SLCD_SDATAH5 (0x42003C50U) /**< \brief (SLCD) Segments Data High for COM5 Line */ +#define REG_SLCD_SDATAL6 (0x42003C54U) /**< \brief (SLCD) Segments Data Low for COM6 Line */ +#define REG_SLCD_SDATAH6 (0x42003C58U) /**< \brief (SLCD) Segments Data High for COM6 Line */ +#define REG_SLCD_SDATAL7 (0x42003C5CU) /**< \brief (SLCD) Segments Data Low for COM7 Line */ +#define REG_SLCD_SDATAH7 (0x42003C60U) /**< \brief (SLCD) Segments Data High for COM7 Line */ +#define REG_SLCD_ISDATA (0x42003C64U) /**< \brief (SLCD) Indirect Segments Data Access */ +#define REG_SLCD_BCFG (0x42003C68U) /**< \brief (SLCD) Blink Configuration */ +#define REG_SLCD_CSRCFG (0x42003C6CU) /**< \brief (SLCD) Circular Shift Register Configuration */ +#define REG_SLCD_CMCFG (0x42003C70U) /**< \brief (SLCD) Character Mapping Configuration */ +#define REG_SLCD_ACMCFG (0x42003C74U) /**< \brief (SLCD) Automated Character Mapping Configuration */ +#define REG_SLCD_ABMCFG (0x42003C78U) /**< \brief (SLCD) Automated Bit Mapping Configuration */ +#define REG_SLCD_CMDATA (0x42003C7CU) /**< \brief (SLCD) Character Mapping Segments Data */ +#define REG_SLCD_CMDMASK (0x42003C80U) /**< \brief (SLCD) Character Mapping Segments Data Mask */ +#define REG_SLCD_CMINDEX (0x42003C84U) /**< \brief (SLCD) Character Mapping SEG/COM Index */ +#else +#define REG_SLCD_CTRLA (*(RwReg *)0x42003C00U) /**< \brief (SLCD) Control A */ +#define REG_SLCD_CTRLB (*(RwReg16*)0x42003C04U) /**< \brief (SLCD) Control B */ +#define REG_SLCD_CTRLC (*(RwReg16*)0x42003C06U) /**< \brief (SLCD) Control C */ +#define REG_SLCD_CTRLD (*(RwReg8 *)0x42003C08U) /**< \brief (SLCD) Control D */ +#define REG_SLCD_EVCTRL (*(RwReg8 *)0x42003C0CU) /**< \brief (SLCD) Event Control */ +#define REG_SLCD_INTENCLR (*(RwReg8 *)0x42003C0DU) /**< \brief (SLCD) Interrupt Enable Clear */ +#define REG_SLCD_INTENSET (*(RwReg8 *)0x42003C0EU) /**< \brief (SLCD) Interrupt Enable Set */ +#define REG_SLCD_INTFLAG (*(RwReg8 *)0x42003C0FU) /**< \brief (SLCD) Interrupt Flag Status and Clear */ +#define REG_SLCD_STATUS (*(RoReg8 *)0x42003C10U) /**< \brief (SLCD) Status */ +#define REG_SLCD_SYNCBUSY (*(RoReg *)0x42003C14U) /**< \brief (SLCD) Synchronization Busy */ +#define REG_SLCD_FC0 (*(RwReg8 *)0x42003C18U) /**< \brief (SLCD) Frame Counter 0 Configuration */ +#define REG_SLCD_FC1 (*(RwReg8 *)0x42003C19U) /**< \brief (SLCD) Frame Counter 1 Configuration */ +#define REG_SLCD_FC2 (*(RwReg8 *)0x42003C1AU) /**< \brief (SLCD) Frame Counter 2 Configuration */ +#define REG_SLCD_LPENL (*(RwReg *)0x42003C1CU) /**< \brief (SLCD) LCD Pin Enable Low */ +#define REG_SLCD_LPENH (*(RwReg *)0x42003C20U) /**< \brief (SLCD) LCD Pin Enable High */ +#define REG_SLCD_SDATAL0 (*(RwReg *)0x42003C24U) /**< \brief (SLCD) Segments Data Low for COM0 Line */ +#define REG_SLCD_SDATAH0 (*(RwReg *)0x42003C28U) /**< \brief (SLCD) Segments Data High for COM0 Line */ +#define REG_SLCD_SDATAL1 (*(RwReg *)0x42003C2CU) /**< \brief (SLCD) Segments Data Low for COM1 Line */ +#define REG_SLCD_SDATAH1 (*(RwReg *)0x42003C30U) /**< \brief (SLCD) Segments Data High for COM1 Line */ +#define REG_SLCD_SDATAL2 (*(RwReg *)0x42003C34U) /**< \brief (SLCD) Segments Data Low for COM2 Line */ +#define REG_SLCD_SDATAH2 (*(RwReg *)0x42003C38U) /**< \brief (SLCD) Segments Data High for COM2 Line */ +#define REG_SLCD_SDATAL3 (*(RwReg *)0x42003C3CU) /**< \brief (SLCD) Segments Data Low for COM3 Line */ +#define REG_SLCD_SDATAH3 (*(RwReg *)0x42003C40U) /**< \brief (SLCD) Segments Data High for COM3 Line */ +#define REG_SLCD_SDATAL4 (*(RwReg *)0x42003C44U) /**< \brief (SLCD) Segments Data Low for COM4 Line */ +#define REG_SLCD_SDATAH4 (*(RwReg *)0x42003C48U) /**< \brief (SLCD) Segments Data High for COM4 Line */ +#define REG_SLCD_SDATAL5 (*(RwReg *)0x42003C4CU) /**< \brief (SLCD) Segments Data Low for COM5 Line */ +#define REG_SLCD_SDATAH5 (*(RwReg *)0x42003C50U) /**< \brief (SLCD) Segments Data High for COM5 Line */ +#define REG_SLCD_SDATAL6 (*(RwReg *)0x42003C54U) /**< \brief (SLCD) Segments Data Low for COM6 Line */ +#define REG_SLCD_SDATAH6 (*(RwReg *)0x42003C58U) /**< \brief (SLCD) Segments Data High for COM6 Line */ +#define REG_SLCD_SDATAL7 (*(RwReg *)0x42003C5CU) /**< \brief (SLCD) Segments Data Low for COM7 Line */ +#define REG_SLCD_SDATAH7 (*(RwReg *)0x42003C60U) /**< \brief (SLCD) Segments Data High for COM7 Line */ +#define REG_SLCD_ISDATA (*(WoReg *)0x42003C64U) /**< \brief (SLCD) Indirect Segments Data Access */ +#define REG_SLCD_BCFG (*(RwReg *)0x42003C68U) /**< \brief (SLCD) Blink Configuration */ +#define REG_SLCD_CSRCFG (*(RwReg *)0x42003C6CU) /**< \brief (SLCD) Circular Shift Register Configuration */ +#define REG_SLCD_CMCFG (*(RwReg8 *)0x42003C70U) /**< \brief (SLCD) Character Mapping Configuration */ +#define REG_SLCD_ACMCFG (*(RwReg *)0x42003C74U) /**< \brief (SLCD) Automated Character Mapping Configuration */ +#define REG_SLCD_ABMCFG (*(RwReg8 *)0x42003C78U) /**< \brief (SLCD) Automated Bit Mapping Configuration */ +#define REG_SLCD_CMDATA (*(WoReg *)0x42003C7CU) /**< \brief (SLCD) Character Mapping Segments Data */ +#define REG_SLCD_CMDMASK (*(RwReg *)0x42003C80U) /**< \brief (SLCD) Character Mapping Segments Data Mask */ +#define REG_SLCD_CMINDEX (*(RwReg16*)0x42003C84U) /**< \brief (SLCD) Character Mapping SEG/COM Index */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SLCD peripheral ========== */ +#define SLCD_DMAC_ID_ABMDRDY 34 +#define SLCD_DMAC_ID_ACMDRDY 33 +#define SLCD_DMAC_ID_DMU 32 +#define SLCD_MAX_COM 8 // Max number of COM lines (4 or 8) +#define SLCD_MAX_SEG 44 // Max number of SEG lines (24 or 44) +#define SLCD_NB_LP 52 // Number of LCD pins ([28..64] or [48..64]) + +#endif /* _SAML22_SLCD_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/supc.h b/Sensor Watch Starter Project/include/instance/supc.h new file mode 100755 index 00000000..b148c204 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/supc.h @@ -0,0 +1,79 @@ +/** + * \file + * + * \brief Instance description for SUPC + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SUPC_INSTANCE_ +#define _SAML22_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SUPC_INTENCLR (0x40001800U) /**< \brief (SUPC) Interrupt Enable Clear */ +#define REG_SUPC_INTENSET (0x40001804U) /**< \brief (SUPC) Interrupt Enable Set */ +#define REG_SUPC_INTFLAG (0x40001808U) /**< \brief (SUPC) Interrupt Flag Status and Clear */ +#define REG_SUPC_STATUS (0x4000180CU) /**< \brief (SUPC) Power and Clocks Status */ +#define REG_SUPC_BOD33 (0x40001810U) /**< \brief (SUPC) BOD33 Control */ +#define REG_SUPC_BOD12 (0x40001814U) /**< \brief (SUPC) BOD12 Control */ +#define REG_SUPC_VREG (0x40001818U) /**< \brief (SUPC) VREG Control */ +#define REG_SUPC_VREF (0x4000181CU) /**< \brief (SUPC) VREF Control */ +#define REG_SUPC_BBPS (0x40001820U) /**< \brief (SUPC) Battery Backup Power Switch */ +#define REG_SUPC_BKOUT (0x40001824U) /**< \brief (SUPC) Backup Output Control */ +#define REG_SUPC_BKIN (0x40001828U) /**< \brief (SUPC) Backup Input Control */ +#else +#define REG_SUPC_INTENCLR (*(RwReg *)0x40001800U) /**< \brief (SUPC) Interrupt Enable Clear */ +#define REG_SUPC_INTENSET (*(RwReg *)0x40001804U) /**< \brief (SUPC) Interrupt Enable Set */ +#define REG_SUPC_INTFLAG (*(RwReg *)0x40001808U) /**< \brief (SUPC) Interrupt Flag Status and Clear */ +#define REG_SUPC_STATUS (*(RoReg *)0x4000180CU) /**< \brief (SUPC) Power and Clocks Status */ +#define REG_SUPC_BOD33 (*(RwReg *)0x40001810U) /**< \brief (SUPC) BOD33 Control */ +#define REG_SUPC_BOD12 (*(RwReg *)0x40001814U) /**< \brief (SUPC) BOD12 Control */ +#define REG_SUPC_VREG (*(RwReg *)0x40001818U) /**< \brief (SUPC) VREG Control */ +#define REG_SUPC_VREF (*(RwReg *)0x4000181CU) /**< \brief (SUPC) VREF Control */ +#define REG_SUPC_BBPS (*(RwReg *)0x40001820U) /**< \brief (SUPC) Battery Backup Power Switch */ +#define REG_SUPC_BKOUT (*(RwReg *)0x40001824U) /**< \brief (SUPC) Backup Output Control */ +#define REG_SUPC_BKIN (*(RoReg *)0x40001828U) /**< \brief (SUPC) Backup Input Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SUPC peripheral ========== */ +#define SUPC_BOD12_CALIB_MSB 5 +#define SUPC_BOD33_CALIB_MSB 5 +#define SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number + +#endif /* _SAML22_SUPC_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/tal.h b/Sensor Watch Starter Project/include/instance/tal.h new file mode 100755 index 00000000..994abf90 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tal.h @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief Instance description for TAL + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TAL_INSTANCE_ +#define _SAML22_TAL_INSTANCE_ + +/* ========== Register definition for TAL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TAL_CTRLA (0x40003000U) /**< \brief (TAL) Control A */ +#define REG_TAL_RSTCTRL (0x40003004U) /**< \brief (TAL) Reset Control */ +#define REG_TAL_EXTCTRL (0x40003005U) /**< \brief (TAL) External Break Control */ +#define REG_TAL_EVCTRL (0x40003006U) /**< \brief (TAL) Event Control */ +#define REG_TAL_INTENCLR (0x40003008U) /**< \brief (TAL) Interrupt Enable Clear */ +#define REG_TAL_INTENSET (0x40003009U) /**< \brief (TAL) Interrupt Enable Set */ +#define REG_TAL_INTFLAG (0x4000300AU) /**< \brief (TAL) Interrupt Flag Status and Clear */ +#define REG_TAL_GLOBMASK (0x4000300BU) /**< \brief (TAL) Global Break Requests Mask */ +#define REG_TAL_HALT (0x4000300CU) /**< \brief (TAL) Debug Halt Request */ +#define REG_TAL_RESTART (0x4000300DU) /**< \brief (TAL) Debug Restart Request */ +#define REG_TAL_BRKSTATUS (0x4000300EU) /**< \brief (TAL) Break Request Status */ +#define REG_TAL_CTICTRLA0 (0x40003010U) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */ +#define REG_TAL_CTIMASK0 (0x40003011U) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */ +#define REG_TAL_CTICTRLA1 (0x40003012U) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */ +#define REG_TAL_CTIMASK1 (0x40003013U) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */ +#define REG_TAL_CTICTRLA2 (0x40003014U) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */ +#define REG_TAL_CTIMASK2 (0x40003015U) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */ +#define REG_TAL_INTSTATUS0 (0x40003020U) /**< \brief (TAL) Interrupt 0 Status */ +#define REG_TAL_INTSTATUS1 (0x40003021U) /**< \brief (TAL) Interrupt 1 Status */ +#define REG_TAL_INTSTATUS2 (0x40003022U) /**< \brief (TAL) Interrupt 2 Status */ +#define REG_TAL_INTSTATUS3 (0x40003023U) /**< \brief (TAL) Interrupt 3 Status */ +#define REG_TAL_INTSTATUS4 (0x40003024U) /**< \brief (TAL) Interrupt 4 Status */ +#define REG_TAL_INTSTATUS5 (0x40003025U) /**< \brief (TAL) Interrupt 5 Status */ +#define REG_TAL_INTSTATUS6 (0x40003026U) /**< \brief (TAL) Interrupt 6 Status */ +#define REG_TAL_INTSTATUS7 (0x40003027U) /**< \brief (TAL) Interrupt 7 Status */ +#define REG_TAL_INTSTATUS8 (0x40003028U) /**< \brief (TAL) Interrupt 8 Status */ +#define REG_TAL_INTSTATUS9 (0x40003029U) /**< \brief (TAL) Interrupt 9 Status */ +#define REG_TAL_INTSTATUS10 (0x4000302AU) /**< \brief (TAL) Interrupt 10 Status */ +#define REG_TAL_INTSTATUS11 (0x4000302BU) /**< \brief (TAL) Interrupt 11 Status */ +#define REG_TAL_INTSTATUS12 (0x4000302CU) /**< \brief (TAL) Interrupt 12 Status */ +#define REG_TAL_INTSTATUS13 (0x4000302DU) /**< \brief (TAL) Interrupt 13 Status */ +#define REG_TAL_INTSTATUS14 (0x4000302EU) /**< \brief (TAL) Interrupt 14 Status */ +#define REG_TAL_INTSTATUS15 (0x4000302FU) /**< \brief (TAL) Interrupt 15 Status */ +#define REG_TAL_INTSTATUS16 (0x40003030U) /**< \brief (TAL) Interrupt 16 Status */ +#define REG_TAL_INTSTATUS17 (0x40003031U) /**< \brief (TAL) Interrupt 17 Status */ +#define REG_TAL_INTSTATUS18 (0x40003032U) /**< \brief (TAL) Interrupt 18 Status */ +#define REG_TAL_INTSTATUS19 (0x40003033U) /**< \brief (TAL) Interrupt 19 Status */ +#define REG_TAL_INTSTATUS20 (0x40003034U) /**< \brief (TAL) Interrupt 20 Status */ +#define REG_TAL_INTSTATUS21 (0x40003035U) /**< \brief (TAL) Interrupt 21 Status */ +#define REG_TAL_INTSTATUS22 (0x40003036U) /**< \brief (TAL) Interrupt 22 Status */ +#define REG_TAL_INTSTATUS23 (0x40003037U) /**< \brief (TAL) Interrupt 23 Status */ +#define REG_TAL_INTSTATUS24 (0x40003038U) /**< \brief (TAL) Interrupt 24 Status */ +#define REG_TAL_INTSTATUS25 (0x40003039U) /**< \brief (TAL) Interrupt 25 Status */ +#define REG_TAL_DMACPUSEL0 (0x40003040U) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */ +#define REG_TAL_EVCPUSEL0 (0x40003048U) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */ +#define REG_TAL_EICCPUSEL0 (0x40003050U) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */ +#define REG_TAL_INTCPUSEL0 (0x40003058U) /**< \brief (TAL) Interrupts CPU Select 0 */ +#define REG_TAL_INTCPUSEL1 (0x4000305CU) /**< \brief (TAL) Interrupts CPU Select 1 */ +#define REG_TAL_IRQTRIG (0x40003060U) /**< \brief (TAL) Interrupt Trigger */ +#define REG_TAL_CPUIRQS0 (0x40003064U) /**< \brief (TAL) Interrupt Status for CPU 0 */ +#else +#define REG_TAL_CTRLA (*(RwReg8 *)0x40003000U) /**< \brief (TAL) Control A */ +#define REG_TAL_RSTCTRL (*(RwReg8 *)0x40003004U) /**< \brief (TAL) Reset Control */ +#define REG_TAL_EXTCTRL (*(RwReg8 *)0x40003005U) /**< \brief (TAL) External Break Control */ +#define REG_TAL_EVCTRL (*(RwReg8 *)0x40003006U) /**< \brief (TAL) Event Control */ +#define REG_TAL_INTENCLR (*(RwReg8 *)0x40003008U) /**< \brief (TAL) Interrupt Enable Clear */ +#define REG_TAL_INTENSET (*(RwReg8 *)0x40003009U) /**< \brief (TAL) Interrupt Enable Set */ +#define REG_TAL_INTFLAG (*(RwReg8 *)0x4000300AU) /**< \brief (TAL) Interrupt Flag Status and Clear */ +#define REG_TAL_GLOBMASK (*(RwReg8 *)0x4000300BU) /**< \brief (TAL) Global Break Requests Mask */ +#define REG_TAL_HALT (*(WoReg8 *)0x4000300CU) /**< \brief (TAL) Debug Halt Request */ +#define REG_TAL_RESTART (*(WoReg8 *)0x4000300DU) /**< \brief (TAL) Debug Restart Request */ +#define REG_TAL_BRKSTATUS (*(RoReg16*)0x4000300EU) /**< \brief (TAL) Break Request Status */ +#define REG_TAL_CTICTRLA0 (*(RwReg8 *)0x40003010U) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */ +#define REG_TAL_CTIMASK0 (*(RwReg8 *)0x40003011U) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */ +#define REG_TAL_CTICTRLA1 (*(RwReg8 *)0x40003012U) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */ +#define REG_TAL_CTIMASK1 (*(RwReg8 *)0x40003013U) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */ +#define REG_TAL_CTICTRLA2 (*(RwReg8 *)0x40003014U) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */ +#define REG_TAL_CTIMASK2 (*(RwReg8 *)0x40003015U) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */ +#define REG_TAL_INTSTATUS0 (*(RoReg8 *)0x40003020U) /**< \brief (TAL) Interrupt 0 Status */ +#define REG_TAL_INTSTATUS1 (*(RoReg8 *)0x40003021U) /**< \brief (TAL) Interrupt 1 Status */ +#define REG_TAL_INTSTATUS2 (*(RoReg8 *)0x40003022U) /**< \brief (TAL) Interrupt 2 Status */ +#define REG_TAL_INTSTATUS3 (*(RoReg8 *)0x40003023U) /**< \brief (TAL) Interrupt 3 Status */ +#define REG_TAL_INTSTATUS4 (*(RoReg8 *)0x40003024U) /**< \brief (TAL) Interrupt 4 Status */ +#define REG_TAL_INTSTATUS5 (*(RoReg8 *)0x40003025U) /**< \brief (TAL) Interrupt 5 Status */ +#define REG_TAL_INTSTATUS6 (*(RoReg8 *)0x40003026U) /**< \brief (TAL) Interrupt 6 Status */ +#define REG_TAL_INTSTATUS7 (*(RoReg8 *)0x40003027U) /**< \brief (TAL) Interrupt 7 Status */ +#define REG_TAL_INTSTATUS8 (*(RoReg8 *)0x40003028U) /**< \brief (TAL) Interrupt 8 Status */ +#define REG_TAL_INTSTATUS9 (*(RoReg8 *)0x40003029U) /**< \brief (TAL) Interrupt 9 Status */ +#define REG_TAL_INTSTATUS10 (*(RoReg8 *)0x4000302AU) /**< \brief (TAL) Interrupt 10 Status */ +#define REG_TAL_INTSTATUS11 (*(RoReg8 *)0x4000302BU) /**< \brief (TAL) Interrupt 11 Status */ +#define REG_TAL_INTSTATUS12 (*(RoReg8 *)0x4000302CU) /**< \brief (TAL) Interrupt 12 Status */ +#define REG_TAL_INTSTATUS13 (*(RoReg8 *)0x4000302DU) /**< \brief (TAL) Interrupt 13 Status */ +#define REG_TAL_INTSTATUS14 (*(RoReg8 *)0x4000302EU) /**< \brief (TAL) Interrupt 14 Status */ +#define REG_TAL_INTSTATUS15 (*(RoReg8 *)0x4000302FU) /**< \brief (TAL) Interrupt 15 Status */ +#define REG_TAL_INTSTATUS16 (*(RoReg8 *)0x40003030U) /**< \brief (TAL) Interrupt 16 Status */ +#define REG_TAL_INTSTATUS17 (*(RoReg8 *)0x40003031U) /**< \brief (TAL) Interrupt 17 Status */ +#define REG_TAL_INTSTATUS18 (*(RoReg8 *)0x40003032U) /**< \brief (TAL) Interrupt 18 Status */ +#define REG_TAL_INTSTATUS19 (*(RoReg8 *)0x40003033U) /**< \brief (TAL) Interrupt 19 Status */ +#define REG_TAL_INTSTATUS20 (*(RoReg8 *)0x40003034U) /**< \brief (TAL) Interrupt 20 Status */ +#define REG_TAL_INTSTATUS21 (*(RoReg8 *)0x40003035U) /**< \brief (TAL) Interrupt 21 Status */ +#define REG_TAL_INTSTATUS22 (*(RoReg8 *)0x40003036U) /**< \brief (TAL) Interrupt 22 Status */ +#define REG_TAL_INTSTATUS23 (*(RoReg8 *)0x40003037U) /**< \brief (TAL) Interrupt 23 Status */ +#define REG_TAL_INTSTATUS24 (*(RoReg8 *)0x40003038U) /**< \brief (TAL) Interrupt 24 Status */ +#define REG_TAL_INTSTATUS25 (*(RoReg8 *)0x40003039U) /**< \brief (TAL) Interrupt 25 Status */ +#define REG_TAL_DMACPUSEL0 (*(RwReg *)0x40003040U) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */ +#define REG_TAL_EVCPUSEL0 (*(RwReg *)0x40003048U) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */ +#define REG_TAL_EICCPUSEL0 (*(RwReg *)0x40003050U) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */ +#define REG_TAL_INTCPUSEL0 (*(RwReg *)0x40003058U) /**< \brief (TAL) Interrupts CPU Select 0 */ +#define REG_TAL_INTCPUSEL1 (*(RwReg *)0x4000305CU) /**< \brief (TAL) Interrupts CPU Select 1 */ +#define REG_TAL_IRQTRIG (*(RwReg16*)0x40003060U) /**< \brief (TAL) Interrupt Trigger */ +#define REG_TAL_CPUIRQS0 (*(RoReg *)0x40003064U) /**< \brief (TAL) Interrupt Status for CPU 0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TAL peripheral ========== */ +#define TAL_CPU_NUM 1 // Number of CPUs +#define TAL_CTI_NUM 3 // Number of Cross-Trigger Interfaces +#define TAL_DMA_CH_NUM 16 // Number of DMAC Channels +#define TAL_EV_CH_NUM 8 // Number of EVSYS Channels +#define TAL_EXTINT_NUM 16 // Number of EIC External Interrrupts +#define TAL_INT_NUM 26 // Number of Interrupt Requests + +#endif /* _SAML22_TAL_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/tc0.h b/Sensor Watch Starter Project/include/instance/tc0.h new file mode 100755 index 00000000..231bbea9 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tc0.h @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief Instance description for TC0 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TC0_INSTANCE_ +#define _SAML22_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC0_CTRLA (0x42002000U) /**< \brief (TC0) Control A */ +#define REG_TC0_CTRLBCLR (0x42002004U) /**< \brief (TC0) Control B Clear */ +#define REG_TC0_CTRLBSET (0x42002005U) /**< \brief (TC0) Control B Set */ +#define REG_TC0_EVCTRL (0x42002006U) /**< \brief (TC0) Event Control */ +#define REG_TC0_INTENCLR (0x42002008U) /**< \brief (TC0) Interrupt Enable Clear */ +#define REG_TC0_INTENSET (0x42002009U) /**< \brief (TC0) Interrupt Enable Set */ +#define REG_TC0_INTFLAG (0x4200200AU) /**< \brief (TC0) Interrupt Flag Status and Clear */ +#define REG_TC0_STATUS (0x4200200BU) /**< \brief (TC0) Status */ +#define REG_TC0_WAVE (0x4200200CU) /**< \brief (TC0) Waveform Generation Control */ +#define REG_TC0_DRVCTRL (0x4200200DU) /**< \brief (TC0) Control C */ +#define REG_TC0_DBGCTRL (0x4200200FU) /**< \brief (TC0) Debug Control */ +#define REG_TC0_SYNCBUSY (0x42002010U) /**< \brief (TC0) Synchronization Status */ +#define REG_TC0_COUNT16_COUNT (0x42002014U) /**< \brief (TC0) COUNT16 Count */ +#define REG_TC0_COUNT16_CC0 (0x4200201CU) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ +#define REG_TC0_COUNT16_CC1 (0x4200201EU) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ +#define REG_TC0_COUNT16_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT16_CCBUF1 (0x42002032U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT32_COUNT (0x42002014U) /**< \brief (TC0) COUNT32 Count */ +#define REG_TC0_COUNT32_CC0 (0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ +#define REG_TC0_COUNT32_CC1 (0x42002020U) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ +#define REG_TC0_COUNT32_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT32_CCBUF1 (0x42002034U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT8_COUNT (0x42002014U) /**< \brief (TC0) COUNT8 Count */ +#define REG_TC0_COUNT8_PER (0x4200201BU) /**< \brief (TC0) COUNT8 Period */ +#define REG_TC0_COUNT8_CC0 (0x4200201CU) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ +#define REG_TC0_COUNT8_CC1 (0x4200201DU) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ +#define REG_TC0_COUNT8_PERBUF (0x4200202FU) /**< \brief (TC0) COUNT8 Period Buffer */ +#define REG_TC0_COUNT8_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT8_CCBUF1 (0x42002031U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TC0) Control A */ +#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TC0) Control B Clear */ +#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TC0) Control B Set */ +#define REG_TC0_EVCTRL (*(RwReg16*)0x42002006U) /**< \brief (TC0) Event Control */ +#define REG_TC0_INTENCLR (*(RwReg8 *)0x42002008U) /**< \brief (TC0) Interrupt Enable Clear */ +#define REG_TC0_INTENSET (*(RwReg8 *)0x42002009U) /**< \brief (TC0) Interrupt Enable Set */ +#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200AU) /**< \brief (TC0) Interrupt Flag Status and Clear */ +#define REG_TC0_STATUS (*(RwReg8 *)0x4200200BU) /**< \brief (TC0) Status */ +#define REG_TC0_WAVE (*(RwReg8 *)0x4200200CU) /**< \brief (TC0) Waveform Generation Control */ +#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200200DU) /**< \brief (TC0) Control C */ +#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200200FU) /**< \brief (TC0) Debug Control */ +#define REG_TC0_SYNCBUSY (*(RoReg *)0x42002010U) /**< \brief (TC0) Synchronization Status */ +#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002014U) /**< \brief (TC0) COUNT16 Count */ +#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4200201CU) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ +#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201EU) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ +#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x42002030U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x42002032U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002014U) /**< \brief (TC0) COUNT32 Count */ +#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ +#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42002020U) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ +#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42002030U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42002034U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002014U) /**< \brief (TC0) COUNT8 Count */ +#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4200201BU) /**< \brief (TC0) COUNT8 Period */ +#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4200201CU) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ +#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4200201DU) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ +#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4200202FU) /**< \brief (TC0) COUNT8 Period Buffer */ +#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x42002030U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x42002031U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC0 peripheral ========== */ +#define TC0_CC_NUM 2 +#define TC0_DMAC_ID_MC_0 20 +#define TC0_DMAC_ID_MC_1 21 +#define TC0_DMAC_ID_MC_LSB 20 +#define TC0_DMAC_ID_MC_MSB 21 +#define TC0_DMAC_ID_MC_SIZE 2 +#define TC0_DMAC_ID_OVF 19 // Indexes of DMA Overflow trigger +#define TC0_EXT 0 +#define TC0_GCLK_ID 23 +#define TC0_MASTER 1 +#define TC0_OW_NUM 2 + +#endif /* _SAML22_TC0_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/tc1.h b/Sensor Watch Starter Project/include/instance/tc1.h new file mode 100755 index 00000000..fc76b275 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tc1.h @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief Instance description for TC1 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TC1_INSTANCE_ +#define _SAML22_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC1_CTRLA (0x42002400U) /**< \brief (TC1) Control A */ +#define REG_TC1_CTRLBCLR (0x42002404U) /**< \brief (TC1) Control B Clear */ +#define REG_TC1_CTRLBSET (0x42002405U) /**< \brief (TC1) Control B Set */ +#define REG_TC1_EVCTRL (0x42002406U) /**< \brief (TC1) Event Control */ +#define REG_TC1_INTENCLR (0x42002408U) /**< \brief (TC1) Interrupt Enable Clear */ +#define REG_TC1_INTENSET (0x42002409U) /**< \brief (TC1) Interrupt Enable Set */ +#define REG_TC1_INTFLAG (0x4200240AU) /**< \brief (TC1) Interrupt Flag Status and Clear */ +#define REG_TC1_STATUS (0x4200240BU) /**< \brief (TC1) Status */ +#define REG_TC1_WAVE (0x4200240CU) /**< \brief (TC1) Waveform Generation Control */ +#define REG_TC1_DRVCTRL (0x4200240DU) /**< \brief (TC1) Control C */ +#define REG_TC1_DBGCTRL (0x4200240FU) /**< \brief (TC1) Debug Control */ +#define REG_TC1_SYNCBUSY (0x42002410U) /**< \brief (TC1) Synchronization Status */ +#define REG_TC1_COUNT16_COUNT (0x42002414U) /**< \brief (TC1) COUNT16 Count */ +#define REG_TC1_COUNT16_CC0 (0x4200241CU) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ +#define REG_TC1_COUNT16_CC1 (0x4200241EU) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ +#define REG_TC1_COUNT16_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT16_CCBUF1 (0x42002432U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT32_COUNT (0x42002414U) /**< \brief (TC1) COUNT32 Count */ +#define REG_TC1_COUNT32_CC0 (0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ +#define REG_TC1_COUNT32_CC1 (0x42002420U) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ +#define REG_TC1_COUNT32_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT32_CCBUF1 (0x42002434U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT8_COUNT (0x42002414U) /**< \brief (TC1) COUNT8 Count */ +#define REG_TC1_COUNT8_PER (0x4200241BU) /**< \brief (TC1) COUNT8 Period */ +#define REG_TC1_COUNT8_CC0 (0x4200241CU) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ +#define REG_TC1_COUNT8_CC1 (0x4200241DU) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ +#define REG_TC1_COUNT8_PERBUF (0x4200242FU) /**< \brief (TC1) COUNT8 Period Buffer */ +#define REG_TC1_COUNT8_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT8_CCBUF1 (0x42002431U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TC1) Control A */ +#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TC1) Control B Clear */ +#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TC1) Control B Set */ +#define REG_TC1_EVCTRL (*(RwReg16*)0x42002406U) /**< \brief (TC1) Event Control */ +#define REG_TC1_INTENCLR (*(RwReg8 *)0x42002408U) /**< \brief (TC1) Interrupt Enable Clear */ +#define REG_TC1_INTENSET (*(RwReg8 *)0x42002409U) /**< \brief (TC1) Interrupt Enable Set */ +#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200240AU) /**< \brief (TC1) Interrupt Flag Status and Clear */ +#define REG_TC1_STATUS (*(RwReg8 *)0x4200240BU) /**< \brief (TC1) Status */ +#define REG_TC1_WAVE (*(RwReg8 *)0x4200240CU) /**< \brief (TC1) Waveform Generation Control */ +#define REG_TC1_DRVCTRL (*(RwReg8 *)0x4200240DU) /**< \brief (TC1) Control C */ +#define REG_TC1_DBGCTRL (*(RwReg8 *)0x4200240FU) /**< \brief (TC1) Debug Control */ +#define REG_TC1_SYNCBUSY (*(RoReg *)0x42002410U) /**< \brief (TC1) Synchronization Status */ +#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42002414U) /**< \brief (TC1) COUNT16 Count */ +#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x4200241CU) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ +#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200241EU) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ +#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x42002430U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x42002432U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42002414U) /**< \brief (TC1) COUNT32 Count */ +#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ +#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x42002420U) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ +#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x42002430U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x42002434U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42002414U) /**< \brief (TC1) COUNT8 Count */ +#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x4200241BU) /**< \brief (TC1) COUNT8 Period */ +#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x4200241CU) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ +#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x4200241DU) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ +#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x4200242FU) /**< \brief (TC1) COUNT8 Period Buffer */ +#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x42002430U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x42002431U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC1 peripheral ========== */ +#define TC1_CC_NUM 2 +#define TC1_DMAC_ID_MC_0 23 +#define TC1_DMAC_ID_MC_1 24 +#define TC1_DMAC_ID_MC_LSB 23 +#define TC1_DMAC_ID_MC_MSB 24 +#define TC1_DMAC_ID_MC_SIZE 2 +#define TC1_DMAC_ID_OVF 22 // Indexes of DMA Overflow trigger +#define TC1_EXT 0 +#define TC1_GCLK_ID 23 +#define TC1_MASTER 0 +#define TC1_OW_NUM 2 + +#endif /* _SAML22_TC1_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/tc2.h b/Sensor Watch Starter Project/include/instance/tc2.h new file mode 100755 index 00000000..7b5b2c84 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tc2.h @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief Instance description for TC2 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TC2_INSTANCE_ +#define _SAML22_TC2_INSTANCE_ + +/* ========== Register definition for TC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC2_CTRLA (0x42002800U) /**< \brief (TC2) Control A */ +#define REG_TC2_CTRLBCLR (0x42002804U) /**< \brief (TC2) Control B Clear */ +#define REG_TC2_CTRLBSET (0x42002805U) /**< \brief (TC2) Control B Set */ +#define REG_TC2_EVCTRL (0x42002806U) /**< \brief (TC2) Event Control */ +#define REG_TC2_INTENCLR (0x42002808U) /**< \brief (TC2) Interrupt Enable Clear */ +#define REG_TC2_INTENSET (0x42002809U) /**< \brief (TC2) Interrupt Enable Set */ +#define REG_TC2_INTFLAG (0x4200280AU) /**< \brief (TC2) Interrupt Flag Status and Clear */ +#define REG_TC2_STATUS (0x4200280BU) /**< \brief (TC2) Status */ +#define REG_TC2_WAVE (0x4200280CU) /**< \brief (TC2) Waveform Generation Control */ +#define REG_TC2_DRVCTRL (0x4200280DU) /**< \brief (TC2) Control C */ +#define REG_TC2_DBGCTRL (0x4200280FU) /**< \brief (TC2) Debug Control */ +#define REG_TC2_SYNCBUSY (0x42002810U) /**< \brief (TC2) Synchronization Status */ +#define REG_TC2_COUNT16_COUNT (0x42002814U) /**< \brief (TC2) COUNT16 Count */ +#define REG_TC2_COUNT16_CC0 (0x4200281CU) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ +#define REG_TC2_COUNT16_CC1 (0x4200281EU) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ +#define REG_TC2_COUNT16_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT16_CCBUF1 (0x42002832U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT32_COUNT (0x42002814U) /**< \brief (TC2) COUNT32 Count */ +#define REG_TC2_COUNT32_CC0 (0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ +#define REG_TC2_COUNT32_CC1 (0x42002820U) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ +#define REG_TC2_COUNT32_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT32_CCBUF1 (0x42002834U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT8_COUNT (0x42002814U) /**< \brief (TC2) COUNT8 Count */ +#define REG_TC2_COUNT8_PER (0x4200281BU) /**< \brief (TC2) COUNT8 Period */ +#define REG_TC2_COUNT8_CC0 (0x4200281CU) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ +#define REG_TC2_COUNT8_CC1 (0x4200281DU) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ +#define REG_TC2_COUNT8_PERBUF (0x4200282FU) /**< \brief (TC2) COUNT8 Period Buffer */ +#define REG_TC2_COUNT8_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT8_CCBUF1 (0x42002831U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TC2) Control A */ +#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TC2) Control B Clear */ +#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TC2) Control B Set */ +#define REG_TC2_EVCTRL (*(RwReg16*)0x42002806U) /**< \brief (TC2) Event Control */ +#define REG_TC2_INTENCLR (*(RwReg8 *)0x42002808U) /**< \brief (TC2) Interrupt Enable Clear */ +#define REG_TC2_INTENSET (*(RwReg8 *)0x42002809U) /**< \brief (TC2) Interrupt Enable Set */ +#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280AU) /**< \brief (TC2) Interrupt Flag Status and Clear */ +#define REG_TC2_STATUS (*(RwReg8 *)0x4200280BU) /**< \brief (TC2) Status */ +#define REG_TC2_WAVE (*(RwReg8 *)0x4200280CU) /**< \brief (TC2) Waveform Generation Control */ +#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200280DU) /**< \brief (TC2) Control C */ +#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200280FU) /**< \brief (TC2) Debug Control */ +#define REG_TC2_SYNCBUSY (*(RoReg *)0x42002810U) /**< \brief (TC2) Synchronization Status */ +#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42002814U) /**< \brief (TC2) COUNT16 Count */ +#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4200281CU) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ +#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200281EU) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ +#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x42002830U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x42002832U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42002814U) /**< \brief (TC2) COUNT32 Count */ +#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ +#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42002820U) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ +#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x42002830U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x42002834U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002814U) /**< \brief (TC2) COUNT8 Count */ +#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4200281BU) /**< \brief (TC2) COUNT8 Period */ +#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4200281CU) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ +#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4200281DU) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ +#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4200282FU) /**< \brief (TC2) COUNT8 Period Buffer */ +#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x42002830U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x42002831U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC2 peripheral ========== */ +#define TC2_CC_NUM 2 +#define TC2_DMAC_ID_MC_0 26 +#define TC2_DMAC_ID_MC_1 27 +#define TC2_DMAC_ID_MC_LSB 26 +#define TC2_DMAC_ID_MC_MSB 27 +#define TC2_DMAC_ID_MC_SIZE 2 +#define TC2_DMAC_ID_OVF 25 // Indexes of DMA Overflow trigger +#define TC2_EXT 0 +#define TC2_GCLK_ID 24 +#define TC2_MASTER 1 +#define TC2_OW_NUM 2 + +#endif /* _SAML22_TC2_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/tc3.h b/Sensor Watch Starter Project/include/instance/tc3.h new file mode 100755 index 00000000..dc7af021 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tc3.h @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief Instance description for TC3 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TC3_INSTANCE_ +#define _SAML22_TC3_INSTANCE_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */ +#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */ +#define REG_TC3_EVCTRL (0x42002C06U) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (0x42002C08U) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (0x42002C09U) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (0x42002C0AU) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (0x42002C0BU) /**< \brief (TC3) Status */ +#define REG_TC3_WAVE (0x42002C0CU) /**< \brief (TC3) Waveform Generation Control */ +#define REG_TC3_DRVCTRL (0x42002C0DU) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (0x42002C0FU) /**< \brief (TC3) Debug Control */ +#define REG_TC3_SYNCBUSY (0x42002C10U) /**< \brief (TC3) Synchronization Status */ +#define REG_TC3_COUNT16_COUNT (0x42002C14U) /**< \brief (TC3) COUNT16 Count */ +#define REG_TC3_COUNT16_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ +#define REG_TC3_COUNT16_CC1 (0x42002C1EU) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ +#define REG_TC3_COUNT16_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT16_CCBUF1 (0x42002C32U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT32_COUNT (0x42002C14U) /**< \brief (TC3) COUNT32 Count */ +#define REG_TC3_COUNT32_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ +#define REG_TC3_COUNT32_CC1 (0x42002C20U) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ +#define REG_TC3_COUNT32_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT32_CCBUF1 (0x42002C34U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT8_COUNT (0x42002C14U) /**< \brief (TC3) COUNT8 Count */ +#define REG_TC3_COUNT8_PER (0x42002C1BU) /**< \brief (TC3) COUNT8 Period */ +#define REG_TC3_COUNT8_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ +#define REG_TC3_COUNT8_CC1 (0x42002C1DU) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ +#define REG_TC3_COUNT8_PERBUF (0x42002C2FU) /**< \brief (TC3) COUNT8 Period Buffer */ +#define REG_TC3_COUNT8_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT8_CCBUF1 (0x42002C31U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC3_CTRLA (*(RwReg *)0x42002C00U) /**< \brief (TC3) Control A */ +#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */ +#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C06U) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C09U) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0AU) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (*(RwReg8 *)0x42002C0BU) /**< \brief (TC3) Status */ +#define REG_TC3_WAVE (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Waveform Generation Control */ +#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C0FU) /**< \brief (TC3) Debug Control */ +#define REG_TC3_SYNCBUSY (*(RoReg *)0x42002C10U) /**< \brief (TC3) Synchronization Status */ +#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C14U) /**< \brief (TC3) COUNT16 Count */ +#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C1CU) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ +#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1EU) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ +#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42002C30U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42002C32U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C14U) /**< \brief (TC3) COUNT32 Count */ +#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ +#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C20U) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ +#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42002C30U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42002C34U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Count */ +#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C1BU) /**< \brief (TC3) COUNT8 Period */ +#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C1CU) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ +#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C1DU) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ +#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42002C2FU) /**< \brief (TC3) COUNT8 Period Buffer */ +#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42002C30U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42002C31U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC3 peripheral ========== */ +#define TC3_CC_NUM 2 +#define TC3_DMAC_ID_MC_0 29 +#define TC3_DMAC_ID_MC_1 30 +#define TC3_DMAC_ID_MC_LSB 29 +#define TC3_DMAC_ID_MC_MSB 30 +#define TC3_DMAC_ID_MC_SIZE 2 +#define TC3_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger +#define TC3_EXT 0 +#define TC3_GCLK_ID 24 +#define TC3_MASTER 0 +#define TC3_OW_NUM 2 + +#endif /* _SAML22_TC3_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/tcc0.h b/Sensor Watch Starter Project/include/instance/tcc0.h new file mode 100755 index 00000000..263eaa85 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tcc0.h @@ -0,0 +1,129 @@ +/** + * \file + * + * \brief Instance description for TCC0 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TCC0_INSTANCE_ +#define _SAML22_TCC0_INSTANCE_ + +/* ========== Register definition for TCC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC0_CTRLA (0x42001C00U) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (0x42001C04U) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (0x42001C05U) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (0x42001C08U) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (0x42001C0CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (0x42001C10U) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (0x42001C14U) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (0x42001C18U) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (0x42001C1EU) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (0x42001C20U) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (0x42001C24U) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (0x42001C28U) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (0x42001C2CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (0x42001C30U) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (0x42001C34U) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (0x42001C38U) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (0x42001C3CU) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (0x42001C40U) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (0x42001C44U) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (0x42001C48U) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (0x42001C4CU) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (0x42001C50U) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTBUF (0x42001C64U) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_PERBUF (0x42001C6CU) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCBUF0 (0x42001C70U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCBUF1 (0x42001C74U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCBUF2 (0x42001C78U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCBUF3 (0x42001C7CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#else +#define REG_TCC0_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42001C04U) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42001C05U) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42001C08U) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (*(RwReg *)0x42001C0CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (*(RwReg *)0x42001C10U) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (*(RwReg *)0x42001C14U) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (*(RwReg *)0x42001C18U) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x42001C1EU) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (*(RwReg *)0x42001C20U) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (*(RwReg *)0x42001C24U) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (*(RwReg *)0x42001C28U) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (*(RwReg *)0x42001C2CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (*(RwReg *)0x42001C30U) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (*(RwReg *)0x42001C34U) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (*(RwReg16*)0x42001C38U) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (*(RwReg *)0x42001C3CU) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (*(RwReg *)0x42001C40U) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (*(RwReg *)0x42001C44U) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (*(RwReg *)0x42001C48U) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (*(RwReg *)0x42001C4CU) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (*(RwReg *)0x42001C50U) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTBUF (*(RwReg16*)0x42001C64U) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_PERBUF (*(RwReg *)0x42001C6CU) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCBUF0 (*(RwReg *)0x42001C70U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCBUF1 (*(RwReg *)0x42001C74U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCBUF2 (*(RwReg *)0x42001C78U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCBUF3 (*(RwReg *)0x42001C7CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC0 peripheral ========== */ +#define TCC0_CC_NUM 4 // Number of Compare/Capture units +#define TCC0_DITHERING 1 // Dithering feature implemented +#define TCC0_DMAC_ID_MC_0 15 +#define TCC0_DMAC_ID_MC_1 16 +#define TCC0_DMAC_ID_MC_2 17 +#define TCC0_DMAC_ID_MC_3 18 +#define TCC0_DMAC_ID_MC_LSB 15 +#define TCC0_DMAC_ID_MC_MSB 18 +#define TCC0_DMAC_ID_MC_SIZE 4 +#define TCC0_DMAC_ID_OVF 14 // DMA overflow/underflow/retrigger trigger +#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented +#define TCC0_EXT 31 // Coding of implemented extended features +#define TCC0_GCLK_ID 22 // Index of Generic Clock +#define TCC0_OTMX 1 // Output Matrix feature implemented +#define TCC0_OW_NUM 8 // Number of Output Waveforms +#define TCC0_PG 1 // Pattern Generation feature implemented +#define TCC0_SIZE 24 +#define TCC0_SWAP 1 // DTI outputs swap feature implemented +#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif /* _SAML22_TCC0_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/trng.h b/Sensor Watch Starter Project/include/instance/trng.h new file mode 100755 index 00000000..b3f143ce --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/trng.h @@ -0,0 +1,65 @@ +/** + * \file + * + * \brief Instance description for TRNG + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TRNG_INSTANCE_ +#define _SAML22_TRNG_INSTANCE_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TRNG_CTRLA (0x42004400U) /**< \brief (TRNG) Control A */ +#define REG_TRNG_EVCTRL (0x42004404U) /**< \brief (TRNG) Event Control */ +#define REG_TRNG_INTENCLR (0x42004408U) /**< \brief (TRNG) Interrupt Enable Clear */ +#define REG_TRNG_INTENSET (0x42004409U) /**< \brief (TRNG) Interrupt Enable Set */ +#define REG_TRNG_INTFLAG (0x4200440AU) /**< \brief (TRNG) Interrupt Flag Status and Clear */ +#define REG_TRNG_DATA (0x42004420U) /**< \brief (TRNG) Output Data */ +#else +#define REG_TRNG_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (TRNG) Control A */ +#define REG_TRNG_EVCTRL (*(RwReg8 *)0x42004404U) /**< \brief (TRNG) Event Control */ +#define REG_TRNG_INTENCLR (*(RwReg8 *)0x42004408U) /**< \brief (TRNG) Interrupt Enable Clear */ +#define REG_TRNG_INTENSET (*(RwReg8 *)0x42004409U) /**< \brief (TRNG) Interrupt Enable Set */ +#define REG_TRNG_INTFLAG (*(RwReg8 *)0x4200440AU) /**< \brief (TRNG) Interrupt Flag Status and Clear */ +#define REG_TRNG_DATA (*(RoReg *)0x42004420U) /**< \brief (TRNG) Output Data */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAML22_TRNG_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/usb.h b/Sensor Watch Starter Project/include/instance/usb.h new file mode 100755 index 00000000..b6b020a1 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/usb.h @@ -0,0 +1,196 @@ +/** + * \file + * + * \brief Instance description for USB + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_USB_INSTANCE_ +#define _SAML22_USB_INSTANCE_ + +/* ========== Register definition for USB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USB_CTRLA (0x41000000U) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (0x41000002U) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_FSMSTATUS (0x4100000DU) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (0x41000024U) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (0x41000028U) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (0x41000008U) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (0x4100000AU) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (0x4100000CU) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (0x41000010U) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (0x41000014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (0x41000018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (0x4100001CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (0x41000020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41000100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41000104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41000105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41000106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41000107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41000108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41000109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41000120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41000124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41000125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41000126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41000127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41000128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41000129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41000140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41000144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41000145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41000146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41000147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41000148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41000149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41000160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41000164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41000165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41000166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41000167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41000168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41000169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41000180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41000184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41000185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41000186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41000187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41000188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41000189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410001A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410001A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410001A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410001A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410001A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410001A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410001A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410001C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410001C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410001C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410001C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410001C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410001C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410001C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410001E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410001E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410001E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410001E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410001E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410001E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410001E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#else +#define REG_USB_CTRLA (*(RwReg8 *)0x41000000U) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41000002U) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100000DU) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (*(RwReg *)0x41000024U) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (*(RwReg16*)0x41000028U) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41000008U) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100000AU) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100000CU) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41000010U) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41000014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41000018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100001CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41000020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41000104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41000105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41000124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41000125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41000129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41000140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41000144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41000145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41000147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41000148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41000149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41000160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41000164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41000165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41000167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41000168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41000169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41000180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41000184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41000185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41000187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41000188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41000189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410001A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410001A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410001A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410001A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410001A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410001A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410001C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410001C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410001C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410001C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410001C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410001C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410001E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410001E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410001E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410001E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410001E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410001E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410001E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for USB peripheral ========== */ +#define USB_EPT_NBR 8 // Number of USB end points (obsolete) +#define USB_EPT_NUM 8 // Number of USB end points +#define USB_GCLK_ID 6 // Index of Generic Clock +#define USB_PIPE_NUM 0 // Number of USB pipes + +#endif /* _SAML22_USB_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/instance/wdt.h b/Sensor Watch Starter Project/include/instance/wdt.h new file mode 100755 index 00000000..2149da28 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/wdt.h @@ -0,0 +1,69 @@ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_WDT_INSTANCE_ +#define _SAML22_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRLA (0x40002000U) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (0x40002001U) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (0x40002002U) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (0x40002004U) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (0x40002005U) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (0x40002006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (0x40002008U) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (0x4000200CU) /**< \brief (WDT) Clear */ +#else +#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000U) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001U) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002U) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004U) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005U) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008U) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CU) /**< \brief (WDT) Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAML22_WDT_INSTANCE_ */ diff --git a/Sensor Watch Starter Project/include/pio/saml22g16a.h b/Sensor Watch Starter Project/include/pio/saml22g16a.h new file mode 100755 index 00000000..451ac145 --- /dev/null +++ b/Sensor Watch Starter Project/include/pio/saml22g16a.h @@ -0,0 +1,894 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22G16A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G16A_PIO_ +#define _SAML22G16A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB02G_RTC_IN1 34L /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 6L +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (1ul << 2) +#define PIN_PA02G_RTC_IN2 2L /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 6L +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (1ul << 2) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +#define PIN_PB22G_USB_SOF_1KHZ 54L /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ 6L +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (1ul << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA20C_SERCOM0_PAD0 20L /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 2L +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (1ul << 20) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA21C_SERCOM0_PAD1 21L /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 2L +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (1ul << 21) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA22C_SERCOM0_PAD2 22L /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 2L +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PB22C_SERCOM0_PAD2 54L /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 2L +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +#define PIN_PA23C_SERCOM0_PAD3 23L /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 2L +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (1ul << 23) +#define PIN_PB23C_SERCOM0_PAD3 55L /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 2L +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (1ul << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 3L +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22) +#define PIN_PA16D_SERCOM2_PAD0 16L /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 3L +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 3L +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23) +#define PIN_PA17D_SERCOM2_PAD1 17L /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 3L +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (1ul << 17) +#define PIN_PA18D_SERCOM2_PAD2 18L /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 3L +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM2_PAD2 20L /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 3L +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 2L +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM2_PAD3 19L /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 3L +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM2_PAD3 21L /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 3L +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 2L +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (1ul << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 24L /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 5L +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (1ul << 24) +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PA25F_TCC0_WO1 25L /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 5L +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (1ul << 25) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PB22F_TCC0_WO2 54L /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 5L +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (1ul << 22) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PB23F_TCC0_WO3 55L /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 5L +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (1ul << 23) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA27F_TCC0_WO5 27L /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 5L +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (1ul << 27) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PA03B_ADC_VREFA 3L /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA 1L +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (1ul << 3) +#define PIN_PA02B_ADC_VREFB 2L /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB 1L +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (1ul << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 2L /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 1L +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (1ul << 2) +#define PIN_PA03B_AC_AIN1 3L /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 1L +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (1ul << 3) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB08B_SLCD_LP2 40L /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 1L +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (1ul << 8) +#define PIN_PB09B_SLCD_LP3 41L /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 1L +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (1ul << 9) +#define PIN_PA04B_SLCD_LP4 4L /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 1L +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (1ul << 4) +#define PIN_PA05B_SLCD_LP5 5L /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 1L +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (1ul << 5) +#define PIN_PA06B_SLCD_LP6 6L /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 1L +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (1ul << 6) +#define PIN_PA07B_SLCD_LP7 7L /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 1L +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (1ul << 7) +#define PIN_PA08B_SLCD_LP11 8L /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 1L +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (1ul << 8) +#define PIN_PA09B_SLCD_LP12 9L /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 1L +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (1ul << 9) +#define PIN_PA10B_SLCD_LP13 10L /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 1L +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (1ul << 10) +#define PIN_PA11B_SLCD_LP14 11L /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 1L +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (1ul << 11) +#define PIN_PB11B_SLCD_LP21 43L /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 1L +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (1ul << 11) +#define PIN_PA12B_SLCD_LP28 12L /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 1L +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (1ul << 12) +#define PIN_PA13B_SLCD_LP29 13L /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 1L +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (1ul << 13) +#define PIN_PA14B_SLCD_LP30 14L /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 1L +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (1ul << 14) +#define PIN_PA15B_SLCD_LP31 15L /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 1L +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (1ul << 15) +#define PIN_PA16B_SLCD_LP32 16L /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 1L +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (1ul << 16) +#define PIN_PA17B_SLCD_LP33 17L /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 1L +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (1ul << 17) +#define PIN_PA18B_SLCD_LP34 18L /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 1L +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (1ul << 18) +#define PIN_PA19B_SLCD_LP35 19L /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 1L +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (1ul << 19) +#define PIN_PA20B_SLCD_LP48 20L /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 1L +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (1ul << 20) +#define PIN_PA21B_SLCD_LP49 21L /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 1L +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (1ul << 21) +#define PIN_PA22B_SLCD_LP50 22L /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 1L +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (1ul << 22) +#define PIN_PA23B_SLCD_LP51 23L /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 1L +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (1ul << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) + +#endif /* _SAML22G16A_PIO_ */ diff --git a/Sensor Watch Starter Project/include/pio/saml22g17a.h b/Sensor Watch Starter Project/include/pio/saml22g17a.h new file mode 100755 index 00000000..989128dd --- /dev/null +++ b/Sensor Watch Starter Project/include/pio/saml22g17a.h @@ -0,0 +1,894 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22G17A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G17A_PIO_ +#define _SAML22G17A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB02G_RTC_IN1 34L /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 6L +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (1ul << 2) +#define PIN_PA02G_RTC_IN2 2L /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 6L +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (1ul << 2) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +#define PIN_PB22G_USB_SOF_1KHZ 54L /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ 6L +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (1ul << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA20C_SERCOM0_PAD0 20L /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 2L +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (1ul << 20) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA21C_SERCOM0_PAD1 21L /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 2L +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (1ul << 21) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA22C_SERCOM0_PAD2 22L /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 2L +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PB22C_SERCOM0_PAD2 54L /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 2L +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +#define PIN_PA23C_SERCOM0_PAD3 23L /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 2L +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (1ul << 23) +#define PIN_PB23C_SERCOM0_PAD3 55L /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 2L +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (1ul << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 3L +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22) +#define PIN_PA16D_SERCOM2_PAD0 16L /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 3L +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 3L +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23) +#define PIN_PA17D_SERCOM2_PAD1 17L /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 3L +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (1ul << 17) +#define PIN_PA18D_SERCOM2_PAD2 18L /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 3L +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM2_PAD2 20L /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 3L +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 2L +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM2_PAD3 19L /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 3L +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM2_PAD3 21L /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 3L +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 2L +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (1ul << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 24L /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 5L +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (1ul << 24) +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PA25F_TCC0_WO1 25L /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 5L +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (1ul << 25) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PB22F_TCC0_WO2 54L /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 5L +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (1ul << 22) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PB23F_TCC0_WO3 55L /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 5L +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (1ul << 23) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA27F_TCC0_WO5 27L /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 5L +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (1ul << 27) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PA03B_ADC_VREFA 3L /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA 1L +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (1ul << 3) +#define PIN_PA02B_ADC_VREFB 2L /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB 1L +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (1ul << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 2L /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 1L +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (1ul << 2) +#define PIN_PA03B_AC_AIN1 3L /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 1L +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (1ul << 3) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB08B_SLCD_LP2 40L /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 1L +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (1ul << 8) +#define PIN_PB09B_SLCD_LP3 41L /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 1L +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (1ul << 9) +#define PIN_PA04B_SLCD_LP4 4L /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 1L +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (1ul << 4) +#define PIN_PA05B_SLCD_LP5 5L /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 1L +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (1ul << 5) +#define PIN_PA06B_SLCD_LP6 6L /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 1L +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (1ul << 6) +#define PIN_PA07B_SLCD_LP7 7L /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 1L +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (1ul << 7) +#define PIN_PA08B_SLCD_LP11 8L /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 1L +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (1ul << 8) +#define PIN_PA09B_SLCD_LP12 9L /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 1L +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (1ul << 9) +#define PIN_PA10B_SLCD_LP13 10L /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 1L +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (1ul << 10) +#define PIN_PA11B_SLCD_LP14 11L /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 1L +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (1ul << 11) +#define PIN_PB11B_SLCD_LP21 43L /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 1L +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (1ul << 11) +#define PIN_PA12B_SLCD_LP28 12L /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 1L +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (1ul << 12) +#define PIN_PA13B_SLCD_LP29 13L /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 1L +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (1ul << 13) +#define PIN_PA14B_SLCD_LP30 14L /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 1L +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (1ul << 14) +#define PIN_PA15B_SLCD_LP31 15L /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 1L +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (1ul << 15) +#define PIN_PA16B_SLCD_LP32 16L /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 1L +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (1ul << 16) +#define PIN_PA17B_SLCD_LP33 17L /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 1L +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (1ul << 17) +#define PIN_PA18B_SLCD_LP34 18L /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 1L +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (1ul << 18) +#define PIN_PA19B_SLCD_LP35 19L /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 1L +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (1ul << 19) +#define PIN_PA20B_SLCD_LP48 20L /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 1L +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (1ul << 20) +#define PIN_PA21B_SLCD_LP49 21L /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 1L +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (1ul << 21) +#define PIN_PA22B_SLCD_LP50 22L /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 1L +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (1ul << 22) +#define PIN_PA23B_SLCD_LP51 23L /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 1L +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (1ul << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) + +#endif /* _SAML22G17A_PIO_ */ diff --git a/Sensor Watch Starter Project/include/pio/saml22g18a.h b/Sensor Watch Starter Project/include/pio/saml22g18a.h new file mode 100755 index 00000000..3391f4d8 --- /dev/null +++ b/Sensor Watch Starter Project/include/pio/saml22g18a.h @@ -0,0 +1,894 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22G18A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G18A_PIO_ +#define _SAML22G18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB02G_RTC_IN1 34L /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 6L +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (1ul << 2) +#define PIN_PA02G_RTC_IN2 2L /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 6L +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (1ul << 2) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +#define PIN_PB22G_USB_SOF_1KHZ 54L /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ 6L +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (1ul << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA20C_SERCOM0_PAD0 20L /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 2L +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (1ul << 20) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA21C_SERCOM0_PAD1 21L /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 2L +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (1ul << 21) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA22C_SERCOM0_PAD2 22L /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 2L +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PB22C_SERCOM0_PAD2 54L /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 2L +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +#define PIN_PA23C_SERCOM0_PAD3 23L /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 2L +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (1ul << 23) +#define PIN_PB23C_SERCOM0_PAD3 55L /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 2L +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (1ul << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 3L +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22) +#define PIN_PA16D_SERCOM2_PAD0 16L /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 3L +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 3L +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23) +#define PIN_PA17D_SERCOM2_PAD1 17L /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 3L +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (1ul << 17) +#define PIN_PA18D_SERCOM2_PAD2 18L /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 3L +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM2_PAD2 20L /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 3L +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 2L +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM2_PAD3 19L /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 3L +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM2_PAD3 21L /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 3L +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 2L +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (1ul << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 24L /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 5L +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (1ul << 24) +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PA25F_TCC0_WO1 25L /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 5L +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (1ul << 25) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PB22F_TCC0_WO2 54L /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 5L +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (1ul << 22) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PB23F_TCC0_WO3 55L /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 5L +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (1ul << 23) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA27F_TCC0_WO5 27L /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 5L +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (1ul << 27) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PA03B_ADC_VREFA 3L /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA 1L +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (1ul << 3) +#define PIN_PA02B_ADC_VREFB 2L /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB 1L +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (1ul << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 2L /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 1L +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (1ul << 2) +#define PIN_PA03B_AC_AIN1 3L /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 1L +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (1ul << 3) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB08B_SLCD_LP2 40L /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 1L +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (1ul << 8) +#define PIN_PB09B_SLCD_LP3 41L /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 1L +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (1ul << 9) +#define PIN_PA04B_SLCD_LP4 4L /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 1L +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (1ul << 4) +#define PIN_PA05B_SLCD_LP5 5L /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 1L +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (1ul << 5) +#define PIN_PA06B_SLCD_LP6 6L /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 1L +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (1ul << 6) +#define PIN_PA07B_SLCD_LP7 7L /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 1L +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (1ul << 7) +#define PIN_PA08B_SLCD_LP11 8L /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 1L +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (1ul << 8) +#define PIN_PA09B_SLCD_LP12 9L /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 1L +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (1ul << 9) +#define PIN_PA10B_SLCD_LP13 10L /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 1L +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (1ul << 10) +#define PIN_PA11B_SLCD_LP14 11L /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 1L +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (1ul << 11) +#define PIN_PB11B_SLCD_LP21 43L /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 1L +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (1ul << 11) +#define PIN_PA12B_SLCD_LP28 12L /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 1L +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (1ul << 12) +#define PIN_PA13B_SLCD_LP29 13L /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 1L +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (1ul << 13) +#define PIN_PA14B_SLCD_LP30 14L /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 1L +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (1ul << 14) +#define PIN_PA15B_SLCD_LP31 15L /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 1L +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (1ul << 15) +#define PIN_PA16B_SLCD_LP32 16L /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 1L +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (1ul << 16) +#define PIN_PA17B_SLCD_LP33 17L /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 1L +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (1ul << 17) +#define PIN_PA18B_SLCD_LP34 18L /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 1L +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (1ul << 18) +#define PIN_PA19B_SLCD_LP35 19L /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 1L +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (1ul << 19) +#define PIN_PA20B_SLCD_LP48 20L /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 1L +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (1ul << 20) +#define PIN_PA21B_SLCD_LP49 21L /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 1L +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (1ul << 21) +#define PIN_PA22B_SLCD_LP50 22L /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 1L +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (1ul << 22) +#define PIN_PA23B_SLCD_LP51 23L /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 1L +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (1ul << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) + +#endif /* _SAML22G18A_PIO_ */ diff --git a/Sensor Watch Starter Project/include/pio/saml22j16a.h b/Sensor Watch Starter Project/include/pio/saml22j16a.h new file mode 100755 index 00000000..9ff66dc9 --- /dev/null +++ b/Sensor Watch Starter Project/include/pio/saml22j16a.h @@ -0,0 +1,1235 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22J16A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J16A_PIO_ +#define _SAML22J16A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 7L +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (1ul << 1) +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK 7L +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (1ul << 0) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 7L +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (1ul << 14) +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 7L +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (1ul << 15) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 7L +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (1ul << 16) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 7L +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 32L /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 6L +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (1ul << 0) +#define PIN_PB02G_RTC_IN1 34L /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 6L +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (1ul << 2) +#define PIN_PA02G_RTC_IN2 2L /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 6L +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (1ul << 2) +#define PIN_PB01F_RTC_IN2 33L /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 5L +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (1ul << 1) +#define PIN_PB01G_RTC_OUT 33L /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT 6L +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (1ul << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 0L +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 0L +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 0L +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 0L +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 0L +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 0L +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 0L +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 0L +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 0L +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 0L +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 0L +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 0L +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 0L +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 0L +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +#define PIN_PB22G_USB_SOF_1KHZ 54L /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ 6L +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (1ul << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA20C_SERCOM0_PAD0 20L /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 2L +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (1ul << 20) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA21C_SERCOM0_PAD1 21L /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 2L +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (1ul << 21) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA22C_SERCOM0_PAD2 22L /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 2L +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PB22C_SERCOM0_PAD2 54L /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 2L +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +#define PIN_PA23C_SERCOM0_PAD3 23L /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 2L +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (1ul << 23) +#define PIN_PB23C_SERCOM0_PAD3 55L /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 2L +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (1ul << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 62L /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 2L +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (1ul << 30) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PB31C_SERCOM1_PAD1 63L /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 2L +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (1ul << 31) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 3L +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22) +#define PIN_PA16D_SERCOM2_PAD0 16L /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 3L +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 3L +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23) +#define PIN_PA17D_SERCOM2_PAD1 17L /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 3L +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (1ul << 17) +#define PIN_PA18D_SERCOM2_PAD2 18L /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 3L +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM2_PAD2 20L /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 3L +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 2L +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM2_PAD3 19L /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 3L +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM2_PAD3 21L /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 3L +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 2L +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 44L /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 2L +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (1ul << 12) +#define PIN_PA12D_SERCOM3_PAD0 12L /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 3L +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM3_PAD0 40L /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 3L +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (1ul << 8) +#define PIN_PB02C_SERCOM3_PAD0 34L /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 2L +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (1ul << 2) +#define PIN_PB13C_SERCOM3_PAD1 45L /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 2L +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (1ul << 13) +#define PIN_PA13D_SERCOM3_PAD1 13L /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 3L +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM3_PAD1 41L /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 3L +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (1ul << 9) +#define PIN_PB03C_SERCOM3_PAD1 35L /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 2L +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (1ul << 3) +#define PIN_PB14C_SERCOM3_PAD2 46L /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 2L +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (1ul << 14) +#define PIN_PA14D_SERCOM3_PAD2 14L /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 3L +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (1ul << 14) +#define PIN_PB00C_SERCOM3_PAD2 32L /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 2L +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (1ul << 0) +#define PIN_PB15C_SERCOM3_PAD3 47L /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 2L +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (1ul << 15) +#define PIN_PA15D_SERCOM3_PAD3 15L /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 3L +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM3_PAD3 43L /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 3L +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (1ul << 11) +#define PIN_PB01C_SERCOM3_PAD3 33L /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 2L +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (1ul << 1) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 24L /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 5L +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (1ul << 24) +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 4L +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (1ul << 30) +#define PIN_PA25F_TCC0_WO1 25L /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 5L +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (1ul << 25) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 4L +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (1ul << 31) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PB22F_TCC0_WO2 54L /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 5L +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (1ul << 22) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PB23F_TCC0_WO3 55L /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 5L +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (1ul << 23) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 5L +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (1ul << 16) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA27F_TCC0_WO5 27L /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 5L +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (1ul << 27) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 5L +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (1ul << 17) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 5L +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (1ul << 12) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 5L +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (1ul << 13) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 4L +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (1ul << 12) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 4L +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (1ul << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 4L +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (1ul << 14) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 4L +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (1ul << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 4L +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (1ul << 16) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 4L +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (1ul << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 4L +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (1ul << 0) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 4L +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (1ul << 1) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 1L +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (1ul << 0) +#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 1L +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (1ul << 1) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 1L +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (1ul << 4) +#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 1L +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (1ul << 5) +#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 1L +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (1ul << 6) +#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 1L +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (1ul << 7) +#define PIN_PA03B_ADC_VREFA 3L /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA 1L +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (1ul << 3) +#define PIN_PA02B_ADC_VREFB 2L /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB 1L +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (1ul << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 2L /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 1L +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (1ul << 2) +#define PIN_PA03B_AC_AIN1 3L /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 1L +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (1ul << 3) +#define PIN_PB04B_AC_AIN2 36L /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 1L +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (1ul << 4) +#define PIN_PB05B_AC_AIN3 37L /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 1L +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (1ul << 5) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 38L /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 1L +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (1ul << 6) +#define PIN_PB07B_SLCD_LP1 39L /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 1L +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (1ul << 7) +#define PIN_PB08B_SLCD_LP2 40L /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 1L +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (1ul << 8) +#define PIN_PB09B_SLCD_LP3 41L /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 1L +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (1ul << 9) +#define PIN_PA04B_SLCD_LP4 4L /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 1L +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (1ul << 4) +#define PIN_PA05B_SLCD_LP5 5L /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 1L +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (1ul << 5) +#define PIN_PA06B_SLCD_LP6 6L /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 1L +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (1ul << 6) +#define PIN_PA07B_SLCD_LP7 7L /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 1L +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (1ul << 7) +#define PIN_PA08B_SLCD_LP11 8L /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 1L +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (1ul << 8) +#define PIN_PA09B_SLCD_LP12 9L /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 1L +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (1ul << 9) +#define PIN_PA10B_SLCD_LP13 10L /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 1L +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (1ul << 10) +#define PIN_PA11B_SLCD_LP14 11L /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 1L +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (1ul << 11) +#define PIN_PB11B_SLCD_LP21 43L /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 1L +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (1ul << 11) +#define PIN_PB12B_SLCD_LP22 44L /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 1L +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (1ul << 12) +#define PIN_PB13B_SLCD_LP23 45L /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 1L +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (1ul << 13) +#define PIN_PB14B_SLCD_LP24 46L /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 1L +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (1ul << 14) +#define PIN_PB15B_SLCD_LP25 47L /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 1L +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (1ul << 15) +#define PIN_PA12B_SLCD_LP28 12L /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 1L +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (1ul << 12) +#define PIN_PA13B_SLCD_LP29 13L /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 1L +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (1ul << 13) +#define PIN_PA14B_SLCD_LP30 14L /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 1L +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (1ul << 14) +#define PIN_PA15B_SLCD_LP31 15L /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 1L +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (1ul << 15) +#define PIN_PA16B_SLCD_LP32 16L /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 1L +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (1ul << 16) +#define PIN_PA17B_SLCD_LP33 17L /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 1L +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (1ul << 17) +#define PIN_PA18B_SLCD_LP34 18L /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 1L +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (1ul << 18) +#define PIN_PA19B_SLCD_LP35 19L /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 1L +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (1ul << 19) +#define PIN_PB16B_SLCD_LP42 48L /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 1L +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (1ul << 16) +#define PIN_PB17B_SLCD_LP43 49L /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 1L +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (1ul << 17) +#define PIN_PA20B_SLCD_LP48 20L /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 1L +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (1ul << 20) +#define PIN_PA21B_SLCD_LP49 21L /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 1L +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (1ul << 21) +#define PIN_PA22B_SLCD_LP50 22L /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 1L +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (1ul << 22) +#define PIN_PA23B_SLCD_LP51 23L /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 1L +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (1ul << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 8L +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (1ul << 0) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 8L +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (1ul << 1) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 8L +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (1ul << 6) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 8L +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (1ul << 7) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 8L +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (1ul << 14) +#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 8L +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (1ul << 15) +#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 8L +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (1ul << 16) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) +#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 8L +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (1ul << 17) + +#endif /* _SAML22J16A_PIO_ */ diff --git a/Sensor Watch Starter Project/include/pio/saml22j17a.h b/Sensor Watch Starter Project/include/pio/saml22j17a.h new file mode 100755 index 00000000..81fce1cb --- /dev/null +++ b/Sensor Watch Starter Project/include/pio/saml22j17a.h @@ -0,0 +1,1235 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22J17A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J17A_PIO_ +#define _SAML22J17A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 7L +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (1ul << 1) +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK 7L +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (1ul << 0) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 7L +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (1ul << 14) +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 7L +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (1ul << 15) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 7L +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (1ul << 16) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 7L +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 32L /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 6L +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (1ul << 0) +#define PIN_PB02G_RTC_IN1 34L /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 6L +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (1ul << 2) +#define PIN_PA02G_RTC_IN2 2L /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 6L +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (1ul << 2) +#define PIN_PB01F_RTC_IN2 33L /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 5L +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (1ul << 1) +#define PIN_PB01G_RTC_OUT 33L /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT 6L +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (1ul << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 0L +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 0L +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 0L +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 0L +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 0L +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 0L +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 0L +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 0L +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 0L +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 0L +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 0L +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 0L +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 0L +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 0L +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +#define PIN_PB22G_USB_SOF_1KHZ 54L /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ 6L +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (1ul << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA20C_SERCOM0_PAD0 20L /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 2L +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (1ul << 20) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA21C_SERCOM0_PAD1 21L /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 2L +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (1ul << 21) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA22C_SERCOM0_PAD2 22L /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 2L +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PB22C_SERCOM0_PAD2 54L /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 2L +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +#define PIN_PA23C_SERCOM0_PAD3 23L /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 2L +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (1ul << 23) +#define PIN_PB23C_SERCOM0_PAD3 55L /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 2L +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (1ul << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 62L /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 2L +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (1ul << 30) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PB31C_SERCOM1_PAD1 63L /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 2L +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (1ul << 31) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 3L +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22) +#define PIN_PA16D_SERCOM2_PAD0 16L /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 3L +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 3L +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23) +#define PIN_PA17D_SERCOM2_PAD1 17L /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 3L +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (1ul << 17) +#define PIN_PA18D_SERCOM2_PAD2 18L /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 3L +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM2_PAD2 20L /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 3L +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 2L +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM2_PAD3 19L /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 3L +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM2_PAD3 21L /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 3L +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 2L +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 44L /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 2L +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (1ul << 12) +#define PIN_PA12D_SERCOM3_PAD0 12L /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 3L +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM3_PAD0 40L /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 3L +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (1ul << 8) +#define PIN_PB02C_SERCOM3_PAD0 34L /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 2L +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (1ul << 2) +#define PIN_PB13C_SERCOM3_PAD1 45L /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 2L +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (1ul << 13) +#define PIN_PA13D_SERCOM3_PAD1 13L /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 3L +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM3_PAD1 41L /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 3L +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (1ul << 9) +#define PIN_PB03C_SERCOM3_PAD1 35L /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 2L +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (1ul << 3) +#define PIN_PB14C_SERCOM3_PAD2 46L /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 2L +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (1ul << 14) +#define PIN_PA14D_SERCOM3_PAD2 14L /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 3L +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (1ul << 14) +#define PIN_PB00C_SERCOM3_PAD2 32L /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 2L +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (1ul << 0) +#define PIN_PB15C_SERCOM3_PAD3 47L /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 2L +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (1ul << 15) +#define PIN_PA15D_SERCOM3_PAD3 15L /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 3L +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM3_PAD3 43L /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 3L +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (1ul << 11) +#define PIN_PB01C_SERCOM3_PAD3 33L /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 2L +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (1ul << 1) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 24L /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 5L +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (1ul << 24) +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 4L +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (1ul << 30) +#define PIN_PA25F_TCC0_WO1 25L /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 5L +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (1ul << 25) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 4L +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (1ul << 31) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PB22F_TCC0_WO2 54L /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 5L +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (1ul << 22) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PB23F_TCC0_WO3 55L /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 5L +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (1ul << 23) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 5L +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (1ul << 16) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA27F_TCC0_WO5 27L /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 5L +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (1ul << 27) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 5L +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (1ul << 17) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 5L +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (1ul << 12) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 5L +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (1ul << 13) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 4L +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (1ul << 12) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 4L +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (1ul << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 4L +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (1ul << 14) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 4L +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (1ul << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 4L +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (1ul << 16) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 4L +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (1ul << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 4L +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (1ul << 0) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 4L +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (1ul << 1) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 1L +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (1ul << 0) +#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 1L +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (1ul << 1) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 1L +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (1ul << 4) +#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 1L +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (1ul << 5) +#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 1L +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (1ul << 6) +#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 1L +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (1ul << 7) +#define PIN_PA03B_ADC_VREFA 3L /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA 1L +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (1ul << 3) +#define PIN_PA02B_ADC_VREFB 2L /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB 1L +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (1ul << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 2L /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 1L +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (1ul << 2) +#define PIN_PA03B_AC_AIN1 3L /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 1L +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (1ul << 3) +#define PIN_PB04B_AC_AIN2 36L /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 1L +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (1ul << 4) +#define PIN_PB05B_AC_AIN3 37L /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 1L +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (1ul << 5) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 38L /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 1L +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (1ul << 6) +#define PIN_PB07B_SLCD_LP1 39L /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 1L +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (1ul << 7) +#define PIN_PB08B_SLCD_LP2 40L /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 1L +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (1ul << 8) +#define PIN_PB09B_SLCD_LP3 41L /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 1L +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (1ul << 9) +#define PIN_PA04B_SLCD_LP4 4L /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 1L +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (1ul << 4) +#define PIN_PA05B_SLCD_LP5 5L /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 1L +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (1ul << 5) +#define PIN_PA06B_SLCD_LP6 6L /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 1L +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (1ul << 6) +#define PIN_PA07B_SLCD_LP7 7L /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 1L +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (1ul << 7) +#define PIN_PA08B_SLCD_LP11 8L /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 1L +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (1ul << 8) +#define PIN_PA09B_SLCD_LP12 9L /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 1L +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (1ul << 9) +#define PIN_PA10B_SLCD_LP13 10L /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 1L +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (1ul << 10) +#define PIN_PA11B_SLCD_LP14 11L /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 1L +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (1ul << 11) +#define PIN_PB11B_SLCD_LP21 43L /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 1L +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (1ul << 11) +#define PIN_PB12B_SLCD_LP22 44L /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 1L +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (1ul << 12) +#define PIN_PB13B_SLCD_LP23 45L /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 1L +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (1ul << 13) +#define PIN_PB14B_SLCD_LP24 46L /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 1L +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (1ul << 14) +#define PIN_PB15B_SLCD_LP25 47L /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 1L +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (1ul << 15) +#define PIN_PA12B_SLCD_LP28 12L /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 1L +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (1ul << 12) +#define PIN_PA13B_SLCD_LP29 13L /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 1L +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (1ul << 13) +#define PIN_PA14B_SLCD_LP30 14L /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 1L +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (1ul << 14) +#define PIN_PA15B_SLCD_LP31 15L /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 1L +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (1ul << 15) +#define PIN_PA16B_SLCD_LP32 16L /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 1L +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (1ul << 16) +#define PIN_PA17B_SLCD_LP33 17L /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 1L +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (1ul << 17) +#define PIN_PA18B_SLCD_LP34 18L /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 1L +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (1ul << 18) +#define PIN_PA19B_SLCD_LP35 19L /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 1L +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (1ul << 19) +#define PIN_PB16B_SLCD_LP42 48L /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 1L +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (1ul << 16) +#define PIN_PB17B_SLCD_LP43 49L /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 1L +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (1ul << 17) +#define PIN_PA20B_SLCD_LP48 20L /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 1L +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (1ul << 20) +#define PIN_PA21B_SLCD_LP49 21L /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 1L +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (1ul << 21) +#define PIN_PA22B_SLCD_LP50 22L /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 1L +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (1ul << 22) +#define PIN_PA23B_SLCD_LP51 23L /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 1L +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (1ul << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 8L +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (1ul << 0) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 8L +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (1ul << 1) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 8L +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (1ul << 6) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 8L +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (1ul << 7) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 8L +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (1ul << 14) +#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 8L +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (1ul << 15) +#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 8L +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (1ul << 16) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) +#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 8L +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (1ul << 17) + +#endif /* _SAML22J17A_PIO_ */ diff --git a/Sensor Watch Starter Project/include/pio/saml22j18a.h b/Sensor Watch Starter Project/include/pio/saml22j18a.h new file mode 100755 index 00000000..6d25d8c8 --- /dev/null +++ b/Sensor Watch Starter Project/include/pio/saml22j18a.h @@ -0,0 +1,1235 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22J18A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J18A_PIO_ +#define _SAML22J18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 7L +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (1ul << 1) +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK 7L +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (1ul << 0) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 7L +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (1ul << 14) +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 7L +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (1ul << 15) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 7L +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (1ul << 16) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 7L +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 32L /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 6L +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (1ul << 0) +#define PIN_PB02G_RTC_IN1 34L /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 6L +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (1ul << 2) +#define PIN_PA02G_RTC_IN2 2L /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 6L +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (1ul << 2) +#define PIN_PB01F_RTC_IN2 33L /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 5L +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (1ul << 1) +#define PIN_PB01G_RTC_OUT 33L /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT 6L +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (1ul << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 0L +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 0L +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 0L +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 0L +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 0L +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 0L +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 0L +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 0L +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 0L +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 0L +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 0L +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 0L +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 0L +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 0L +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +#define PIN_PB22G_USB_SOF_1KHZ 54L /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ 6L +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (1ul << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA20C_SERCOM0_PAD0 20L /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 2L +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (1ul << 20) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA21C_SERCOM0_PAD1 21L /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 2L +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (1ul << 21) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA22C_SERCOM0_PAD2 22L /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 2L +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PB22C_SERCOM0_PAD2 54L /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 2L +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +#define PIN_PA23C_SERCOM0_PAD3 23L /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 2L +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (1ul << 23) +#define PIN_PB23C_SERCOM0_PAD3 55L /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 2L +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (1ul << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 62L /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 2L +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (1ul << 30) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PB31C_SERCOM1_PAD1 63L /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 2L +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (1ul << 31) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 3L +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22) +#define PIN_PA16D_SERCOM2_PAD0 16L /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 3L +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 3L +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23) +#define PIN_PA17D_SERCOM2_PAD1 17L /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 3L +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (1ul << 17) +#define PIN_PA18D_SERCOM2_PAD2 18L /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 3L +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM2_PAD2 20L /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 3L +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 2L +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM2_PAD3 19L /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 3L +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM2_PAD3 21L /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 3L +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 2L +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 44L /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 2L +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (1ul << 12) +#define PIN_PA12D_SERCOM3_PAD0 12L /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 3L +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM3_PAD0 40L /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 3L +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (1ul << 8) +#define PIN_PB02C_SERCOM3_PAD0 34L /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 2L +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (1ul << 2) +#define PIN_PB13C_SERCOM3_PAD1 45L /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 2L +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (1ul << 13) +#define PIN_PA13D_SERCOM3_PAD1 13L /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 3L +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM3_PAD1 41L /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 3L +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (1ul << 9) +#define PIN_PB03C_SERCOM3_PAD1 35L /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 2L +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (1ul << 3) +#define PIN_PB14C_SERCOM3_PAD2 46L /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 2L +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (1ul << 14) +#define PIN_PA14D_SERCOM3_PAD2 14L /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 3L +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (1ul << 14) +#define PIN_PB00C_SERCOM3_PAD2 32L /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 2L +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (1ul << 0) +#define PIN_PB15C_SERCOM3_PAD3 47L /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 2L +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (1ul << 15) +#define PIN_PA15D_SERCOM3_PAD3 15L /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 3L +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM3_PAD3 43L /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 3L +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (1ul << 11) +#define PIN_PB01C_SERCOM3_PAD3 33L /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 2L +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (1ul << 1) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 24L /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 5L +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (1ul << 24) +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 4L +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (1ul << 30) +#define PIN_PA25F_TCC0_WO1 25L /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 5L +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (1ul << 25) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 4L +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (1ul << 31) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PB22F_TCC0_WO2 54L /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 5L +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (1ul << 22) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PB23F_TCC0_WO3 55L /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 5L +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (1ul << 23) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 5L +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (1ul << 16) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA27F_TCC0_WO5 27L /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 5L +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (1ul << 27) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 5L +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (1ul << 17) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 5L +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (1ul << 12) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 5L +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (1ul << 13) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 4L +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (1ul << 12) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 4L +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (1ul << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 4L +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (1ul << 14) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 4L +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (1ul << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 4L +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (1ul << 16) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 4L +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (1ul << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 4L +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (1ul << 0) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 4L +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (1ul << 1) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 1L +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (1ul << 0) +#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 1L +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (1ul << 1) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 1L +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (1ul << 4) +#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 1L +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (1ul << 5) +#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 1L +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (1ul << 6) +#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 1L +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (1ul << 7) +#define PIN_PA03B_ADC_VREFA 3L /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA 1L +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (1ul << 3) +#define PIN_PA02B_ADC_VREFB 2L /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB 1L +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (1ul << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 2L /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 1L +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (1ul << 2) +#define PIN_PA03B_AC_AIN1 3L /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 1L +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (1ul << 3) +#define PIN_PB04B_AC_AIN2 36L /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 1L +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (1ul << 4) +#define PIN_PB05B_AC_AIN3 37L /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 1L +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (1ul << 5) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 38L /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 1L +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (1ul << 6) +#define PIN_PB07B_SLCD_LP1 39L /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 1L +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (1ul << 7) +#define PIN_PB08B_SLCD_LP2 40L /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 1L +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (1ul << 8) +#define PIN_PB09B_SLCD_LP3 41L /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 1L +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (1ul << 9) +#define PIN_PA04B_SLCD_LP4 4L /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 1L +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (1ul << 4) +#define PIN_PA05B_SLCD_LP5 5L /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 1L +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (1ul << 5) +#define PIN_PA06B_SLCD_LP6 6L /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 1L +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (1ul << 6) +#define PIN_PA07B_SLCD_LP7 7L /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 1L +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (1ul << 7) +#define PIN_PA08B_SLCD_LP11 8L /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 1L +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (1ul << 8) +#define PIN_PA09B_SLCD_LP12 9L /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 1L +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (1ul << 9) +#define PIN_PA10B_SLCD_LP13 10L /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 1L +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (1ul << 10) +#define PIN_PA11B_SLCD_LP14 11L /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 1L +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (1ul << 11) +#define PIN_PB11B_SLCD_LP21 43L /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 1L +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (1ul << 11) +#define PIN_PB12B_SLCD_LP22 44L /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 1L +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (1ul << 12) +#define PIN_PB13B_SLCD_LP23 45L /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 1L +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (1ul << 13) +#define PIN_PB14B_SLCD_LP24 46L /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 1L +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (1ul << 14) +#define PIN_PB15B_SLCD_LP25 47L /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 1L +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (1ul << 15) +#define PIN_PA12B_SLCD_LP28 12L /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 1L +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (1ul << 12) +#define PIN_PA13B_SLCD_LP29 13L /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 1L +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (1ul << 13) +#define PIN_PA14B_SLCD_LP30 14L /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 1L +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (1ul << 14) +#define PIN_PA15B_SLCD_LP31 15L /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 1L +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (1ul << 15) +#define PIN_PA16B_SLCD_LP32 16L /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 1L +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (1ul << 16) +#define PIN_PA17B_SLCD_LP33 17L /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 1L +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (1ul << 17) +#define PIN_PA18B_SLCD_LP34 18L /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 1L +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (1ul << 18) +#define PIN_PA19B_SLCD_LP35 19L /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 1L +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (1ul << 19) +#define PIN_PB16B_SLCD_LP42 48L /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 1L +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (1ul << 16) +#define PIN_PB17B_SLCD_LP43 49L /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 1L +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (1ul << 17) +#define PIN_PA20B_SLCD_LP48 20L /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 1L +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (1ul << 20) +#define PIN_PA21B_SLCD_LP49 21L /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 1L +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (1ul << 21) +#define PIN_PA22B_SLCD_LP50 22L /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 1L +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (1ul << 22) +#define PIN_PA23B_SLCD_LP51 23L /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 1L +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (1ul << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 8L +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (1ul << 0) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 8L +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (1ul << 1) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 8L +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (1ul << 6) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 8L +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (1ul << 7) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 8L +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (1ul << 14) +#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 8L +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (1ul << 15) +#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 8L +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (1ul << 16) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) +#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 8L +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (1ul << 17) + +#endif /* _SAML22J18A_PIO_ */ diff --git a/Sensor Watch Starter Project/include/pio/saml22n16a.h b/Sensor Watch Starter Project/include/pio/saml22n16a.h new file mode 100755 index 00000000..87834efb --- /dev/null +++ b/Sensor Watch Starter Project/include/pio/saml22n16a.h @@ -0,0 +1,1789 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22N16A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N16A_PIO_ +#define _SAML22N16A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (1ul << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (1ul << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (1ul << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (1ul << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (1ul << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (1ul << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (1ul << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (1ul << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (1ul << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (1ul << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (1ul << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (1ul << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (1ul << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC08 72 /**< \brief Pin Number for PC08 */ +#define PORT_PC08 (1ul << 8) /**< \brief PORT Mask for PC08 */ +#define PIN_PC09 73 /**< \brief Pin Number for PC09 */ +#define PORT_PC09 (1ul << 9) /**< \brief PORT Mask for PC09 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (1ul << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (1ul << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (1ul << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (1ul << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (1ul << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (1ul << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (1ul << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (1ul << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (1ul << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (1ul << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (1ul << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (1ul << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (1ul << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (1ul << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 7L +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (1ul << 1) +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK 7L +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (1ul << 0) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 7L +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (1ul << 14) +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 7L +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (1ul << 15) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 7L +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (1ul << 16) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 7L +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 32L /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 6L +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (1ul << 0) +#define PIN_PB02G_RTC_IN1 34L /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 6L +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (1ul << 2) +#define PIN_PA02G_RTC_IN2 2L /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 6L +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (1ul << 2) +#define PIN_PB01F_RTC_IN2 33L /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 5L +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (1ul << 1) +#define PIN_PC00G_RTC_IN3 64L /**< \brief RTC signal: IN3 on PC00 mux G */ +#define MUX_PC00G_RTC_IN3 6L +#define PINMUX_PC00G_RTC_IN3 ((PIN_PC00G_RTC_IN3 << 16) | MUX_PC00G_RTC_IN3) +#define PORT_PC00G_RTC_IN3 (1ul << 0) +#define PIN_PC01G_RTC_IN4 65L /**< \brief RTC signal: IN4 on PC01 mux G */ +#define MUX_PC01G_RTC_IN4 6L +#define PINMUX_PC01G_RTC_IN4 ((PIN_PC01G_RTC_IN4 << 16) | MUX_PC01G_RTC_IN4) +#define PORT_PC01G_RTC_IN4 (1ul << 1) +#define PIN_PB01G_RTC_OUT 33L /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT 6L +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (1ul << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 0L +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 0L +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PC08A_EIC_EXTINT0 72L /**< \brief EIC signal: EXTINT0 on PC08 mux A */ +#define MUX_PC08A_EIC_EXTINT0 0L +#define PINMUX_PC08A_EIC_EXTINT0 ((PIN_PC08A_EIC_EXTINT0 << 16) | MUX_PC08A_EIC_EXTINT0) +#define PORT_PC08A_EIC_EXTINT0 (1ul << 8) +#define PIN_PC24A_EIC_EXTINT0 88L /**< \brief EIC signal: EXTINT0 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT0 0L +#define PINMUX_PC24A_EIC_EXTINT0 ((PIN_PC24A_EIC_EXTINT0 << 16) | MUX_PC24A_EIC_EXTINT0) +#define PORT_PC24A_EIC_EXTINT0 (1ul << 24) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 0L +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 0L +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PC09A_EIC_EXTINT1 73L /**< \brief EIC signal: EXTINT1 on PC09 mux A */ +#define MUX_PC09A_EIC_EXTINT1 0L +#define PINMUX_PC09A_EIC_EXTINT1 ((PIN_PC09A_EIC_EXTINT1 << 16) | MUX_PC09A_EIC_EXTINT1) +#define PORT_PC09A_EIC_EXTINT1 (1ul << 9) +#define PIN_PC25A_EIC_EXTINT1 89L /**< \brief EIC signal: EXTINT1 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT1 0L +#define PINMUX_PC25A_EIC_EXTINT1 ((PIN_PC25A_EIC_EXTINT1 << 16) | MUX_PC25A_EIC_EXTINT1) +#define PORT_PC25A_EIC_EXTINT1 (1ul << 25) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PB18A_EIC_EXTINT2 50L /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 0L +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PC10A_EIC_EXTINT2 74L /**< \brief EIC signal: EXTINT2 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT2 0L +#define PINMUX_PC10A_EIC_EXTINT2 ((PIN_PC10A_EIC_EXTINT2 << 16) | MUX_PC10A_EIC_EXTINT2) +#define PORT_PC10A_EIC_EXTINT2 (1ul << 10) +#define PIN_PC26A_EIC_EXTINT2 90L /**< \brief EIC signal: EXTINT2 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT2 0L +#define PINMUX_PC26A_EIC_EXTINT2 ((PIN_PC26A_EIC_EXTINT2 << 16) | MUX_PC26A_EIC_EXTINT2) +#define PORT_PC26A_EIC_EXTINT2 (1ul << 26) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PB19A_EIC_EXTINT3 51L /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 0L +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PC11A_EIC_EXTINT3 75L /**< \brief EIC signal: EXTINT3 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT3 0L +#define PINMUX_PC11A_EIC_EXTINT3 ((PIN_PC11A_EIC_EXTINT3 << 16) | MUX_PC11A_EIC_EXTINT3) +#define PORT_PC11A_EIC_EXTINT3 (1ul << 11) +#define PIN_PC27A_EIC_EXTINT3 91L /**< \brief EIC signal: EXTINT3 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT3 0L +#define PINMUX_PC27A_EIC_EXTINT3 ((PIN_PC27A_EIC_EXTINT3 << 16) | MUX_PC27A_EIC_EXTINT3) +#define PORT_PC27A_EIC_EXTINT3 (1ul << 27) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 0L +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PB20A_EIC_EXTINT4 52L /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 0L +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PC12A_EIC_EXTINT4 76L /**< \brief EIC signal: EXTINT4 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT4 0L +#define PINMUX_PC12A_EIC_EXTINT4 ((PIN_PC12A_EIC_EXTINT4 << 16) | MUX_PC12A_EIC_EXTINT4) +#define PORT_PC12A_EIC_EXTINT4 (1ul << 12) +#define PIN_PC28A_EIC_EXTINT4 92L /**< \brief EIC signal: EXTINT4 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT4 0L +#define PINMUX_PC28A_EIC_EXTINT4 ((PIN_PC28A_EIC_EXTINT4 << 16) | MUX_PC28A_EIC_EXTINT4) +#define PORT_PC28A_EIC_EXTINT4 (1ul << 28) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 0L +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PB21A_EIC_EXTINT5 53L /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 0L +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PC13A_EIC_EXTINT5 77L /**< \brief EIC signal: EXTINT5 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT5 0L +#define PINMUX_PC13A_EIC_EXTINT5 ((PIN_PC13A_EIC_EXTINT5 << 16) | MUX_PC13A_EIC_EXTINT5) +#define PORT_PC13A_EIC_EXTINT5 (1ul << 13) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 0L +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PC14A_EIC_EXTINT6 78L /**< \brief EIC signal: EXTINT6 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT6 0L +#define PINMUX_PC14A_EIC_EXTINT6 ((PIN_PC14A_EIC_EXTINT6 << 16) | MUX_PC14A_EIC_EXTINT6) +#define PORT_PC14A_EIC_EXTINT6 (1ul << 14) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 0L +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PC15A_EIC_EXTINT7 79L /**< \brief EIC signal: EXTINT7 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT7 0L +#define PINMUX_PC15A_EIC_EXTINT7 ((PIN_PC15A_EIC_EXTINT7 << 16) | MUX_PC15A_EIC_EXTINT7) +#define PORT_PC15A_EIC_EXTINT7 (1ul << 15) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PB24A_EIC_EXTINT8 56L /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 0L +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (1ul << 24) +#define PIN_PC00A_EIC_EXTINT8 64L /**< \brief EIC signal: EXTINT8 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT8 0L +#define PINMUX_PC00A_EIC_EXTINT8 ((PIN_PC00A_EIC_EXTINT8 << 16) | MUX_PC00A_EIC_EXTINT8) +#define PORT_PC00A_EIC_EXTINT8 (1ul << 0) +#define PIN_PC16A_EIC_EXTINT8 80L /**< \brief EIC signal: EXTINT8 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT8 0L +#define PINMUX_PC16A_EIC_EXTINT8 ((PIN_PC16A_EIC_EXTINT8 << 16) | MUX_PC16A_EIC_EXTINT8) +#define PORT_PC16A_EIC_EXTINT8 (1ul << 16) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB25A_EIC_EXTINT9 57L /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 0L +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (1ul << 25) +#define PIN_PC01A_EIC_EXTINT9 65L /**< \brief EIC signal: EXTINT9 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT9 0L +#define PINMUX_PC01A_EIC_EXTINT9 ((PIN_PC01A_EIC_EXTINT9 << 16) | MUX_PC01A_EIC_EXTINT9) +#define PORT_PC01A_EIC_EXTINT9 (1ul << 1) +#define PIN_PC17A_EIC_EXTINT9 81L /**< \brief EIC signal: EXTINT9 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT9 0L +#define PINMUX_PC17A_EIC_EXTINT9 ((PIN_PC17A_EIC_EXTINT9 << 16) | MUX_PC17A_EIC_EXTINT9) +#define PORT_PC17A_EIC_EXTINT9 (1ul << 17) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PC02A_EIC_EXTINT10 66L /**< \brief EIC signal: EXTINT10 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT10 0L +#define PINMUX_PC02A_EIC_EXTINT10 ((PIN_PC02A_EIC_EXTINT10 << 16) | MUX_PC02A_EIC_EXTINT10) +#define PORT_PC02A_EIC_EXTINT10 (1ul << 2) +#define PIN_PC18A_EIC_EXTINT10 82L /**< \brief EIC signal: EXTINT10 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT10 0L +#define PINMUX_PC18A_EIC_EXTINT10 ((PIN_PC18A_EIC_EXTINT10 << 16) | MUX_PC18A_EIC_EXTINT10) +#define PORT_PC18A_EIC_EXTINT10 (1ul << 18) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PC03A_EIC_EXTINT11 67L /**< \brief EIC signal: EXTINT11 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT11 0L +#define PINMUX_PC03A_EIC_EXTINT11 ((PIN_PC03A_EIC_EXTINT11 << 16) | MUX_PC03A_EIC_EXTINT11) +#define PORT_PC03A_EIC_EXTINT11 (1ul << 3) +#define PIN_PC19A_EIC_EXTINT11 83L /**< \brief EIC signal: EXTINT11 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT11 0L +#define PINMUX_PC19A_EIC_EXTINT11 ((PIN_PC19A_EIC_EXTINT11 << 16) | MUX_PC19A_EIC_EXTINT11) +#define PORT_PC19A_EIC_EXTINT11 (1ul << 19) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 0L +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PC20A_EIC_EXTINT12 84L /**< \brief EIC signal: EXTINT12 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT12 0L +#define PINMUX_PC20A_EIC_EXTINT12 ((PIN_PC20A_EIC_EXTINT12 << 16) | MUX_PC20A_EIC_EXTINT12) +#define PORT_PC20A_EIC_EXTINT12 (1ul << 20) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 0L +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PC05A_EIC_EXTINT13 69L /**< \brief EIC signal: EXTINT13 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT13 0L +#define PINMUX_PC05A_EIC_EXTINT13 ((PIN_PC05A_EIC_EXTINT13 << 16) | MUX_PC05A_EIC_EXTINT13) +#define PORT_PC05A_EIC_EXTINT13 (1ul << 5) +#define PIN_PC21A_EIC_EXTINT13 85L /**< \brief EIC signal: EXTINT13 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT13 0L +#define PINMUX_PC21A_EIC_EXTINT13 ((PIN_PC21A_EIC_EXTINT13 << 16) | MUX_PC21A_EIC_EXTINT13) +#define PORT_PC21A_EIC_EXTINT13 (1ul << 21) +#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 0L +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 0L +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) +#define PIN_PC06A_EIC_EXTINT14 70L /**< \brief EIC signal: EXTINT14 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT14 0L +#define PINMUX_PC06A_EIC_EXTINT14 ((PIN_PC06A_EIC_EXTINT14 << 16) | MUX_PC06A_EIC_EXTINT14) +#define PORT_PC06A_EIC_EXTINT14 (1ul << 6) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 0L +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 0L +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) +#define PIN_PC07A_EIC_EXTINT15 71L /**< \brief EIC signal: EXTINT15 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT15 0L +#define PINMUX_PC07A_EIC_EXTINT15 ((PIN_PC07A_EIC_EXTINT15 << 16) | MUX_PC07A_EIC_EXTINT15) +#define PORT_PC07A_EIC_EXTINT15 (1ul << 7) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +#define PIN_PB22G_USB_SOF_1KHZ 54L /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ 6L +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (1ul << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA20C_SERCOM0_PAD0 20L /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 2L +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (1ul << 20) +#define PIN_PB24C_SERCOM0_PAD0 56L /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 2L +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (1ul << 24) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA21C_SERCOM0_PAD1 21L /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 2L +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (1ul << 21) +#define PIN_PB25C_SERCOM0_PAD1 57L /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 2L +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (1ul << 25) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA22C_SERCOM0_PAD2 22L /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 2L +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PC24C_SERCOM0_PAD2 88L /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 2L +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (1ul << 24) +#define PIN_PB22C_SERCOM0_PAD2 54L /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 2L +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +#define PIN_PA23C_SERCOM0_PAD3 23L /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 2L +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (1ul << 23) +#define PIN_PC25C_SERCOM0_PAD3 89L /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 2L +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (1ul << 25) +#define PIN_PB23C_SERCOM0_PAD3 55L /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 2L +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (1ul << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 62L /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 2L +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (1ul << 30) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PC27D_SERCOM1_PAD0 91L /**< \brief SERCOM1 signal: PAD0 on PC27 mux D */ +#define MUX_PC27D_SERCOM1_PAD0 3L +#define PINMUX_PC27D_SERCOM1_PAD0 ((PIN_PC27D_SERCOM1_PAD0 << 16) | MUX_PC27D_SERCOM1_PAD0) +#define PORT_PC27D_SERCOM1_PAD0 (1ul << 27) +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PC12C_SERCOM1_PAD0 76L /**< \brief SERCOM1 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM1_PAD0 2L +#define PINMUX_PC12C_SERCOM1_PAD0 ((PIN_PC12C_SERCOM1_PAD0 << 16) | MUX_PC12C_SERCOM1_PAD0) +#define PORT_PC12C_SERCOM1_PAD0 (1ul << 12) +#define PIN_PB31C_SERCOM1_PAD1 63L /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 2L +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (1ul << 31) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PC28D_SERCOM1_PAD1 92L /**< \brief SERCOM1 signal: PAD1 on PC28 mux D */ +#define MUX_PC28D_SERCOM1_PAD1 3L +#define PINMUX_PC28D_SERCOM1_PAD1 ((PIN_PC28D_SERCOM1_PAD1 << 16) | MUX_PC28D_SERCOM1_PAD1) +#define PORT_PC28D_SERCOM1_PAD1 (1ul << 28) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PC13C_SERCOM1_PAD1 77L /**< \brief SERCOM1 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM1_PAD1 2L +#define PINMUX_PC13C_SERCOM1_PAD1 ((PIN_PC13C_SERCOM1_PAD1 << 16) | MUX_PC13C_SERCOM1_PAD1) +#define PORT_PC13C_SERCOM1_PAD1 (1ul << 13) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PC10C_SERCOM1_PAD2 74L /**< \brief SERCOM1 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM1_PAD2 2L +#define PINMUX_PC10C_SERCOM1_PAD2 ((PIN_PC10C_SERCOM1_PAD2 << 16) | MUX_PC10C_SERCOM1_PAD2) +#define PORT_PC10C_SERCOM1_PAD2 (1ul << 10) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +#define PIN_PC11C_SERCOM1_PAD3 75L /**< \brief SERCOM1 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM1_PAD3 2L +#define PINMUX_PC11C_SERCOM1_PAD3 ((PIN_PC11C_SERCOM1_PAD3 << 16) | MUX_PC11C_SERCOM1_PAD3) +#define PORT_PC11C_SERCOM1_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 3L +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22) +#define PIN_PA16D_SERCOM2_PAD0 16L /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 3L +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 3L +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23) +#define PIN_PA17D_SERCOM2_PAD1 17L /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 3L +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (1ul << 17) +#define PIN_PA18D_SERCOM2_PAD2 18L /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 3L +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM2_PAD2 20L /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 3L +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 2L +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM2_PAD3 19L /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 3L +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM2_PAD3 21L /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 3L +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 2L +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 44L /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 2L +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (1ul << 12) +#define PIN_PA12D_SERCOM3_PAD0 12L /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 3L +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM3_PAD0 40L /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 3L +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (1ul << 8) +#define PIN_PB02C_SERCOM3_PAD0 34L /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 2L +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (1ul << 2) +#define PIN_PB20C_SERCOM3_PAD0 52L /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 2L +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (1ul << 20) +#define PIN_PB13C_SERCOM3_PAD1 45L /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 2L +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (1ul << 13) +#define PIN_PA13D_SERCOM3_PAD1 13L /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 3L +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM3_PAD1 41L /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 3L +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (1ul << 9) +#define PIN_PB03C_SERCOM3_PAD1 35L /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 2L +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (1ul << 3) +#define PIN_PB21C_SERCOM3_PAD1 53L /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 2L +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (1ul << 21) +#define PIN_PB14C_SERCOM3_PAD2 46L /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 2L +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (1ul << 14) +#define PIN_PA14D_SERCOM3_PAD2 14L /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 3L +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (1ul << 14) +#define PIN_PB18D_SERCOM3_PAD2 50L /**< \brief SERCOM3 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM3_PAD2 3L +#define PINMUX_PB18D_SERCOM3_PAD2 ((PIN_PB18D_SERCOM3_PAD2 << 16) | MUX_PB18D_SERCOM3_PAD2) +#define PORT_PB18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PB00C_SERCOM3_PAD2 32L /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 2L +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (1ul << 0) +#define PIN_PB15C_SERCOM3_PAD3 47L /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 2L +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (1ul << 15) +#define PIN_PA15D_SERCOM3_PAD3 15L /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 3L +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM3_PAD3 43L /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 3L +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (1ul << 11) +#define PIN_PB19D_SERCOM3_PAD3 51L /**< \brief SERCOM3 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM3_PAD3 3L +#define PINMUX_PB19D_SERCOM3_PAD3 ((PIN_PB19D_SERCOM3_PAD3 << 16) | MUX_PB19D_SERCOM3_PAD3) +#define PORT_PB19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PB01C_SERCOM3_PAD3 33L /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 2L +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (1ul << 1) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA08D_SERCOM4_PAD0 8L /**< \brief SERCOM4 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM4_PAD0 3L +#define PINMUX_PA08D_SERCOM4_PAD0 ((PIN_PA08D_SERCOM4_PAD0 << 16) | MUX_PA08D_SERCOM4_PAD0) +#define PORT_PA08D_SERCOM4_PAD0 (1ul << 8) +#define PIN_PB24D_SERCOM4_PAD0 56L /**< \brief SERCOM4 signal: PAD0 on PB24 mux D */ +#define MUX_PB24D_SERCOM4_PAD0 3L +#define PINMUX_PB24D_SERCOM4_PAD0 ((PIN_PB24D_SERCOM4_PAD0 << 16) | MUX_PB24D_SERCOM4_PAD0) +#define PORT_PB24D_SERCOM4_PAD0 (1ul << 24) +#define PIN_PA12C_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM4_PAD0 2L +#define PINMUX_PA12C_SERCOM4_PAD0 ((PIN_PA12C_SERCOM4_PAD0 << 16) | MUX_PA12C_SERCOM4_PAD0) +#define PORT_PA12C_SERCOM4_PAD0 (1ul << 12) +#define PIN_PA09D_SERCOM4_PAD1 9L /**< \brief SERCOM4 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM4_PAD1 3L +#define PINMUX_PA09D_SERCOM4_PAD1 ((PIN_PA09D_SERCOM4_PAD1 << 16) | MUX_PA09D_SERCOM4_PAD1) +#define PORT_PA09D_SERCOM4_PAD1 (1ul << 9) +#define PIN_PB25D_SERCOM4_PAD1 57L /**< \brief SERCOM4 signal: PAD1 on PB25 mux D */ +#define MUX_PB25D_SERCOM4_PAD1 3L +#define PINMUX_PB25D_SERCOM4_PAD1 ((PIN_PB25D_SERCOM4_PAD1 << 16) | MUX_PB25D_SERCOM4_PAD1) +#define PORT_PB25D_SERCOM4_PAD1 (1ul << 25) +#define PIN_PA13C_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM4_PAD1 2L +#define PINMUX_PA13C_SERCOM4_PAD1 ((PIN_PA13C_SERCOM4_PAD1 << 16) | MUX_PA13C_SERCOM4_PAD1) +#define PORT_PA13C_SERCOM4_PAD1 (1ul << 13) +#define PIN_PA10D_SERCOM4_PAD2 10L /**< \brief SERCOM4 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM4_PAD2 3L +#define PINMUX_PA10D_SERCOM4_PAD2 ((PIN_PA10D_SERCOM4_PAD2 << 16) | MUX_PA10D_SERCOM4_PAD2) +#define PORT_PA10D_SERCOM4_PAD2 (1ul << 10) +#define PIN_PC24D_SERCOM4_PAD2 88L /**< \brief SERCOM4 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM4_PAD2 3L +#define PINMUX_PC24D_SERCOM4_PAD2 ((PIN_PC24D_SERCOM4_PAD2 << 16) | MUX_PC24D_SERCOM4_PAD2) +#define PORT_PC24D_SERCOM4_PAD2 (1ul << 24) +#define PIN_PA14C_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM4_PAD2 2L +#define PINMUX_PA14C_SERCOM4_PAD2 ((PIN_PA14C_SERCOM4_PAD2 << 16) | MUX_PA14C_SERCOM4_PAD2) +#define PORT_PA14C_SERCOM4_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM4_PAD3 11L /**< \brief SERCOM4 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM4_PAD3 3L +#define PINMUX_PA11D_SERCOM4_PAD3 ((PIN_PA11D_SERCOM4_PAD3 << 16) | MUX_PA11D_SERCOM4_PAD3) +#define PORT_PA11D_SERCOM4_PAD3 (1ul << 11) +#define PIN_PC25D_SERCOM4_PAD3 89L /**< \brief SERCOM4 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM4_PAD3 3L +#define PINMUX_PC25D_SERCOM4_PAD3 ((PIN_PC25D_SERCOM4_PAD3 << 16) | MUX_PC25D_SERCOM4_PAD3) +#define PORT_PC25D_SERCOM4_PAD3 (1ul << 25) +#define PIN_PA15C_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM4_PAD3 2L +#define PINMUX_PA15C_SERCOM4_PAD3 ((PIN_PA15C_SERCOM4_PAD3 << 16) | MUX_PA15C_SERCOM4_PAD3) +#define PORT_PA15C_SERCOM4_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD0 3L +#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) +#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) +#define PIN_PA24D_SERCOM5_PAD0 24L /**< \brief SERCOM5 signal: PAD0 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD0 3L +#define PINMUX_PA24D_SERCOM5_PAD0 ((PIN_PA24D_SERCOM5_PAD0 << 16) | MUX_PA24D_SERCOM5_PAD0) +#define PORT_PA24D_SERCOM5_PAD0 (1ul << 24) +#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 3L +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) +#define PIN_PB20D_SERCOM5_PAD0 52L /**< \brief SERCOM5 signal: PAD0 on PB20 mux D */ +#define MUX_PB20D_SERCOM5_PAD0 3L +#define PINMUX_PB20D_SERCOM5_PAD0 ((PIN_PB20D_SERCOM5_PAD0 << 16) | MUX_PB20D_SERCOM5_PAD0) +#define PORT_PB20D_SERCOM5_PAD0 (1ul << 20) +#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 2L +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) +#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD1 3L +#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) +#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) +#define PIN_PA25D_SERCOM5_PAD1 25L /**< \brief SERCOM5 signal: PAD1 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD1 3L +#define PINMUX_PA25D_SERCOM5_PAD1 ((PIN_PA25D_SERCOM5_PAD1 << 16) | MUX_PA25D_SERCOM5_PAD1) +#define PORT_PA25D_SERCOM5_PAD1 (1ul << 25) +#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 3L +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) +#define PIN_PB21D_SERCOM5_PAD1 53L /**< \brief SERCOM5 signal: PAD1 on PB21 mux D */ +#define MUX_PB21D_SERCOM5_PAD1 3L +#define PINMUX_PB21D_SERCOM5_PAD1 ((PIN_PB21D_SERCOM5_PAD1 << 16) | MUX_PB21D_SERCOM5_PAD1) +#define PORT_PB21D_SERCOM5_PAD1 (1ul << 21) +#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 2L +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) +#define PIN_PB18C_SERCOM5_PAD2 50L /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 2L +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (1ul << 18) +#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 3L +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) +#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 3L +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) +#define PIN_PB19C_SERCOM5_PAD3 51L /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 2L +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (1ul << 19) +#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 3L +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) +#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 3L +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 24L /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 5L +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (1ul << 24) +#define PIN_PB18F_TCC0_WO0 50L /**< \brief TCC0 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC0_WO0 5L +#define PINMUX_PB18F_TCC0_WO0 ((PIN_PB18F_TCC0_WO0 << 16) | MUX_PB18F_TCC0_WO0) +#define PORT_PB18F_TCC0_WO0 (1ul << 18) +#define PIN_PC24F_TCC0_WO0 88L /**< \brief TCC0 signal: WO0 on PC24 mux F */ +#define MUX_PC24F_TCC0_WO0 5L +#define PINMUX_PC24F_TCC0_WO0 ((PIN_PC24F_TCC0_WO0 << 16) | MUX_PC24F_TCC0_WO0) +#define PORT_PC24F_TCC0_WO0 (1ul << 24) +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 4L +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (1ul << 30) +#define PIN_PA25F_TCC0_WO1 25L /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 5L +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (1ul << 25) +#define PIN_PB19F_TCC0_WO1 51L /**< \brief TCC0 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC0_WO1 5L +#define PINMUX_PB19F_TCC0_WO1 ((PIN_PB19F_TCC0_WO1 << 16) | MUX_PB19F_TCC0_WO1) +#define PORT_PB19F_TCC0_WO1 (1ul << 19) +#define PIN_PC25F_TCC0_WO1 89L /**< \brief TCC0 signal: WO1 on PC25 mux F */ +#define MUX_PC25F_TCC0_WO1 5L +#define PINMUX_PC25F_TCC0_WO1 ((PIN_PC25F_TCC0_WO1 << 16) | MUX_PC25F_TCC0_WO1) +#define PORT_PC25F_TCC0_WO1 (1ul << 25) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 4L +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (1ul << 31) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PB20F_TCC0_WO2 52L /**< \brief TCC0 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC0_WO2 5L +#define PINMUX_PB20F_TCC0_WO2 ((PIN_PB20F_TCC0_WO2 << 16) | MUX_PB20F_TCC0_WO2) +#define PORT_PB20F_TCC0_WO2 (1ul << 20) +#define PIN_PB22F_TCC0_WO2 54L /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 5L +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (1ul << 22) +#define PIN_PC26F_TCC0_WO2 90L /**< \brief TCC0 signal: WO2 on PC26 mux F */ +#define MUX_PC26F_TCC0_WO2 5L +#define PINMUX_PC26F_TCC0_WO2 ((PIN_PC26F_TCC0_WO2 << 16) | MUX_PC26F_TCC0_WO2) +#define PORT_PC26F_TCC0_WO2 (1ul << 26) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PB21F_TCC0_WO3 53L /**< \brief TCC0 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC0_WO3 5L +#define PINMUX_PB21F_TCC0_WO3 ((PIN_PB21F_TCC0_WO3 << 16) | MUX_PB21F_TCC0_WO3) +#define PORT_PB21F_TCC0_WO3 (1ul << 21) +#define PIN_PB23F_TCC0_WO3 55L /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 5L +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (1ul << 23) +#define PIN_PC27F_TCC0_WO3 91L /**< \brief TCC0 signal: WO3 on PC27 mux F */ +#define MUX_PC27F_TCC0_WO3 5L +#define PINMUX_PC27F_TCC0_WO3 ((PIN_PC27F_TCC0_WO3 << 16) | MUX_PC27F_TCC0_WO3) +#define PORT_PC27F_TCC0_WO3 (1ul << 27) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 5L +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (1ul << 16) +#define PIN_PC28F_TCC0_WO4 92L /**< \brief TCC0 signal: WO4 on PC28 mux F */ +#define MUX_PC28F_TCC0_WO4 5L +#define PINMUX_PC28F_TCC0_WO4 ((PIN_PC28F_TCC0_WO4 << 16) | MUX_PC28F_TCC0_WO4) +#define PORT_PC28F_TCC0_WO4 (1ul << 28) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA27F_TCC0_WO5 27L /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 5L +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (1ul << 27) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 5L +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (1ul << 17) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 5L +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (1ul << 12) +#define PIN_PB24F_TCC0_WO6 56L /**< \brief TCC0 signal: WO6 on PB24 mux F */ +#define MUX_PB24F_TCC0_WO6 5L +#define PINMUX_PB24F_TCC0_WO6 ((PIN_PB24F_TCC0_WO6 << 16) | MUX_PB24F_TCC0_WO6) +#define PORT_PB24F_TCC0_WO6 (1ul << 24) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 5L +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (1ul << 13) +#define PIN_PB25F_TCC0_WO7 57L /**< \brief TCC0 signal: WO7 on PB25 mux F */ +#define MUX_PB25F_TCC0_WO7 5L +#define PINMUX_PB25F_TCC0_WO7 ((PIN_PB25F_TCC0_WO7 << 16) | MUX_PB25F_TCC0_WO7) +#define PORT_PB25F_TCC0_WO7 (1ul << 25) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 4L +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (1ul << 12) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 4L +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (1ul << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 4L +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (1ul << 14) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 4L +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (1ul << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 4L +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (1ul << 16) +#define PIN_PC24E_TC2_WO0 88L /**< \brief TC2 signal: WO0 on PC24 mux E */ +#define MUX_PC24E_TC2_WO0 4L +#define PINMUX_PC24E_TC2_WO0 ((PIN_PC24E_TC2_WO0 << 16) | MUX_PC24E_TC2_WO0) +#define PORT_PC24E_TC2_WO0 (1ul << 24) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 4L +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (1ul << 17) +#define PIN_PC25E_TC2_WO1 89L /**< \brief TC2 signal: WO1 on PC25 mux E */ +#define MUX_PC25E_TC2_WO1 4L +#define PINMUX_PC25E_TC2_WO1 ((PIN_PC25E_TC2_WO1 << 16) | MUX_PC25E_TC2_WO1) +#define PORT_PC25E_TC2_WO1 (1ul << 25) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 4L +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (1ul << 0) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PC26E_TC3_WO0 90L /**< \brief TC3 signal: WO0 on PC26 mux E */ +#define MUX_PC26E_TC3_WO0 4L +#define PINMUX_PC26E_TC3_WO0 ((PIN_PC26E_TC3_WO0 << 16) | MUX_PC26E_TC3_WO0) +#define PORT_PC26E_TC3_WO0 (1ul << 26) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 4L +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (1ul << 1) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +#define PIN_PC27E_TC3_WO1 91L /**< \brief TC3 signal: WO1 on PC27 mux E */ +#define MUX_PC27E_TC3_WO1 4L +#define PINMUX_PC27E_TC3_WO1 ((PIN_PC27E_TC3_WO1 << 16) | MUX_PC27E_TC3_WO1) +#define PORT_PC27E_TC3_WO1 (1ul << 27) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 1L +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (1ul << 0) +#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 1L +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (1ul << 1) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 1L +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (1ul << 4) +#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 1L +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (1ul << 5) +#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 1L +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (1ul << 6) +#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 1L +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (1ul << 7) +#define PIN_PC00B_ADC_AIN16 64L /**< \brief ADC signal: AIN16 on PC00 mux B */ +#define MUX_PC00B_ADC_AIN16 1L +#define PINMUX_PC00B_ADC_AIN16 ((PIN_PC00B_ADC_AIN16 << 16) | MUX_PC00B_ADC_AIN16) +#define PORT_PC00B_ADC_AIN16 (1ul << 0) +#define PIN_PC01B_ADC_AIN17 65L /**< \brief ADC signal: AIN17 on PC01 mux B */ +#define MUX_PC01B_ADC_AIN17 1L +#define PINMUX_PC01B_ADC_AIN17 ((PIN_PC01B_ADC_AIN17 << 16) | MUX_PC01B_ADC_AIN17) +#define PORT_PC01B_ADC_AIN17 (1ul << 1) +#define PIN_PC02B_ADC_AIN18 66L /**< \brief ADC signal: AIN18 on PC02 mux B */ +#define MUX_PC02B_ADC_AIN18 1L +#define PINMUX_PC02B_ADC_AIN18 ((PIN_PC02B_ADC_AIN18 << 16) | MUX_PC02B_ADC_AIN18) +#define PORT_PC02B_ADC_AIN18 (1ul << 2) +#define PIN_PC03B_ADC_AIN19 67L /**< \brief ADC signal: AIN19 on PC03 mux B */ +#define MUX_PC03B_ADC_AIN19 1L +#define PINMUX_PC03B_ADC_AIN19 ((PIN_PC03B_ADC_AIN19 << 16) | MUX_PC03B_ADC_AIN19) +#define PORT_PC03B_ADC_AIN19 (1ul << 3) +#define PIN_PA03B_ADC_VREFA 3L /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA 1L +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (1ul << 3) +#define PIN_PA02B_ADC_VREFB 2L /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB 1L +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (1ul << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 2L /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 1L +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (1ul << 2) +#define PIN_PA03B_AC_AIN1 3L /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 1L +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (1ul << 3) +#define PIN_PB04B_AC_AIN2 36L /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 1L +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (1ul << 4) +#define PIN_PB05B_AC_AIN3 37L /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 1L +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (1ul << 5) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PB24H_AC_CMP0 56L /**< \brief AC signal: CMP0 on PB24 mux H */ +#define MUX_PB24H_AC_CMP0 7L +#define PINMUX_PB24H_AC_CMP0 ((PIN_PB24H_AC_CMP0 << 16) | MUX_PB24H_AC_CMP0) +#define PORT_PB24H_AC_CMP0 (1ul << 24) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +#define PIN_PB25H_AC_CMP1 57L /**< \brief AC signal: CMP1 on PB25 mux H */ +#define MUX_PB25H_AC_CMP1 7L +#define PINMUX_PB25H_AC_CMP1 ((PIN_PB25H_AC_CMP1 << 16) | MUX_PB25H_AC_CMP1) +#define PORT_PB25H_AC_CMP1 (1ul << 25) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 38L /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 1L +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (1ul << 6) +#define PIN_PB07B_SLCD_LP1 39L /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 1L +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (1ul << 7) +#define PIN_PB08B_SLCD_LP2 40L /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 1L +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (1ul << 8) +#define PIN_PB09B_SLCD_LP3 41L /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 1L +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (1ul << 9) +#define PIN_PA04B_SLCD_LP4 4L /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 1L +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (1ul << 4) +#define PIN_PA05B_SLCD_LP5 5L /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 1L +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (1ul << 5) +#define PIN_PA06B_SLCD_LP6 6L /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 1L +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (1ul << 6) +#define PIN_PA07B_SLCD_LP7 7L /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 1L +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (1ul << 7) +#define PIN_PC05B_SLCD_LP8 69L /**< \brief SLCD signal: LP8 on PC05 mux B */ +#define MUX_PC05B_SLCD_LP8 1L +#define PINMUX_PC05B_SLCD_LP8 ((PIN_PC05B_SLCD_LP8 << 16) | MUX_PC05B_SLCD_LP8) +#define PORT_PC05B_SLCD_LP8 (1ul << 5) +#define PIN_PC06B_SLCD_LP9 70L /**< \brief SLCD signal: LP9 on PC06 mux B */ +#define MUX_PC06B_SLCD_LP9 1L +#define PINMUX_PC06B_SLCD_LP9 ((PIN_PC06B_SLCD_LP9 << 16) | MUX_PC06B_SLCD_LP9) +#define PORT_PC06B_SLCD_LP9 (1ul << 6) +#define PIN_PC07B_SLCD_LP10 71L /**< \brief SLCD signal: LP10 on PC07 mux B */ +#define MUX_PC07B_SLCD_LP10 1L +#define PINMUX_PC07B_SLCD_LP10 ((PIN_PC07B_SLCD_LP10 << 16) | MUX_PC07B_SLCD_LP10) +#define PORT_PC07B_SLCD_LP10 (1ul << 7) +#define PIN_PA08B_SLCD_LP11 8L /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 1L +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (1ul << 8) +#define PIN_PA09B_SLCD_LP12 9L /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 1L +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (1ul << 9) +#define PIN_PA10B_SLCD_LP13 10L /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 1L +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (1ul << 10) +#define PIN_PA11B_SLCD_LP14 11L /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 1L +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (1ul << 11) +#define PIN_PC08B_SLCD_LP15 72L /**< \brief SLCD signal: LP15 on PC08 mux B */ +#define MUX_PC08B_SLCD_LP15 1L +#define PINMUX_PC08B_SLCD_LP15 ((PIN_PC08B_SLCD_LP15 << 16) | MUX_PC08B_SLCD_LP15) +#define PORT_PC08B_SLCD_LP15 (1ul << 8) +#define PIN_PC09B_SLCD_LP16 73L /**< \brief SLCD signal: LP16 on PC09 mux B */ +#define MUX_PC09B_SLCD_LP16 1L +#define PINMUX_PC09B_SLCD_LP16 ((PIN_PC09B_SLCD_LP16 << 16) | MUX_PC09B_SLCD_LP16) +#define PORT_PC09B_SLCD_LP16 (1ul << 9) +#define PIN_PC10B_SLCD_LP17 74L /**< \brief SLCD signal: LP17 on PC10 mux B */ +#define MUX_PC10B_SLCD_LP17 1L +#define PINMUX_PC10B_SLCD_LP17 ((PIN_PC10B_SLCD_LP17 << 16) | MUX_PC10B_SLCD_LP17) +#define PORT_PC10B_SLCD_LP17 (1ul << 10) +#define PIN_PC11B_SLCD_LP18 75L /**< \brief SLCD signal: LP18 on PC11 mux B */ +#define MUX_PC11B_SLCD_LP18 1L +#define PINMUX_PC11B_SLCD_LP18 ((PIN_PC11B_SLCD_LP18 << 16) | MUX_PC11B_SLCD_LP18) +#define PORT_PC11B_SLCD_LP18 (1ul << 11) +#define PIN_PC12B_SLCD_LP19 76L /**< \brief SLCD signal: LP19 on PC12 mux B */ +#define MUX_PC12B_SLCD_LP19 1L +#define PINMUX_PC12B_SLCD_LP19 ((PIN_PC12B_SLCD_LP19 << 16) | MUX_PC12B_SLCD_LP19) +#define PORT_PC12B_SLCD_LP19 (1ul << 12) +#define PIN_PC13B_SLCD_LP20 77L /**< \brief SLCD signal: LP20 on PC13 mux B */ +#define MUX_PC13B_SLCD_LP20 1L +#define PINMUX_PC13B_SLCD_LP20 ((PIN_PC13B_SLCD_LP20 << 16) | MUX_PC13B_SLCD_LP20) +#define PORT_PC13B_SLCD_LP20 (1ul << 13) +#define PIN_PB11B_SLCD_LP21 43L /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 1L +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (1ul << 11) +#define PIN_PB12B_SLCD_LP22 44L /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 1L +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (1ul << 12) +#define PIN_PB13B_SLCD_LP23 45L /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 1L +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (1ul << 13) +#define PIN_PB14B_SLCD_LP24 46L /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 1L +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (1ul << 14) +#define PIN_PB15B_SLCD_LP25 47L /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 1L +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (1ul << 15) +#define PIN_PC14B_SLCD_LP26 78L /**< \brief SLCD signal: LP26 on PC14 mux B */ +#define MUX_PC14B_SLCD_LP26 1L +#define PINMUX_PC14B_SLCD_LP26 ((PIN_PC14B_SLCD_LP26 << 16) | MUX_PC14B_SLCD_LP26) +#define PORT_PC14B_SLCD_LP26 (1ul << 14) +#define PIN_PC15B_SLCD_LP27 79L /**< \brief SLCD signal: LP27 on PC15 mux B */ +#define MUX_PC15B_SLCD_LP27 1L +#define PINMUX_PC15B_SLCD_LP27 ((PIN_PC15B_SLCD_LP27 << 16) | MUX_PC15B_SLCD_LP27) +#define PORT_PC15B_SLCD_LP27 (1ul << 15) +#define PIN_PA12B_SLCD_LP28 12L /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 1L +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (1ul << 12) +#define PIN_PA13B_SLCD_LP29 13L /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 1L +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (1ul << 13) +#define PIN_PA14B_SLCD_LP30 14L /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 1L +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (1ul << 14) +#define PIN_PA15B_SLCD_LP31 15L /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 1L +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (1ul << 15) +#define PIN_PA16B_SLCD_LP32 16L /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 1L +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (1ul << 16) +#define PIN_PA17B_SLCD_LP33 17L /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 1L +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (1ul << 17) +#define PIN_PA18B_SLCD_LP34 18L /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 1L +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (1ul << 18) +#define PIN_PA19B_SLCD_LP35 19L /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 1L +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (1ul << 19) +#define PIN_PC16B_SLCD_LP36 80L /**< \brief SLCD signal: LP36 on PC16 mux B */ +#define MUX_PC16B_SLCD_LP36 1L +#define PINMUX_PC16B_SLCD_LP36 ((PIN_PC16B_SLCD_LP36 << 16) | MUX_PC16B_SLCD_LP36) +#define PORT_PC16B_SLCD_LP36 (1ul << 16) +#define PIN_PC17B_SLCD_LP37 81L /**< \brief SLCD signal: LP37 on PC17 mux B */ +#define MUX_PC17B_SLCD_LP37 1L +#define PINMUX_PC17B_SLCD_LP37 ((PIN_PC17B_SLCD_LP37 << 16) | MUX_PC17B_SLCD_LP37) +#define PORT_PC17B_SLCD_LP37 (1ul << 17) +#define PIN_PC18B_SLCD_LP38 82L /**< \brief SLCD signal: LP38 on PC18 mux B */ +#define MUX_PC18B_SLCD_LP38 1L +#define PINMUX_PC18B_SLCD_LP38 ((PIN_PC18B_SLCD_LP38 << 16) | MUX_PC18B_SLCD_LP38) +#define PORT_PC18B_SLCD_LP38 (1ul << 18) +#define PIN_PC19B_SLCD_LP39 83L /**< \brief SLCD signal: LP39 on PC19 mux B */ +#define MUX_PC19B_SLCD_LP39 1L +#define PINMUX_PC19B_SLCD_LP39 ((PIN_PC19B_SLCD_LP39 << 16) | MUX_PC19B_SLCD_LP39) +#define PORT_PC19B_SLCD_LP39 (1ul << 19) +#define PIN_PC20B_SLCD_LP40 84L /**< \brief SLCD signal: LP40 on PC20 mux B */ +#define MUX_PC20B_SLCD_LP40 1L +#define PINMUX_PC20B_SLCD_LP40 ((PIN_PC20B_SLCD_LP40 << 16) | MUX_PC20B_SLCD_LP40) +#define PORT_PC20B_SLCD_LP40 (1ul << 20) +#define PIN_PC21B_SLCD_LP41 85L /**< \brief SLCD signal: LP41 on PC21 mux B */ +#define MUX_PC21B_SLCD_LP41 1L +#define PINMUX_PC21B_SLCD_LP41 ((PIN_PC21B_SLCD_LP41 << 16) | MUX_PC21B_SLCD_LP41) +#define PORT_PC21B_SLCD_LP41 (1ul << 21) +#define PIN_PB16B_SLCD_LP42 48L /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 1L +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (1ul << 16) +#define PIN_PB17B_SLCD_LP43 49L /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 1L +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (1ul << 17) +#define PIN_PB18B_SLCD_LP44 50L /**< \brief SLCD signal: LP44 on PB18 mux B */ +#define MUX_PB18B_SLCD_LP44 1L +#define PINMUX_PB18B_SLCD_LP44 ((PIN_PB18B_SLCD_LP44 << 16) | MUX_PB18B_SLCD_LP44) +#define PORT_PB18B_SLCD_LP44 (1ul << 18) +#define PIN_PB19B_SLCD_LP45 51L /**< \brief SLCD signal: LP45 on PB19 mux B */ +#define MUX_PB19B_SLCD_LP45 1L +#define PINMUX_PB19B_SLCD_LP45 ((PIN_PB19B_SLCD_LP45 << 16) | MUX_PB19B_SLCD_LP45) +#define PORT_PB19B_SLCD_LP45 (1ul << 19) +#define PIN_PB20B_SLCD_LP46 52L /**< \brief SLCD signal: LP46 on PB20 mux B */ +#define MUX_PB20B_SLCD_LP46 1L +#define PINMUX_PB20B_SLCD_LP46 ((PIN_PB20B_SLCD_LP46 << 16) | MUX_PB20B_SLCD_LP46) +#define PORT_PB20B_SLCD_LP46 (1ul << 20) +#define PIN_PB21B_SLCD_LP47 53L /**< \brief SLCD signal: LP47 on PB21 mux B */ +#define MUX_PB21B_SLCD_LP47 1L +#define PINMUX_PB21B_SLCD_LP47 ((PIN_PB21B_SLCD_LP47 << 16) | MUX_PB21B_SLCD_LP47) +#define PORT_PB21B_SLCD_LP47 (1ul << 21) +#define PIN_PA20B_SLCD_LP48 20L /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 1L +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (1ul << 20) +#define PIN_PA21B_SLCD_LP49 21L /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 1L +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (1ul << 21) +#define PIN_PA22B_SLCD_LP50 22L /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 1L +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (1ul << 22) +#define PIN_PA23B_SLCD_LP51 23L /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 1L +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (1ul << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 8L +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (1ul << 0) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 8L +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (1ul << 1) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PC27I_CCL_IN4 91L /**< \brief CCL signal: IN4 on PC27 mux I */ +#define MUX_PC27I_CCL_IN4 8L +#define PINMUX_PC27I_CCL_IN4 ((PIN_PC27I_CCL_IN4 << 16) | MUX_PC27I_CCL_IN4) +#define PORT_PC27I_CCL_IN4 (1ul << 27) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PC28I_CCL_IN5 92L /**< \brief CCL signal: IN5 on PC28 mux I */ +#define MUX_PC28I_CCL_IN5 8L +#define PINMUX_PC28I_CCL_IN5 ((PIN_PC28I_CCL_IN5 << 16) | MUX_PC28I_CCL_IN5) +#define PORT_PC28I_CCL_IN5 (1ul << 28) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 8L +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (1ul << 6) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 8L +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (1ul << 7) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 8L +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (1ul << 14) +#define PIN_PC20I_CCL_IN9 84L /**< \brief CCL signal: IN9 on PC20 mux I */ +#define MUX_PC20I_CCL_IN9 8L +#define PINMUX_PC20I_CCL_IN9 ((PIN_PC20I_CCL_IN9 << 16) | MUX_PC20I_CCL_IN9) +#define PORT_PC20I_CCL_IN9 (1ul << 20) +#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 8L +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (1ul << 15) +#define PIN_PC21I_CCL_IN10 85L /**< \brief CCL signal: IN10 on PC21 mux I */ +#define MUX_PC21I_CCL_IN10 8L +#define PINMUX_PC21I_CCL_IN10 ((PIN_PC21I_CCL_IN10 << 16) | MUX_PC21I_CCL_IN10) +#define PORT_PC21I_CCL_IN10 (1ul << 21) +#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 8L +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (1ul << 16) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) +#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 8L +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (1ul << 17) + +#endif /* _SAML22N16A_PIO_ */ diff --git a/Sensor Watch Starter Project/include/pio/saml22n17a.h b/Sensor Watch Starter Project/include/pio/saml22n17a.h new file mode 100755 index 00000000..430a1826 --- /dev/null +++ b/Sensor Watch Starter Project/include/pio/saml22n17a.h @@ -0,0 +1,1789 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22N17A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N17A_PIO_ +#define _SAML22N17A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (1ul << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (1ul << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (1ul << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (1ul << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (1ul << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (1ul << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (1ul << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (1ul << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (1ul << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (1ul << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (1ul << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (1ul << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (1ul << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC08 72 /**< \brief Pin Number for PC08 */ +#define PORT_PC08 (1ul << 8) /**< \brief PORT Mask for PC08 */ +#define PIN_PC09 73 /**< \brief Pin Number for PC09 */ +#define PORT_PC09 (1ul << 9) /**< \brief PORT Mask for PC09 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (1ul << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (1ul << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (1ul << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (1ul << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (1ul << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (1ul << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (1ul << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (1ul << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (1ul << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (1ul << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (1ul << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (1ul << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (1ul << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (1ul << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 7L +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (1ul << 1) +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK 7L +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (1ul << 0) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 7L +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (1ul << 14) +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 7L +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (1ul << 15) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 7L +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (1ul << 16) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 7L +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 32L /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 6L +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (1ul << 0) +#define PIN_PB02G_RTC_IN1 34L /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 6L +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (1ul << 2) +#define PIN_PA02G_RTC_IN2 2L /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 6L +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (1ul << 2) +#define PIN_PB01F_RTC_IN2 33L /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 5L +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (1ul << 1) +#define PIN_PC00G_RTC_IN3 64L /**< \brief RTC signal: IN3 on PC00 mux G */ +#define MUX_PC00G_RTC_IN3 6L +#define PINMUX_PC00G_RTC_IN3 ((PIN_PC00G_RTC_IN3 << 16) | MUX_PC00G_RTC_IN3) +#define PORT_PC00G_RTC_IN3 (1ul << 0) +#define PIN_PC01G_RTC_IN4 65L /**< \brief RTC signal: IN4 on PC01 mux G */ +#define MUX_PC01G_RTC_IN4 6L +#define PINMUX_PC01G_RTC_IN4 ((PIN_PC01G_RTC_IN4 << 16) | MUX_PC01G_RTC_IN4) +#define PORT_PC01G_RTC_IN4 (1ul << 1) +#define PIN_PB01G_RTC_OUT 33L /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT 6L +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (1ul << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 0L +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 0L +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PC08A_EIC_EXTINT0 72L /**< \brief EIC signal: EXTINT0 on PC08 mux A */ +#define MUX_PC08A_EIC_EXTINT0 0L +#define PINMUX_PC08A_EIC_EXTINT0 ((PIN_PC08A_EIC_EXTINT0 << 16) | MUX_PC08A_EIC_EXTINT0) +#define PORT_PC08A_EIC_EXTINT0 (1ul << 8) +#define PIN_PC24A_EIC_EXTINT0 88L /**< \brief EIC signal: EXTINT0 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT0 0L +#define PINMUX_PC24A_EIC_EXTINT0 ((PIN_PC24A_EIC_EXTINT0 << 16) | MUX_PC24A_EIC_EXTINT0) +#define PORT_PC24A_EIC_EXTINT0 (1ul << 24) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 0L +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 0L +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PC09A_EIC_EXTINT1 73L /**< \brief EIC signal: EXTINT1 on PC09 mux A */ +#define MUX_PC09A_EIC_EXTINT1 0L +#define PINMUX_PC09A_EIC_EXTINT1 ((PIN_PC09A_EIC_EXTINT1 << 16) | MUX_PC09A_EIC_EXTINT1) +#define PORT_PC09A_EIC_EXTINT1 (1ul << 9) +#define PIN_PC25A_EIC_EXTINT1 89L /**< \brief EIC signal: EXTINT1 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT1 0L +#define PINMUX_PC25A_EIC_EXTINT1 ((PIN_PC25A_EIC_EXTINT1 << 16) | MUX_PC25A_EIC_EXTINT1) +#define PORT_PC25A_EIC_EXTINT1 (1ul << 25) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PB18A_EIC_EXTINT2 50L /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 0L +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PC10A_EIC_EXTINT2 74L /**< \brief EIC signal: EXTINT2 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT2 0L +#define PINMUX_PC10A_EIC_EXTINT2 ((PIN_PC10A_EIC_EXTINT2 << 16) | MUX_PC10A_EIC_EXTINT2) +#define PORT_PC10A_EIC_EXTINT2 (1ul << 10) +#define PIN_PC26A_EIC_EXTINT2 90L /**< \brief EIC signal: EXTINT2 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT2 0L +#define PINMUX_PC26A_EIC_EXTINT2 ((PIN_PC26A_EIC_EXTINT2 << 16) | MUX_PC26A_EIC_EXTINT2) +#define PORT_PC26A_EIC_EXTINT2 (1ul << 26) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PB19A_EIC_EXTINT3 51L /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 0L +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PC11A_EIC_EXTINT3 75L /**< \brief EIC signal: EXTINT3 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT3 0L +#define PINMUX_PC11A_EIC_EXTINT3 ((PIN_PC11A_EIC_EXTINT3 << 16) | MUX_PC11A_EIC_EXTINT3) +#define PORT_PC11A_EIC_EXTINT3 (1ul << 11) +#define PIN_PC27A_EIC_EXTINT3 91L /**< \brief EIC signal: EXTINT3 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT3 0L +#define PINMUX_PC27A_EIC_EXTINT3 ((PIN_PC27A_EIC_EXTINT3 << 16) | MUX_PC27A_EIC_EXTINT3) +#define PORT_PC27A_EIC_EXTINT3 (1ul << 27) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 0L +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PB20A_EIC_EXTINT4 52L /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 0L +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PC12A_EIC_EXTINT4 76L /**< \brief EIC signal: EXTINT4 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT4 0L +#define PINMUX_PC12A_EIC_EXTINT4 ((PIN_PC12A_EIC_EXTINT4 << 16) | MUX_PC12A_EIC_EXTINT4) +#define PORT_PC12A_EIC_EXTINT4 (1ul << 12) +#define PIN_PC28A_EIC_EXTINT4 92L /**< \brief EIC signal: EXTINT4 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT4 0L +#define PINMUX_PC28A_EIC_EXTINT4 ((PIN_PC28A_EIC_EXTINT4 << 16) | MUX_PC28A_EIC_EXTINT4) +#define PORT_PC28A_EIC_EXTINT4 (1ul << 28) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 0L +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PB21A_EIC_EXTINT5 53L /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 0L +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PC13A_EIC_EXTINT5 77L /**< \brief EIC signal: EXTINT5 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT5 0L +#define PINMUX_PC13A_EIC_EXTINT5 ((PIN_PC13A_EIC_EXTINT5 << 16) | MUX_PC13A_EIC_EXTINT5) +#define PORT_PC13A_EIC_EXTINT5 (1ul << 13) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 0L +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PC14A_EIC_EXTINT6 78L /**< \brief EIC signal: EXTINT6 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT6 0L +#define PINMUX_PC14A_EIC_EXTINT6 ((PIN_PC14A_EIC_EXTINT6 << 16) | MUX_PC14A_EIC_EXTINT6) +#define PORT_PC14A_EIC_EXTINT6 (1ul << 14) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 0L +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PC15A_EIC_EXTINT7 79L /**< \brief EIC signal: EXTINT7 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT7 0L +#define PINMUX_PC15A_EIC_EXTINT7 ((PIN_PC15A_EIC_EXTINT7 << 16) | MUX_PC15A_EIC_EXTINT7) +#define PORT_PC15A_EIC_EXTINT7 (1ul << 15) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PB24A_EIC_EXTINT8 56L /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 0L +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (1ul << 24) +#define PIN_PC00A_EIC_EXTINT8 64L /**< \brief EIC signal: EXTINT8 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT8 0L +#define PINMUX_PC00A_EIC_EXTINT8 ((PIN_PC00A_EIC_EXTINT8 << 16) | MUX_PC00A_EIC_EXTINT8) +#define PORT_PC00A_EIC_EXTINT8 (1ul << 0) +#define PIN_PC16A_EIC_EXTINT8 80L /**< \brief EIC signal: EXTINT8 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT8 0L +#define PINMUX_PC16A_EIC_EXTINT8 ((PIN_PC16A_EIC_EXTINT8 << 16) | MUX_PC16A_EIC_EXTINT8) +#define PORT_PC16A_EIC_EXTINT8 (1ul << 16) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB25A_EIC_EXTINT9 57L /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 0L +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (1ul << 25) +#define PIN_PC01A_EIC_EXTINT9 65L /**< \brief EIC signal: EXTINT9 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT9 0L +#define PINMUX_PC01A_EIC_EXTINT9 ((PIN_PC01A_EIC_EXTINT9 << 16) | MUX_PC01A_EIC_EXTINT9) +#define PORT_PC01A_EIC_EXTINT9 (1ul << 1) +#define PIN_PC17A_EIC_EXTINT9 81L /**< \brief EIC signal: EXTINT9 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT9 0L +#define PINMUX_PC17A_EIC_EXTINT9 ((PIN_PC17A_EIC_EXTINT9 << 16) | MUX_PC17A_EIC_EXTINT9) +#define PORT_PC17A_EIC_EXTINT9 (1ul << 17) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PC02A_EIC_EXTINT10 66L /**< \brief EIC signal: EXTINT10 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT10 0L +#define PINMUX_PC02A_EIC_EXTINT10 ((PIN_PC02A_EIC_EXTINT10 << 16) | MUX_PC02A_EIC_EXTINT10) +#define PORT_PC02A_EIC_EXTINT10 (1ul << 2) +#define PIN_PC18A_EIC_EXTINT10 82L /**< \brief EIC signal: EXTINT10 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT10 0L +#define PINMUX_PC18A_EIC_EXTINT10 ((PIN_PC18A_EIC_EXTINT10 << 16) | MUX_PC18A_EIC_EXTINT10) +#define PORT_PC18A_EIC_EXTINT10 (1ul << 18) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PC03A_EIC_EXTINT11 67L /**< \brief EIC signal: EXTINT11 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT11 0L +#define PINMUX_PC03A_EIC_EXTINT11 ((PIN_PC03A_EIC_EXTINT11 << 16) | MUX_PC03A_EIC_EXTINT11) +#define PORT_PC03A_EIC_EXTINT11 (1ul << 3) +#define PIN_PC19A_EIC_EXTINT11 83L /**< \brief EIC signal: EXTINT11 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT11 0L +#define PINMUX_PC19A_EIC_EXTINT11 ((PIN_PC19A_EIC_EXTINT11 << 16) | MUX_PC19A_EIC_EXTINT11) +#define PORT_PC19A_EIC_EXTINT11 (1ul << 19) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 0L +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PC20A_EIC_EXTINT12 84L /**< \brief EIC signal: EXTINT12 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT12 0L +#define PINMUX_PC20A_EIC_EXTINT12 ((PIN_PC20A_EIC_EXTINT12 << 16) | MUX_PC20A_EIC_EXTINT12) +#define PORT_PC20A_EIC_EXTINT12 (1ul << 20) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 0L +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PC05A_EIC_EXTINT13 69L /**< \brief EIC signal: EXTINT13 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT13 0L +#define PINMUX_PC05A_EIC_EXTINT13 ((PIN_PC05A_EIC_EXTINT13 << 16) | MUX_PC05A_EIC_EXTINT13) +#define PORT_PC05A_EIC_EXTINT13 (1ul << 5) +#define PIN_PC21A_EIC_EXTINT13 85L /**< \brief EIC signal: EXTINT13 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT13 0L +#define PINMUX_PC21A_EIC_EXTINT13 ((PIN_PC21A_EIC_EXTINT13 << 16) | MUX_PC21A_EIC_EXTINT13) +#define PORT_PC21A_EIC_EXTINT13 (1ul << 21) +#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 0L +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 0L +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) +#define PIN_PC06A_EIC_EXTINT14 70L /**< \brief EIC signal: EXTINT14 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT14 0L +#define PINMUX_PC06A_EIC_EXTINT14 ((PIN_PC06A_EIC_EXTINT14 << 16) | MUX_PC06A_EIC_EXTINT14) +#define PORT_PC06A_EIC_EXTINT14 (1ul << 6) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 0L +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 0L +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) +#define PIN_PC07A_EIC_EXTINT15 71L /**< \brief EIC signal: EXTINT15 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT15 0L +#define PINMUX_PC07A_EIC_EXTINT15 ((PIN_PC07A_EIC_EXTINT15 << 16) | MUX_PC07A_EIC_EXTINT15) +#define PORT_PC07A_EIC_EXTINT15 (1ul << 7) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +#define PIN_PB22G_USB_SOF_1KHZ 54L /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ 6L +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (1ul << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA20C_SERCOM0_PAD0 20L /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 2L +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (1ul << 20) +#define PIN_PB24C_SERCOM0_PAD0 56L /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 2L +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (1ul << 24) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA21C_SERCOM0_PAD1 21L /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 2L +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (1ul << 21) +#define PIN_PB25C_SERCOM0_PAD1 57L /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 2L +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (1ul << 25) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA22C_SERCOM0_PAD2 22L /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 2L +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PC24C_SERCOM0_PAD2 88L /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 2L +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (1ul << 24) +#define PIN_PB22C_SERCOM0_PAD2 54L /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 2L +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +#define PIN_PA23C_SERCOM0_PAD3 23L /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 2L +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (1ul << 23) +#define PIN_PC25C_SERCOM0_PAD3 89L /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 2L +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (1ul << 25) +#define PIN_PB23C_SERCOM0_PAD3 55L /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 2L +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (1ul << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 62L /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 2L +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (1ul << 30) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PC27D_SERCOM1_PAD0 91L /**< \brief SERCOM1 signal: PAD0 on PC27 mux D */ +#define MUX_PC27D_SERCOM1_PAD0 3L +#define PINMUX_PC27D_SERCOM1_PAD0 ((PIN_PC27D_SERCOM1_PAD0 << 16) | MUX_PC27D_SERCOM1_PAD0) +#define PORT_PC27D_SERCOM1_PAD0 (1ul << 27) +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PC12C_SERCOM1_PAD0 76L /**< \brief SERCOM1 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM1_PAD0 2L +#define PINMUX_PC12C_SERCOM1_PAD0 ((PIN_PC12C_SERCOM1_PAD0 << 16) | MUX_PC12C_SERCOM1_PAD0) +#define PORT_PC12C_SERCOM1_PAD0 (1ul << 12) +#define PIN_PB31C_SERCOM1_PAD1 63L /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 2L +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (1ul << 31) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PC28D_SERCOM1_PAD1 92L /**< \brief SERCOM1 signal: PAD1 on PC28 mux D */ +#define MUX_PC28D_SERCOM1_PAD1 3L +#define PINMUX_PC28D_SERCOM1_PAD1 ((PIN_PC28D_SERCOM1_PAD1 << 16) | MUX_PC28D_SERCOM1_PAD1) +#define PORT_PC28D_SERCOM1_PAD1 (1ul << 28) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PC13C_SERCOM1_PAD1 77L /**< \brief SERCOM1 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM1_PAD1 2L +#define PINMUX_PC13C_SERCOM1_PAD1 ((PIN_PC13C_SERCOM1_PAD1 << 16) | MUX_PC13C_SERCOM1_PAD1) +#define PORT_PC13C_SERCOM1_PAD1 (1ul << 13) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PC10C_SERCOM1_PAD2 74L /**< \brief SERCOM1 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM1_PAD2 2L +#define PINMUX_PC10C_SERCOM1_PAD2 ((PIN_PC10C_SERCOM1_PAD2 << 16) | MUX_PC10C_SERCOM1_PAD2) +#define PORT_PC10C_SERCOM1_PAD2 (1ul << 10) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +#define PIN_PC11C_SERCOM1_PAD3 75L /**< \brief SERCOM1 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM1_PAD3 2L +#define PINMUX_PC11C_SERCOM1_PAD3 ((PIN_PC11C_SERCOM1_PAD3 << 16) | MUX_PC11C_SERCOM1_PAD3) +#define PORT_PC11C_SERCOM1_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 3L +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22) +#define PIN_PA16D_SERCOM2_PAD0 16L /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 3L +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 3L +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23) +#define PIN_PA17D_SERCOM2_PAD1 17L /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 3L +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (1ul << 17) +#define PIN_PA18D_SERCOM2_PAD2 18L /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 3L +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM2_PAD2 20L /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 3L +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 2L +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM2_PAD3 19L /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 3L +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM2_PAD3 21L /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 3L +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 2L +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 44L /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 2L +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (1ul << 12) +#define PIN_PA12D_SERCOM3_PAD0 12L /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 3L +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM3_PAD0 40L /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 3L +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (1ul << 8) +#define PIN_PB02C_SERCOM3_PAD0 34L /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 2L +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (1ul << 2) +#define PIN_PB20C_SERCOM3_PAD0 52L /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 2L +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (1ul << 20) +#define PIN_PB13C_SERCOM3_PAD1 45L /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 2L +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (1ul << 13) +#define PIN_PA13D_SERCOM3_PAD1 13L /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 3L +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM3_PAD1 41L /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 3L +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (1ul << 9) +#define PIN_PB03C_SERCOM3_PAD1 35L /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 2L +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (1ul << 3) +#define PIN_PB21C_SERCOM3_PAD1 53L /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 2L +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (1ul << 21) +#define PIN_PB14C_SERCOM3_PAD2 46L /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 2L +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (1ul << 14) +#define PIN_PA14D_SERCOM3_PAD2 14L /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 3L +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (1ul << 14) +#define PIN_PB18D_SERCOM3_PAD2 50L /**< \brief SERCOM3 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM3_PAD2 3L +#define PINMUX_PB18D_SERCOM3_PAD2 ((PIN_PB18D_SERCOM3_PAD2 << 16) | MUX_PB18D_SERCOM3_PAD2) +#define PORT_PB18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PB00C_SERCOM3_PAD2 32L /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 2L +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (1ul << 0) +#define PIN_PB15C_SERCOM3_PAD3 47L /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 2L +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (1ul << 15) +#define PIN_PA15D_SERCOM3_PAD3 15L /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 3L +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM3_PAD3 43L /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 3L +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (1ul << 11) +#define PIN_PB19D_SERCOM3_PAD3 51L /**< \brief SERCOM3 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM3_PAD3 3L +#define PINMUX_PB19D_SERCOM3_PAD3 ((PIN_PB19D_SERCOM3_PAD3 << 16) | MUX_PB19D_SERCOM3_PAD3) +#define PORT_PB19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PB01C_SERCOM3_PAD3 33L /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 2L +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (1ul << 1) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA08D_SERCOM4_PAD0 8L /**< \brief SERCOM4 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM4_PAD0 3L +#define PINMUX_PA08D_SERCOM4_PAD0 ((PIN_PA08D_SERCOM4_PAD0 << 16) | MUX_PA08D_SERCOM4_PAD0) +#define PORT_PA08D_SERCOM4_PAD0 (1ul << 8) +#define PIN_PB24D_SERCOM4_PAD0 56L /**< \brief SERCOM4 signal: PAD0 on PB24 mux D */ +#define MUX_PB24D_SERCOM4_PAD0 3L +#define PINMUX_PB24D_SERCOM4_PAD0 ((PIN_PB24D_SERCOM4_PAD0 << 16) | MUX_PB24D_SERCOM4_PAD0) +#define PORT_PB24D_SERCOM4_PAD0 (1ul << 24) +#define PIN_PA12C_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM4_PAD0 2L +#define PINMUX_PA12C_SERCOM4_PAD0 ((PIN_PA12C_SERCOM4_PAD0 << 16) | MUX_PA12C_SERCOM4_PAD0) +#define PORT_PA12C_SERCOM4_PAD0 (1ul << 12) +#define PIN_PA09D_SERCOM4_PAD1 9L /**< \brief SERCOM4 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM4_PAD1 3L +#define PINMUX_PA09D_SERCOM4_PAD1 ((PIN_PA09D_SERCOM4_PAD1 << 16) | MUX_PA09D_SERCOM4_PAD1) +#define PORT_PA09D_SERCOM4_PAD1 (1ul << 9) +#define PIN_PB25D_SERCOM4_PAD1 57L /**< \brief SERCOM4 signal: PAD1 on PB25 mux D */ +#define MUX_PB25D_SERCOM4_PAD1 3L +#define PINMUX_PB25D_SERCOM4_PAD1 ((PIN_PB25D_SERCOM4_PAD1 << 16) | MUX_PB25D_SERCOM4_PAD1) +#define PORT_PB25D_SERCOM4_PAD1 (1ul << 25) +#define PIN_PA13C_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM4_PAD1 2L +#define PINMUX_PA13C_SERCOM4_PAD1 ((PIN_PA13C_SERCOM4_PAD1 << 16) | MUX_PA13C_SERCOM4_PAD1) +#define PORT_PA13C_SERCOM4_PAD1 (1ul << 13) +#define PIN_PA10D_SERCOM4_PAD2 10L /**< \brief SERCOM4 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM4_PAD2 3L +#define PINMUX_PA10D_SERCOM4_PAD2 ((PIN_PA10D_SERCOM4_PAD2 << 16) | MUX_PA10D_SERCOM4_PAD2) +#define PORT_PA10D_SERCOM4_PAD2 (1ul << 10) +#define PIN_PC24D_SERCOM4_PAD2 88L /**< \brief SERCOM4 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM4_PAD2 3L +#define PINMUX_PC24D_SERCOM4_PAD2 ((PIN_PC24D_SERCOM4_PAD2 << 16) | MUX_PC24D_SERCOM4_PAD2) +#define PORT_PC24D_SERCOM4_PAD2 (1ul << 24) +#define PIN_PA14C_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM4_PAD2 2L +#define PINMUX_PA14C_SERCOM4_PAD2 ((PIN_PA14C_SERCOM4_PAD2 << 16) | MUX_PA14C_SERCOM4_PAD2) +#define PORT_PA14C_SERCOM4_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM4_PAD3 11L /**< \brief SERCOM4 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM4_PAD3 3L +#define PINMUX_PA11D_SERCOM4_PAD3 ((PIN_PA11D_SERCOM4_PAD3 << 16) | MUX_PA11D_SERCOM4_PAD3) +#define PORT_PA11D_SERCOM4_PAD3 (1ul << 11) +#define PIN_PC25D_SERCOM4_PAD3 89L /**< \brief SERCOM4 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM4_PAD3 3L +#define PINMUX_PC25D_SERCOM4_PAD3 ((PIN_PC25D_SERCOM4_PAD3 << 16) | MUX_PC25D_SERCOM4_PAD3) +#define PORT_PC25D_SERCOM4_PAD3 (1ul << 25) +#define PIN_PA15C_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM4_PAD3 2L +#define PINMUX_PA15C_SERCOM4_PAD3 ((PIN_PA15C_SERCOM4_PAD3 << 16) | MUX_PA15C_SERCOM4_PAD3) +#define PORT_PA15C_SERCOM4_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD0 3L +#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) +#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) +#define PIN_PA24D_SERCOM5_PAD0 24L /**< \brief SERCOM5 signal: PAD0 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD0 3L +#define PINMUX_PA24D_SERCOM5_PAD0 ((PIN_PA24D_SERCOM5_PAD0 << 16) | MUX_PA24D_SERCOM5_PAD0) +#define PORT_PA24D_SERCOM5_PAD0 (1ul << 24) +#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 3L +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) +#define PIN_PB20D_SERCOM5_PAD0 52L /**< \brief SERCOM5 signal: PAD0 on PB20 mux D */ +#define MUX_PB20D_SERCOM5_PAD0 3L +#define PINMUX_PB20D_SERCOM5_PAD0 ((PIN_PB20D_SERCOM5_PAD0 << 16) | MUX_PB20D_SERCOM5_PAD0) +#define PORT_PB20D_SERCOM5_PAD0 (1ul << 20) +#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 2L +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) +#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD1 3L +#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) +#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) +#define PIN_PA25D_SERCOM5_PAD1 25L /**< \brief SERCOM5 signal: PAD1 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD1 3L +#define PINMUX_PA25D_SERCOM5_PAD1 ((PIN_PA25D_SERCOM5_PAD1 << 16) | MUX_PA25D_SERCOM5_PAD1) +#define PORT_PA25D_SERCOM5_PAD1 (1ul << 25) +#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 3L +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) +#define PIN_PB21D_SERCOM5_PAD1 53L /**< \brief SERCOM5 signal: PAD1 on PB21 mux D */ +#define MUX_PB21D_SERCOM5_PAD1 3L +#define PINMUX_PB21D_SERCOM5_PAD1 ((PIN_PB21D_SERCOM5_PAD1 << 16) | MUX_PB21D_SERCOM5_PAD1) +#define PORT_PB21D_SERCOM5_PAD1 (1ul << 21) +#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 2L +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) +#define PIN_PB18C_SERCOM5_PAD2 50L /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 2L +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (1ul << 18) +#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 3L +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) +#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 3L +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) +#define PIN_PB19C_SERCOM5_PAD3 51L /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 2L +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (1ul << 19) +#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 3L +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) +#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 3L +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 24L /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 5L +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (1ul << 24) +#define PIN_PB18F_TCC0_WO0 50L /**< \brief TCC0 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC0_WO0 5L +#define PINMUX_PB18F_TCC0_WO0 ((PIN_PB18F_TCC0_WO0 << 16) | MUX_PB18F_TCC0_WO0) +#define PORT_PB18F_TCC0_WO0 (1ul << 18) +#define PIN_PC24F_TCC0_WO0 88L /**< \brief TCC0 signal: WO0 on PC24 mux F */ +#define MUX_PC24F_TCC0_WO0 5L +#define PINMUX_PC24F_TCC0_WO0 ((PIN_PC24F_TCC0_WO0 << 16) | MUX_PC24F_TCC0_WO0) +#define PORT_PC24F_TCC0_WO0 (1ul << 24) +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 4L +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (1ul << 30) +#define PIN_PA25F_TCC0_WO1 25L /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 5L +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (1ul << 25) +#define PIN_PB19F_TCC0_WO1 51L /**< \brief TCC0 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC0_WO1 5L +#define PINMUX_PB19F_TCC0_WO1 ((PIN_PB19F_TCC0_WO1 << 16) | MUX_PB19F_TCC0_WO1) +#define PORT_PB19F_TCC0_WO1 (1ul << 19) +#define PIN_PC25F_TCC0_WO1 89L /**< \brief TCC0 signal: WO1 on PC25 mux F */ +#define MUX_PC25F_TCC0_WO1 5L +#define PINMUX_PC25F_TCC0_WO1 ((PIN_PC25F_TCC0_WO1 << 16) | MUX_PC25F_TCC0_WO1) +#define PORT_PC25F_TCC0_WO1 (1ul << 25) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 4L +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (1ul << 31) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PB20F_TCC0_WO2 52L /**< \brief TCC0 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC0_WO2 5L +#define PINMUX_PB20F_TCC0_WO2 ((PIN_PB20F_TCC0_WO2 << 16) | MUX_PB20F_TCC0_WO2) +#define PORT_PB20F_TCC0_WO2 (1ul << 20) +#define PIN_PB22F_TCC0_WO2 54L /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 5L +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (1ul << 22) +#define PIN_PC26F_TCC0_WO2 90L /**< \brief TCC0 signal: WO2 on PC26 mux F */ +#define MUX_PC26F_TCC0_WO2 5L +#define PINMUX_PC26F_TCC0_WO2 ((PIN_PC26F_TCC0_WO2 << 16) | MUX_PC26F_TCC0_WO2) +#define PORT_PC26F_TCC0_WO2 (1ul << 26) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PB21F_TCC0_WO3 53L /**< \brief TCC0 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC0_WO3 5L +#define PINMUX_PB21F_TCC0_WO3 ((PIN_PB21F_TCC0_WO3 << 16) | MUX_PB21F_TCC0_WO3) +#define PORT_PB21F_TCC0_WO3 (1ul << 21) +#define PIN_PB23F_TCC0_WO3 55L /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 5L +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (1ul << 23) +#define PIN_PC27F_TCC0_WO3 91L /**< \brief TCC0 signal: WO3 on PC27 mux F */ +#define MUX_PC27F_TCC0_WO3 5L +#define PINMUX_PC27F_TCC0_WO3 ((PIN_PC27F_TCC0_WO3 << 16) | MUX_PC27F_TCC0_WO3) +#define PORT_PC27F_TCC0_WO3 (1ul << 27) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 5L +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (1ul << 16) +#define PIN_PC28F_TCC0_WO4 92L /**< \brief TCC0 signal: WO4 on PC28 mux F */ +#define MUX_PC28F_TCC0_WO4 5L +#define PINMUX_PC28F_TCC0_WO4 ((PIN_PC28F_TCC0_WO4 << 16) | MUX_PC28F_TCC0_WO4) +#define PORT_PC28F_TCC0_WO4 (1ul << 28) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA27F_TCC0_WO5 27L /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 5L +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (1ul << 27) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 5L +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (1ul << 17) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 5L +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (1ul << 12) +#define PIN_PB24F_TCC0_WO6 56L /**< \brief TCC0 signal: WO6 on PB24 mux F */ +#define MUX_PB24F_TCC0_WO6 5L +#define PINMUX_PB24F_TCC0_WO6 ((PIN_PB24F_TCC0_WO6 << 16) | MUX_PB24F_TCC0_WO6) +#define PORT_PB24F_TCC0_WO6 (1ul << 24) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 5L +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (1ul << 13) +#define PIN_PB25F_TCC0_WO7 57L /**< \brief TCC0 signal: WO7 on PB25 mux F */ +#define MUX_PB25F_TCC0_WO7 5L +#define PINMUX_PB25F_TCC0_WO7 ((PIN_PB25F_TCC0_WO7 << 16) | MUX_PB25F_TCC0_WO7) +#define PORT_PB25F_TCC0_WO7 (1ul << 25) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 4L +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (1ul << 12) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 4L +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (1ul << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 4L +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (1ul << 14) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 4L +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (1ul << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 4L +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (1ul << 16) +#define PIN_PC24E_TC2_WO0 88L /**< \brief TC2 signal: WO0 on PC24 mux E */ +#define MUX_PC24E_TC2_WO0 4L +#define PINMUX_PC24E_TC2_WO0 ((PIN_PC24E_TC2_WO0 << 16) | MUX_PC24E_TC2_WO0) +#define PORT_PC24E_TC2_WO0 (1ul << 24) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 4L +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (1ul << 17) +#define PIN_PC25E_TC2_WO1 89L /**< \brief TC2 signal: WO1 on PC25 mux E */ +#define MUX_PC25E_TC2_WO1 4L +#define PINMUX_PC25E_TC2_WO1 ((PIN_PC25E_TC2_WO1 << 16) | MUX_PC25E_TC2_WO1) +#define PORT_PC25E_TC2_WO1 (1ul << 25) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 4L +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (1ul << 0) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PC26E_TC3_WO0 90L /**< \brief TC3 signal: WO0 on PC26 mux E */ +#define MUX_PC26E_TC3_WO0 4L +#define PINMUX_PC26E_TC3_WO0 ((PIN_PC26E_TC3_WO0 << 16) | MUX_PC26E_TC3_WO0) +#define PORT_PC26E_TC3_WO0 (1ul << 26) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 4L +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (1ul << 1) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +#define PIN_PC27E_TC3_WO1 91L /**< \brief TC3 signal: WO1 on PC27 mux E */ +#define MUX_PC27E_TC3_WO1 4L +#define PINMUX_PC27E_TC3_WO1 ((PIN_PC27E_TC3_WO1 << 16) | MUX_PC27E_TC3_WO1) +#define PORT_PC27E_TC3_WO1 (1ul << 27) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 1L +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (1ul << 0) +#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 1L +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (1ul << 1) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 1L +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (1ul << 4) +#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 1L +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (1ul << 5) +#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 1L +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (1ul << 6) +#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 1L +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (1ul << 7) +#define PIN_PC00B_ADC_AIN16 64L /**< \brief ADC signal: AIN16 on PC00 mux B */ +#define MUX_PC00B_ADC_AIN16 1L +#define PINMUX_PC00B_ADC_AIN16 ((PIN_PC00B_ADC_AIN16 << 16) | MUX_PC00B_ADC_AIN16) +#define PORT_PC00B_ADC_AIN16 (1ul << 0) +#define PIN_PC01B_ADC_AIN17 65L /**< \brief ADC signal: AIN17 on PC01 mux B */ +#define MUX_PC01B_ADC_AIN17 1L +#define PINMUX_PC01B_ADC_AIN17 ((PIN_PC01B_ADC_AIN17 << 16) | MUX_PC01B_ADC_AIN17) +#define PORT_PC01B_ADC_AIN17 (1ul << 1) +#define PIN_PC02B_ADC_AIN18 66L /**< \brief ADC signal: AIN18 on PC02 mux B */ +#define MUX_PC02B_ADC_AIN18 1L +#define PINMUX_PC02B_ADC_AIN18 ((PIN_PC02B_ADC_AIN18 << 16) | MUX_PC02B_ADC_AIN18) +#define PORT_PC02B_ADC_AIN18 (1ul << 2) +#define PIN_PC03B_ADC_AIN19 67L /**< \brief ADC signal: AIN19 on PC03 mux B */ +#define MUX_PC03B_ADC_AIN19 1L +#define PINMUX_PC03B_ADC_AIN19 ((PIN_PC03B_ADC_AIN19 << 16) | MUX_PC03B_ADC_AIN19) +#define PORT_PC03B_ADC_AIN19 (1ul << 3) +#define PIN_PA03B_ADC_VREFA 3L /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA 1L +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (1ul << 3) +#define PIN_PA02B_ADC_VREFB 2L /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB 1L +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (1ul << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 2L /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 1L +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (1ul << 2) +#define PIN_PA03B_AC_AIN1 3L /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 1L +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (1ul << 3) +#define PIN_PB04B_AC_AIN2 36L /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 1L +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (1ul << 4) +#define PIN_PB05B_AC_AIN3 37L /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 1L +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (1ul << 5) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PB24H_AC_CMP0 56L /**< \brief AC signal: CMP0 on PB24 mux H */ +#define MUX_PB24H_AC_CMP0 7L +#define PINMUX_PB24H_AC_CMP0 ((PIN_PB24H_AC_CMP0 << 16) | MUX_PB24H_AC_CMP0) +#define PORT_PB24H_AC_CMP0 (1ul << 24) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +#define PIN_PB25H_AC_CMP1 57L /**< \brief AC signal: CMP1 on PB25 mux H */ +#define MUX_PB25H_AC_CMP1 7L +#define PINMUX_PB25H_AC_CMP1 ((PIN_PB25H_AC_CMP1 << 16) | MUX_PB25H_AC_CMP1) +#define PORT_PB25H_AC_CMP1 (1ul << 25) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 38L /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 1L +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (1ul << 6) +#define PIN_PB07B_SLCD_LP1 39L /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 1L +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (1ul << 7) +#define PIN_PB08B_SLCD_LP2 40L /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 1L +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (1ul << 8) +#define PIN_PB09B_SLCD_LP3 41L /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 1L +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (1ul << 9) +#define PIN_PA04B_SLCD_LP4 4L /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 1L +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (1ul << 4) +#define PIN_PA05B_SLCD_LP5 5L /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 1L +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (1ul << 5) +#define PIN_PA06B_SLCD_LP6 6L /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 1L +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (1ul << 6) +#define PIN_PA07B_SLCD_LP7 7L /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 1L +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (1ul << 7) +#define PIN_PC05B_SLCD_LP8 69L /**< \brief SLCD signal: LP8 on PC05 mux B */ +#define MUX_PC05B_SLCD_LP8 1L +#define PINMUX_PC05B_SLCD_LP8 ((PIN_PC05B_SLCD_LP8 << 16) | MUX_PC05B_SLCD_LP8) +#define PORT_PC05B_SLCD_LP8 (1ul << 5) +#define PIN_PC06B_SLCD_LP9 70L /**< \brief SLCD signal: LP9 on PC06 mux B */ +#define MUX_PC06B_SLCD_LP9 1L +#define PINMUX_PC06B_SLCD_LP9 ((PIN_PC06B_SLCD_LP9 << 16) | MUX_PC06B_SLCD_LP9) +#define PORT_PC06B_SLCD_LP9 (1ul << 6) +#define PIN_PC07B_SLCD_LP10 71L /**< \brief SLCD signal: LP10 on PC07 mux B */ +#define MUX_PC07B_SLCD_LP10 1L +#define PINMUX_PC07B_SLCD_LP10 ((PIN_PC07B_SLCD_LP10 << 16) | MUX_PC07B_SLCD_LP10) +#define PORT_PC07B_SLCD_LP10 (1ul << 7) +#define PIN_PA08B_SLCD_LP11 8L /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 1L +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (1ul << 8) +#define PIN_PA09B_SLCD_LP12 9L /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 1L +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (1ul << 9) +#define PIN_PA10B_SLCD_LP13 10L /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 1L +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (1ul << 10) +#define PIN_PA11B_SLCD_LP14 11L /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 1L +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (1ul << 11) +#define PIN_PC08B_SLCD_LP15 72L /**< \brief SLCD signal: LP15 on PC08 mux B */ +#define MUX_PC08B_SLCD_LP15 1L +#define PINMUX_PC08B_SLCD_LP15 ((PIN_PC08B_SLCD_LP15 << 16) | MUX_PC08B_SLCD_LP15) +#define PORT_PC08B_SLCD_LP15 (1ul << 8) +#define PIN_PC09B_SLCD_LP16 73L /**< \brief SLCD signal: LP16 on PC09 mux B */ +#define MUX_PC09B_SLCD_LP16 1L +#define PINMUX_PC09B_SLCD_LP16 ((PIN_PC09B_SLCD_LP16 << 16) | MUX_PC09B_SLCD_LP16) +#define PORT_PC09B_SLCD_LP16 (1ul << 9) +#define PIN_PC10B_SLCD_LP17 74L /**< \brief SLCD signal: LP17 on PC10 mux B */ +#define MUX_PC10B_SLCD_LP17 1L +#define PINMUX_PC10B_SLCD_LP17 ((PIN_PC10B_SLCD_LP17 << 16) | MUX_PC10B_SLCD_LP17) +#define PORT_PC10B_SLCD_LP17 (1ul << 10) +#define PIN_PC11B_SLCD_LP18 75L /**< \brief SLCD signal: LP18 on PC11 mux B */ +#define MUX_PC11B_SLCD_LP18 1L +#define PINMUX_PC11B_SLCD_LP18 ((PIN_PC11B_SLCD_LP18 << 16) | MUX_PC11B_SLCD_LP18) +#define PORT_PC11B_SLCD_LP18 (1ul << 11) +#define PIN_PC12B_SLCD_LP19 76L /**< \brief SLCD signal: LP19 on PC12 mux B */ +#define MUX_PC12B_SLCD_LP19 1L +#define PINMUX_PC12B_SLCD_LP19 ((PIN_PC12B_SLCD_LP19 << 16) | MUX_PC12B_SLCD_LP19) +#define PORT_PC12B_SLCD_LP19 (1ul << 12) +#define PIN_PC13B_SLCD_LP20 77L /**< \brief SLCD signal: LP20 on PC13 mux B */ +#define MUX_PC13B_SLCD_LP20 1L +#define PINMUX_PC13B_SLCD_LP20 ((PIN_PC13B_SLCD_LP20 << 16) | MUX_PC13B_SLCD_LP20) +#define PORT_PC13B_SLCD_LP20 (1ul << 13) +#define PIN_PB11B_SLCD_LP21 43L /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 1L +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (1ul << 11) +#define PIN_PB12B_SLCD_LP22 44L /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 1L +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (1ul << 12) +#define PIN_PB13B_SLCD_LP23 45L /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 1L +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (1ul << 13) +#define PIN_PB14B_SLCD_LP24 46L /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 1L +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (1ul << 14) +#define PIN_PB15B_SLCD_LP25 47L /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 1L +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (1ul << 15) +#define PIN_PC14B_SLCD_LP26 78L /**< \brief SLCD signal: LP26 on PC14 mux B */ +#define MUX_PC14B_SLCD_LP26 1L +#define PINMUX_PC14B_SLCD_LP26 ((PIN_PC14B_SLCD_LP26 << 16) | MUX_PC14B_SLCD_LP26) +#define PORT_PC14B_SLCD_LP26 (1ul << 14) +#define PIN_PC15B_SLCD_LP27 79L /**< \brief SLCD signal: LP27 on PC15 mux B */ +#define MUX_PC15B_SLCD_LP27 1L +#define PINMUX_PC15B_SLCD_LP27 ((PIN_PC15B_SLCD_LP27 << 16) | MUX_PC15B_SLCD_LP27) +#define PORT_PC15B_SLCD_LP27 (1ul << 15) +#define PIN_PA12B_SLCD_LP28 12L /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 1L +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (1ul << 12) +#define PIN_PA13B_SLCD_LP29 13L /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 1L +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (1ul << 13) +#define PIN_PA14B_SLCD_LP30 14L /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 1L +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (1ul << 14) +#define PIN_PA15B_SLCD_LP31 15L /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 1L +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (1ul << 15) +#define PIN_PA16B_SLCD_LP32 16L /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 1L +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (1ul << 16) +#define PIN_PA17B_SLCD_LP33 17L /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 1L +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (1ul << 17) +#define PIN_PA18B_SLCD_LP34 18L /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 1L +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (1ul << 18) +#define PIN_PA19B_SLCD_LP35 19L /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 1L +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (1ul << 19) +#define PIN_PC16B_SLCD_LP36 80L /**< \brief SLCD signal: LP36 on PC16 mux B */ +#define MUX_PC16B_SLCD_LP36 1L +#define PINMUX_PC16B_SLCD_LP36 ((PIN_PC16B_SLCD_LP36 << 16) | MUX_PC16B_SLCD_LP36) +#define PORT_PC16B_SLCD_LP36 (1ul << 16) +#define PIN_PC17B_SLCD_LP37 81L /**< \brief SLCD signal: LP37 on PC17 mux B */ +#define MUX_PC17B_SLCD_LP37 1L +#define PINMUX_PC17B_SLCD_LP37 ((PIN_PC17B_SLCD_LP37 << 16) | MUX_PC17B_SLCD_LP37) +#define PORT_PC17B_SLCD_LP37 (1ul << 17) +#define PIN_PC18B_SLCD_LP38 82L /**< \brief SLCD signal: LP38 on PC18 mux B */ +#define MUX_PC18B_SLCD_LP38 1L +#define PINMUX_PC18B_SLCD_LP38 ((PIN_PC18B_SLCD_LP38 << 16) | MUX_PC18B_SLCD_LP38) +#define PORT_PC18B_SLCD_LP38 (1ul << 18) +#define PIN_PC19B_SLCD_LP39 83L /**< \brief SLCD signal: LP39 on PC19 mux B */ +#define MUX_PC19B_SLCD_LP39 1L +#define PINMUX_PC19B_SLCD_LP39 ((PIN_PC19B_SLCD_LP39 << 16) | MUX_PC19B_SLCD_LP39) +#define PORT_PC19B_SLCD_LP39 (1ul << 19) +#define PIN_PC20B_SLCD_LP40 84L /**< \brief SLCD signal: LP40 on PC20 mux B */ +#define MUX_PC20B_SLCD_LP40 1L +#define PINMUX_PC20B_SLCD_LP40 ((PIN_PC20B_SLCD_LP40 << 16) | MUX_PC20B_SLCD_LP40) +#define PORT_PC20B_SLCD_LP40 (1ul << 20) +#define PIN_PC21B_SLCD_LP41 85L /**< \brief SLCD signal: LP41 on PC21 mux B */ +#define MUX_PC21B_SLCD_LP41 1L +#define PINMUX_PC21B_SLCD_LP41 ((PIN_PC21B_SLCD_LP41 << 16) | MUX_PC21B_SLCD_LP41) +#define PORT_PC21B_SLCD_LP41 (1ul << 21) +#define PIN_PB16B_SLCD_LP42 48L /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 1L +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (1ul << 16) +#define PIN_PB17B_SLCD_LP43 49L /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 1L +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (1ul << 17) +#define PIN_PB18B_SLCD_LP44 50L /**< \brief SLCD signal: LP44 on PB18 mux B */ +#define MUX_PB18B_SLCD_LP44 1L +#define PINMUX_PB18B_SLCD_LP44 ((PIN_PB18B_SLCD_LP44 << 16) | MUX_PB18B_SLCD_LP44) +#define PORT_PB18B_SLCD_LP44 (1ul << 18) +#define PIN_PB19B_SLCD_LP45 51L /**< \brief SLCD signal: LP45 on PB19 mux B */ +#define MUX_PB19B_SLCD_LP45 1L +#define PINMUX_PB19B_SLCD_LP45 ((PIN_PB19B_SLCD_LP45 << 16) | MUX_PB19B_SLCD_LP45) +#define PORT_PB19B_SLCD_LP45 (1ul << 19) +#define PIN_PB20B_SLCD_LP46 52L /**< \brief SLCD signal: LP46 on PB20 mux B */ +#define MUX_PB20B_SLCD_LP46 1L +#define PINMUX_PB20B_SLCD_LP46 ((PIN_PB20B_SLCD_LP46 << 16) | MUX_PB20B_SLCD_LP46) +#define PORT_PB20B_SLCD_LP46 (1ul << 20) +#define PIN_PB21B_SLCD_LP47 53L /**< \brief SLCD signal: LP47 on PB21 mux B */ +#define MUX_PB21B_SLCD_LP47 1L +#define PINMUX_PB21B_SLCD_LP47 ((PIN_PB21B_SLCD_LP47 << 16) | MUX_PB21B_SLCD_LP47) +#define PORT_PB21B_SLCD_LP47 (1ul << 21) +#define PIN_PA20B_SLCD_LP48 20L /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 1L +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (1ul << 20) +#define PIN_PA21B_SLCD_LP49 21L /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 1L +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (1ul << 21) +#define PIN_PA22B_SLCD_LP50 22L /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 1L +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (1ul << 22) +#define PIN_PA23B_SLCD_LP51 23L /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 1L +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (1ul << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 8L +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (1ul << 0) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 8L +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (1ul << 1) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PC27I_CCL_IN4 91L /**< \brief CCL signal: IN4 on PC27 mux I */ +#define MUX_PC27I_CCL_IN4 8L +#define PINMUX_PC27I_CCL_IN4 ((PIN_PC27I_CCL_IN4 << 16) | MUX_PC27I_CCL_IN4) +#define PORT_PC27I_CCL_IN4 (1ul << 27) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PC28I_CCL_IN5 92L /**< \brief CCL signal: IN5 on PC28 mux I */ +#define MUX_PC28I_CCL_IN5 8L +#define PINMUX_PC28I_CCL_IN5 ((PIN_PC28I_CCL_IN5 << 16) | MUX_PC28I_CCL_IN5) +#define PORT_PC28I_CCL_IN5 (1ul << 28) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 8L +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (1ul << 6) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 8L +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (1ul << 7) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 8L +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (1ul << 14) +#define PIN_PC20I_CCL_IN9 84L /**< \brief CCL signal: IN9 on PC20 mux I */ +#define MUX_PC20I_CCL_IN9 8L +#define PINMUX_PC20I_CCL_IN9 ((PIN_PC20I_CCL_IN9 << 16) | MUX_PC20I_CCL_IN9) +#define PORT_PC20I_CCL_IN9 (1ul << 20) +#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 8L +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (1ul << 15) +#define PIN_PC21I_CCL_IN10 85L /**< \brief CCL signal: IN10 on PC21 mux I */ +#define MUX_PC21I_CCL_IN10 8L +#define PINMUX_PC21I_CCL_IN10 ((PIN_PC21I_CCL_IN10 << 16) | MUX_PC21I_CCL_IN10) +#define PORT_PC21I_CCL_IN10 (1ul << 21) +#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 8L +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (1ul << 16) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) +#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 8L +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (1ul << 17) + +#endif /* _SAML22N17A_PIO_ */ diff --git a/Sensor Watch Starter Project/include/pio/saml22n18a.h b/Sensor Watch Starter Project/include/pio/saml22n18a.h new file mode 100755 index 00000000..108790c5 --- /dev/null +++ b/Sensor Watch Starter Project/include/pio/saml22n18a.h @@ -0,0 +1,1789 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22N18A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N18A_PIO_ +#define _SAML22N18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (1ul << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (1ul << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (1ul << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (1ul << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (1ul << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (1ul << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (1ul << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (1ul << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (1ul << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (1ul << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (1ul << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (1ul << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (1ul << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC08 72 /**< \brief Pin Number for PC08 */ +#define PORT_PC08 (1ul << 8) /**< \brief PORT Mask for PC08 */ +#define PIN_PC09 73 /**< \brief Pin Number for PC09 */ +#define PORT_PC09 (1ul << 9) /**< \brief PORT Mask for PC09 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (1ul << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (1ul << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (1ul << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (1ul << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (1ul << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (1ul << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (1ul << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (1ul << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (1ul << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (1ul << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (1ul << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (1ul << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (1ul << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (1ul << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 7L +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (1ul << 1) +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK 7L +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (1ul << 0) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 7L +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (1ul << 14) +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 7L +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (1ul << 15) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 7L +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (1ul << 16) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 7L +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 32L /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 6L +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (1ul << 0) +#define PIN_PB02G_RTC_IN1 34L /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 6L +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (1ul << 2) +#define PIN_PA02G_RTC_IN2 2L /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 6L +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (1ul << 2) +#define PIN_PB01F_RTC_IN2 33L /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 5L +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (1ul << 1) +#define PIN_PC00G_RTC_IN3 64L /**< \brief RTC signal: IN3 on PC00 mux G */ +#define MUX_PC00G_RTC_IN3 6L +#define PINMUX_PC00G_RTC_IN3 ((PIN_PC00G_RTC_IN3 << 16) | MUX_PC00G_RTC_IN3) +#define PORT_PC00G_RTC_IN3 (1ul << 0) +#define PIN_PC01G_RTC_IN4 65L /**< \brief RTC signal: IN4 on PC01 mux G */ +#define MUX_PC01G_RTC_IN4 6L +#define PINMUX_PC01G_RTC_IN4 ((PIN_PC01G_RTC_IN4 << 16) | MUX_PC01G_RTC_IN4) +#define PORT_PC01G_RTC_IN4 (1ul << 1) +#define PIN_PB01G_RTC_OUT 33L /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT 6L +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (1ul << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 0L +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 0L +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PC08A_EIC_EXTINT0 72L /**< \brief EIC signal: EXTINT0 on PC08 mux A */ +#define MUX_PC08A_EIC_EXTINT0 0L +#define PINMUX_PC08A_EIC_EXTINT0 ((PIN_PC08A_EIC_EXTINT0 << 16) | MUX_PC08A_EIC_EXTINT0) +#define PORT_PC08A_EIC_EXTINT0 (1ul << 8) +#define PIN_PC24A_EIC_EXTINT0 88L /**< \brief EIC signal: EXTINT0 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT0 0L +#define PINMUX_PC24A_EIC_EXTINT0 ((PIN_PC24A_EIC_EXTINT0 << 16) | MUX_PC24A_EIC_EXTINT0) +#define PORT_PC24A_EIC_EXTINT0 (1ul << 24) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 0L +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 0L +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PC09A_EIC_EXTINT1 73L /**< \brief EIC signal: EXTINT1 on PC09 mux A */ +#define MUX_PC09A_EIC_EXTINT1 0L +#define PINMUX_PC09A_EIC_EXTINT1 ((PIN_PC09A_EIC_EXTINT1 << 16) | MUX_PC09A_EIC_EXTINT1) +#define PORT_PC09A_EIC_EXTINT1 (1ul << 9) +#define PIN_PC25A_EIC_EXTINT1 89L /**< \brief EIC signal: EXTINT1 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT1 0L +#define PINMUX_PC25A_EIC_EXTINT1 ((PIN_PC25A_EIC_EXTINT1 << 16) | MUX_PC25A_EIC_EXTINT1) +#define PORT_PC25A_EIC_EXTINT1 (1ul << 25) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PB18A_EIC_EXTINT2 50L /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 0L +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PC10A_EIC_EXTINT2 74L /**< \brief EIC signal: EXTINT2 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT2 0L +#define PINMUX_PC10A_EIC_EXTINT2 ((PIN_PC10A_EIC_EXTINT2 << 16) | MUX_PC10A_EIC_EXTINT2) +#define PORT_PC10A_EIC_EXTINT2 (1ul << 10) +#define PIN_PC26A_EIC_EXTINT2 90L /**< \brief EIC signal: EXTINT2 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT2 0L +#define PINMUX_PC26A_EIC_EXTINT2 ((PIN_PC26A_EIC_EXTINT2 << 16) | MUX_PC26A_EIC_EXTINT2) +#define PORT_PC26A_EIC_EXTINT2 (1ul << 26) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PB19A_EIC_EXTINT3 51L /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 0L +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PC11A_EIC_EXTINT3 75L /**< \brief EIC signal: EXTINT3 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT3 0L +#define PINMUX_PC11A_EIC_EXTINT3 ((PIN_PC11A_EIC_EXTINT3 << 16) | MUX_PC11A_EIC_EXTINT3) +#define PORT_PC11A_EIC_EXTINT3 (1ul << 11) +#define PIN_PC27A_EIC_EXTINT3 91L /**< \brief EIC signal: EXTINT3 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT3 0L +#define PINMUX_PC27A_EIC_EXTINT3 ((PIN_PC27A_EIC_EXTINT3 << 16) | MUX_PC27A_EIC_EXTINT3) +#define PORT_PC27A_EIC_EXTINT3 (1ul << 27) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 0L +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PB20A_EIC_EXTINT4 52L /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 0L +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PC12A_EIC_EXTINT4 76L /**< \brief EIC signal: EXTINT4 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT4 0L +#define PINMUX_PC12A_EIC_EXTINT4 ((PIN_PC12A_EIC_EXTINT4 << 16) | MUX_PC12A_EIC_EXTINT4) +#define PORT_PC12A_EIC_EXTINT4 (1ul << 12) +#define PIN_PC28A_EIC_EXTINT4 92L /**< \brief EIC signal: EXTINT4 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT4 0L +#define PINMUX_PC28A_EIC_EXTINT4 ((PIN_PC28A_EIC_EXTINT4 << 16) | MUX_PC28A_EIC_EXTINT4) +#define PORT_PC28A_EIC_EXTINT4 (1ul << 28) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 0L +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PB21A_EIC_EXTINT5 53L /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 0L +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PC13A_EIC_EXTINT5 77L /**< \brief EIC signal: EXTINT5 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT5 0L +#define PINMUX_PC13A_EIC_EXTINT5 ((PIN_PC13A_EIC_EXTINT5 << 16) | MUX_PC13A_EIC_EXTINT5) +#define PORT_PC13A_EIC_EXTINT5 (1ul << 13) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 0L +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PC14A_EIC_EXTINT6 78L /**< \brief EIC signal: EXTINT6 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT6 0L +#define PINMUX_PC14A_EIC_EXTINT6 ((PIN_PC14A_EIC_EXTINT6 << 16) | MUX_PC14A_EIC_EXTINT6) +#define PORT_PC14A_EIC_EXTINT6 (1ul << 14) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 0L +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PC15A_EIC_EXTINT7 79L /**< \brief EIC signal: EXTINT7 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT7 0L +#define PINMUX_PC15A_EIC_EXTINT7 ((PIN_PC15A_EIC_EXTINT7 << 16) | MUX_PC15A_EIC_EXTINT7) +#define PORT_PC15A_EIC_EXTINT7 (1ul << 15) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PB24A_EIC_EXTINT8 56L /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 0L +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (1ul << 24) +#define PIN_PC00A_EIC_EXTINT8 64L /**< \brief EIC signal: EXTINT8 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT8 0L +#define PINMUX_PC00A_EIC_EXTINT8 ((PIN_PC00A_EIC_EXTINT8 << 16) | MUX_PC00A_EIC_EXTINT8) +#define PORT_PC00A_EIC_EXTINT8 (1ul << 0) +#define PIN_PC16A_EIC_EXTINT8 80L /**< \brief EIC signal: EXTINT8 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT8 0L +#define PINMUX_PC16A_EIC_EXTINT8 ((PIN_PC16A_EIC_EXTINT8 << 16) | MUX_PC16A_EIC_EXTINT8) +#define PORT_PC16A_EIC_EXTINT8 (1ul << 16) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB25A_EIC_EXTINT9 57L /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 0L +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (1ul << 25) +#define PIN_PC01A_EIC_EXTINT9 65L /**< \brief EIC signal: EXTINT9 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT9 0L +#define PINMUX_PC01A_EIC_EXTINT9 ((PIN_PC01A_EIC_EXTINT9 << 16) | MUX_PC01A_EIC_EXTINT9) +#define PORT_PC01A_EIC_EXTINT9 (1ul << 1) +#define PIN_PC17A_EIC_EXTINT9 81L /**< \brief EIC signal: EXTINT9 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT9 0L +#define PINMUX_PC17A_EIC_EXTINT9 ((PIN_PC17A_EIC_EXTINT9 << 16) | MUX_PC17A_EIC_EXTINT9) +#define PORT_PC17A_EIC_EXTINT9 (1ul << 17) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PC02A_EIC_EXTINT10 66L /**< \brief EIC signal: EXTINT10 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT10 0L +#define PINMUX_PC02A_EIC_EXTINT10 ((PIN_PC02A_EIC_EXTINT10 << 16) | MUX_PC02A_EIC_EXTINT10) +#define PORT_PC02A_EIC_EXTINT10 (1ul << 2) +#define PIN_PC18A_EIC_EXTINT10 82L /**< \brief EIC signal: EXTINT10 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT10 0L +#define PINMUX_PC18A_EIC_EXTINT10 ((PIN_PC18A_EIC_EXTINT10 << 16) | MUX_PC18A_EIC_EXTINT10) +#define PORT_PC18A_EIC_EXTINT10 (1ul << 18) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PC03A_EIC_EXTINT11 67L /**< \brief EIC signal: EXTINT11 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT11 0L +#define PINMUX_PC03A_EIC_EXTINT11 ((PIN_PC03A_EIC_EXTINT11 << 16) | MUX_PC03A_EIC_EXTINT11) +#define PORT_PC03A_EIC_EXTINT11 (1ul << 3) +#define PIN_PC19A_EIC_EXTINT11 83L /**< \brief EIC signal: EXTINT11 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT11 0L +#define PINMUX_PC19A_EIC_EXTINT11 ((PIN_PC19A_EIC_EXTINT11 << 16) | MUX_PC19A_EIC_EXTINT11) +#define PORT_PC19A_EIC_EXTINT11 (1ul << 19) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 0L +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PC20A_EIC_EXTINT12 84L /**< \brief EIC signal: EXTINT12 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT12 0L +#define PINMUX_PC20A_EIC_EXTINT12 ((PIN_PC20A_EIC_EXTINT12 << 16) | MUX_PC20A_EIC_EXTINT12) +#define PORT_PC20A_EIC_EXTINT12 (1ul << 20) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 0L +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PC05A_EIC_EXTINT13 69L /**< \brief EIC signal: EXTINT13 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT13 0L +#define PINMUX_PC05A_EIC_EXTINT13 ((PIN_PC05A_EIC_EXTINT13 << 16) | MUX_PC05A_EIC_EXTINT13) +#define PORT_PC05A_EIC_EXTINT13 (1ul << 5) +#define PIN_PC21A_EIC_EXTINT13 85L /**< \brief EIC signal: EXTINT13 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT13 0L +#define PINMUX_PC21A_EIC_EXTINT13 ((PIN_PC21A_EIC_EXTINT13 << 16) | MUX_PC21A_EIC_EXTINT13) +#define PORT_PC21A_EIC_EXTINT13 (1ul << 21) +#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 0L +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 0L +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) +#define PIN_PC06A_EIC_EXTINT14 70L /**< \brief EIC signal: EXTINT14 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT14 0L +#define PINMUX_PC06A_EIC_EXTINT14 ((PIN_PC06A_EIC_EXTINT14 << 16) | MUX_PC06A_EIC_EXTINT14) +#define PORT_PC06A_EIC_EXTINT14 (1ul << 6) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 0L +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 0L +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) +#define PIN_PC07A_EIC_EXTINT15 71L /**< \brief EIC signal: EXTINT15 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT15 0L +#define PINMUX_PC07A_EIC_EXTINT15 ((PIN_PC07A_EIC_EXTINT15 << 16) | MUX_PC07A_EIC_EXTINT15) +#define PORT_PC07A_EIC_EXTINT15 (1ul << 7) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +#define PIN_PB22G_USB_SOF_1KHZ 54L /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ 6L +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (1ul << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA20C_SERCOM0_PAD0 20L /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 2L +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (1ul << 20) +#define PIN_PB24C_SERCOM0_PAD0 56L /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 2L +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (1ul << 24) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA21C_SERCOM0_PAD1 21L /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 2L +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (1ul << 21) +#define PIN_PB25C_SERCOM0_PAD1 57L /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 2L +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (1ul << 25) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA22C_SERCOM0_PAD2 22L /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 2L +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PC24C_SERCOM0_PAD2 88L /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 2L +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (1ul << 24) +#define PIN_PB22C_SERCOM0_PAD2 54L /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 2L +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (1ul << 22) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +#define PIN_PA23C_SERCOM0_PAD3 23L /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 2L +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (1ul << 23) +#define PIN_PC25C_SERCOM0_PAD3 89L /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 2L +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (1ul << 25) +#define PIN_PB23C_SERCOM0_PAD3 55L /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 2L +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (1ul << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 62L /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 2L +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (1ul << 30) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PC27D_SERCOM1_PAD0 91L /**< \brief SERCOM1 signal: PAD0 on PC27 mux D */ +#define MUX_PC27D_SERCOM1_PAD0 3L +#define PINMUX_PC27D_SERCOM1_PAD0 ((PIN_PC27D_SERCOM1_PAD0 << 16) | MUX_PC27D_SERCOM1_PAD0) +#define PORT_PC27D_SERCOM1_PAD0 (1ul << 27) +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PC12C_SERCOM1_PAD0 76L /**< \brief SERCOM1 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM1_PAD0 2L +#define PINMUX_PC12C_SERCOM1_PAD0 ((PIN_PC12C_SERCOM1_PAD0 << 16) | MUX_PC12C_SERCOM1_PAD0) +#define PORT_PC12C_SERCOM1_PAD0 (1ul << 12) +#define PIN_PB31C_SERCOM1_PAD1 63L /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 2L +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (1ul << 31) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PC28D_SERCOM1_PAD1 92L /**< \brief SERCOM1 signal: PAD1 on PC28 mux D */ +#define MUX_PC28D_SERCOM1_PAD1 3L +#define PINMUX_PC28D_SERCOM1_PAD1 ((PIN_PC28D_SERCOM1_PAD1 << 16) | MUX_PC28D_SERCOM1_PAD1) +#define PORT_PC28D_SERCOM1_PAD1 (1ul << 28) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PC13C_SERCOM1_PAD1 77L /**< \brief SERCOM1 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM1_PAD1 2L +#define PINMUX_PC13C_SERCOM1_PAD1 ((PIN_PC13C_SERCOM1_PAD1 << 16) | MUX_PC13C_SERCOM1_PAD1) +#define PORT_PC13C_SERCOM1_PAD1 (1ul << 13) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PC10C_SERCOM1_PAD2 74L /**< \brief SERCOM1 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM1_PAD2 2L +#define PINMUX_PC10C_SERCOM1_PAD2 ((PIN_PC10C_SERCOM1_PAD2 << 16) | MUX_PC10C_SERCOM1_PAD2) +#define PORT_PC10C_SERCOM1_PAD2 (1ul << 10) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +#define PIN_PC11C_SERCOM1_PAD3 75L /**< \brief SERCOM1 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM1_PAD3 2L +#define PINMUX_PC11C_SERCOM1_PAD3 ((PIN_PC11C_SERCOM1_PAD3 << 16) | MUX_PC11C_SERCOM1_PAD3) +#define PORT_PC11C_SERCOM1_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 3L +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22) +#define PIN_PA16D_SERCOM2_PAD0 16L /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 3L +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 3L +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23) +#define PIN_PA17D_SERCOM2_PAD1 17L /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 3L +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (1ul << 17) +#define PIN_PA18D_SERCOM2_PAD2 18L /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 3L +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM2_PAD2 20L /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 3L +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 2L +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM2_PAD3 19L /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 3L +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM2_PAD3 21L /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 3L +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 2L +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 44L /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 2L +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (1ul << 12) +#define PIN_PA12D_SERCOM3_PAD0 12L /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 3L +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM3_PAD0 40L /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 3L +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (1ul << 8) +#define PIN_PB02C_SERCOM3_PAD0 34L /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 2L +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (1ul << 2) +#define PIN_PB20C_SERCOM3_PAD0 52L /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 2L +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (1ul << 20) +#define PIN_PB13C_SERCOM3_PAD1 45L /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 2L +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (1ul << 13) +#define PIN_PA13D_SERCOM3_PAD1 13L /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 3L +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM3_PAD1 41L /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 3L +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (1ul << 9) +#define PIN_PB03C_SERCOM3_PAD1 35L /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 2L +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (1ul << 3) +#define PIN_PB21C_SERCOM3_PAD1 53L /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 2L +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (1ul << 21) +#define PIN_PB14C_SERCOM3_PAD2 46L /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 2L +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (1ul << 14) +#define PIN_PA14D_SERCOM3_PAD2 14L /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 3L +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (1ul << 14) +#define PIN_PB18D_SERCOM3_PAD2 50L /**< \brief SERCOM3 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM3_PAD2 3L +#define PINMUX_PB18D_SERCOM3_PAD2 ((PIN_PB18D_SERCOM3_PAD2 << 16) | MUX_PB18D_SERCOM3_PAD2) +#define PORT_PB18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PB00C_SERCOM3_PAD2 32L /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 2L +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (1ul << 0) +#define PIN_PB15C_SERCOM3_PAD3 47L /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 2L +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (1ul << 15) +#define PIN_PA15D_SERCOM3_PAD3 15L /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 3L +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM3_PAD3 43L /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 3L +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (1ul << 11) +#define PIN_PB19D_SERCOM3_PAD3 51L /**< \brief SERCOM3 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM3_PAD3 3L +#define PINMUX_PB19D_SERCOM3_PAD3 ((PIN_PB19D_SERCOM3_PAD3 << 16) | MUX_PB19D_SERCOM3_PAD3) +#define PORT_PB19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PB01C_SERCOM3_PAD3 33L /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 2L +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (1ul << 1) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA08D_SERCOM4_PAD0 8L /**< \brief SERCOM4 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM4_PAD0 3L +#define PINMUX_PA08D_SERCOM4_PAD0 ((PIN_PA08D_SERCOM4_PAD0 << 16) | MUX_PA08D_SERCOM4_PAD0) +#define PORT_PA08D_SERCOM4_PAD0 (1ul << 8) +#define PIN_PB24D_SERCOM4_PAD0 56L /**< \brief SERCOM4 signal: PAD0 on PB24 mux D */ +#define MUX_PB24D_SERCOM4_PAD0 3L +#define PINMUX_PB24D_SERCOM4_PAD0 ((PIN_PB24D_SERCOM4_PAD0 << 16) | MUX_PB24D_SERCOM4_PAD0) +#define PORT_PB24D_SERCOM4_PAD0 (1ul << 24) +#define PIN_PA12C_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM4_PAD0 2L +#define PINMUX_PA12C_SERCOM4_PAD0 ((PIN_PA12C_SERCOM4_PAD0 << 16) | MUX_PA12C_SERCOM4_PAD0) +#define PORT_PA12C_SERCOM4_PAD0 (1ul << 12) +#define PIN_PA09D_SERCOM4_PAD1 9L /**< \brief SERCOM4 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM4_PAD1 3L +#define PINMUX_PA09D_SERCOM4_PAD1 ((PIN_PA09D_SERCOM4_PAD1 << 16) | MUX_PA09D_SERCOM4_PAD1) +#define PORT_PA09D_SERCOM4_PAD1 (1ul << 9) +#define PIN_PB25D_SERCOM4_PAD1 57L /**< \brief SERCOM4 signal: PAD1 on PB25 mux D */ +#define MUX_PB25D_SERCOM4_PAD1 3L +#define PINMUX_PB25D_SERCOM4_PAD1 ((PIN_PB25D_SERCOM4_PAD1 << 16) | MUX_PB25D_SERCOM4_PAD1) +#define PORT_PB25D_SERCOM4_PAD1 (1ul << 25) +#define PIN_PA13C_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM4_PAD1 2L +#define PINMUX_PA13C_SERCOM4_PAD1 ((PIN_PA13C_SERCOM4_PAD1 << 16) | MUX_PA13C_SERCOM4_PAD1) +#define PORT_PA13C_SERCOM4_PAD1 (1ul << 13) +#define PIN_PA10D_SERCOM4_PAD2 10L /**< \brief SERCOM4 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM4_PAD2 3L +#define PINMUX_PA10D_SERCOM4_PAD2 ((PIN_PA10D_SERCOM4_PAD2 << 16) | MUX_PA10D_SERCOM4_PAD2) +#define PORT_PA10D_SERCOM4_PAD2 (1ul << 10) +#define PIN_PC24D_SERCOM4_PAD2 88L /**< \brief SERCOM4 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM4_PAD2 3L +#define PINMUX_PC24D_SERCOM4_PAD2 ((PIN_PC24D_SERCOM4_PAD2 << 16) | MUX_PC24D_SERCOM4_PAD2) +#define PORT_PC24D_SERCOM4_PAD2 (1ul << 24) +#define PIN_PA14C_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM4_PAD2 2L +#define PINMUX_PA14C_SERCOM4_PAD2 ((PIN_PA14C_SERCOM4_PAD2 << 16) | MUX_PA14C_SERCOM4_PAD2) +#define PORT_PA14C_SERCOM4_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM4_PAD3 11L /**< \brief SERCOM4 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM4_PAD3 3L +#define PINMUX_PA11D_SERCOM4_PAD3 ((PIN_PA11D_SERCOM4_PAD3 << 16) | MUX_PA11D_SERCOM4_PAD3) +#define PORT_PA11D_SERCOM4_PAD3 (1ul << 11) +#define PIN_PC25D_SERCOM4_PAD3 89L /**< \brief SERCOM4 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM4_PAD3 3L +#define PINMUX_PC25D_SERCOM4_PAD3 ((PIN_PC25D_SERCOM4_PAD3 << 16) | MUX_PC25D_SERCOM4_PAD3) +#define PORT_PC25D_SERCOM4_PAD3 (1ul << 25) +#define PIN_PA15C_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM4_PAD3 2L +#define PINMUX_PA15C_SERCOM4_PAD3 ((PIN_PA15C_SERCOM4_PAD3 << 16) | MUX_PA15C_SERCOM4_PAD3) +#define PORT_PA15C_SERCOM4_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD0 3L +#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) +#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) +#define PIN_PA24D_SERCOM5_PAD0 24L /**< \brief SERCOM5 signal: PAD0 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD0 3L +#define PINMUX_PA24D_SERCOM5_PAD0 ((PIN_PA24D_SERCOM5_PAD0 << 16) | MUX_PA24D_SERCOM5_PAD0) +#define PORT_PA24D_SERCOM5_PAD0 (1ul << 24) +#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 3L +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) +#define PIN_PB20D_SERCOM5_PAD0 52L /**< \brief SERCOM5 signal: PAD0 on PB20 mux D */ +#define MUX_PB20D_SERCOM5_PAD0 3L +#define PINMUX_PB20D_SERCOM5_PAD0 ((PIN_PB20D_SERCOM5_PAD0 << 16) | MUX_PB20D_SERCOM5_PAD0) +#define PORT_PB20D_SERCOM5_PAD0 (1ul << 20) +#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 2L +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) +#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD1 3L +#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) +#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) +#define PIN_PA25D_SERCOM5_PAD1 25L /**< \brief SERCOM5 signal: PAD1 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD1 3L +#define PINMUX_PA25D_SERCOM5_PAD1 ((PIN_PA25D_SERCOM5_PAD1 << 16) | MUX_PA25D_SERCOM5_PAD1) +#define PORT_PA25D_SERCOM5_PAD1 (1ul << 25) +#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 3L +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) +#define PIN_PB21D_SERCOM5_PAD1 53L /**< \brief SERCOM5 signal: PAD1 on PB21 mux D */ +#define MUX_PB21D_SERCOM5_PAD1 3L +#define PINMUX_PB21D_SERCOM5_PAD1 ((PIN_PB21D_SERCOM5_PAD1 << 16) | MUX_PB21D_SERCOM5_PAD1) +#define PORT_PB21D_SERCOM5_PAD1 (1ul << 21) +#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 2L +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) +#define PIN_PB18C_SERCOM5_PAD2 50L /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 2L +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (1ul << 18) +#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 3L +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) +#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 3L +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) +#define PIN_PB19C_SERCOM5_PAD3 51L /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 2L +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (1ul << 19) +#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 3L +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) +#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 3L +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 24L /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 5L +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (1ul << 24) +#define PIN_PB18F_TCC0_WO0 50L /**< \brief TCC0 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC0_WO0 5L +#define PINMUX_PB18F_TCC0_WO0 ((PIN_PB18F_TCC0_WO0 << 16) | MUX_PB18F_TCC0_WO0) +#define PORT_PB18F_TCC0_WO0 (1ul << 18) +#define PIN_PC24F_TCC0_WO0 88L /**< \brief TCC0 signal: WO0 on PC24 mux F */ +#define MUX_PC24F_TCC0_WO0 5L +#define PINMUX_PC24F_TCC0_WO0 ((PIN_PC24F_TCC0_WO0 << 16) | MUX_PC24F_TCC0_WO0) +#define PORT_PC24F_TCC0_WO0 (1ul << 24) +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 4L +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (1ul << 30) +#define PIN_PA25F_TCC0_WO1 25L /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 5L +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (1ul << 25) +#define PIN_PB19F_TCC0_WO1 51L /**< \brief TCC0 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC0_WO1 5L +#define PINMUX_PB19F_TCC0_WO1 ((PIN_PB19F_TCC0_WO1 << 16) | MUX_PB19F_TCC0_WO1) +#define PORT_PB19F_TCC0_WO1 (1ul << 19) +#define PIN_PC25F_TCC0_WO1 89L /**< \brief TCC0 signal: WO1 on PC25 mux F */ +#define MUX_PC25F_TCC0_WO1 5L +#define PINMUX_PC25F_TCC0_WO1 ((PIN_PC25F_TCC0_WO1 << 16) | MUX_PC25F_TCC0_WO1) +#define PORT_PC25F_TCC0_WO1 (1ul << 25) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 4L +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (1ul << 31) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PB20F_TCC0_WO2 52L /**< \brief TCC0 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC0_WO2 5L +#define PINMUX_PB20F_TCC0_WO2 ((PIN_PB20F_TCC0_WO2 << 16) | MUX_PB20F_TCC0_WO2) +#define PORT_PB20F_TCC0_WO2 (1ul << 20) +#define PIN_PB22F_TCC0_WO2 54L /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 5L +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (1ul << 22) +#define PIN_PC26F_TCC0_WO2 90L /**< \brief TCC0 signal: WO2 on PC26 mux F */ +#define MUX_PC26F_TCC0_WO2 5L +#define PINMUX_PC26F_TCC0_WO2 ((PIN_PC26F_TCC0_WO2 << 16) | MUX_PC26F_TCC0_WO2) +#define PORT_PC26F_TCC0_WO2 (1ul << 26) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PB21F_TCC0_WO3 53L /**< \brief TCC0 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC0_WO3 5L +#define PINMUX_PB21F_TCC0_WO3 ((PIN_PB21F_TCC0_WO3 << 16) | MUX_PB21F_TCC0_WO3) +#define PORT_PB21F_TCC0_WO3 (1ul << 21) +#define PIN_PB23F_TCC0_WO3 55L /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 5L +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (1ul << 23) +#define PIN_PC27F_TCC0_WO3 91L /**< \brief TCC0 signal: WO3 on PC27 mux F */ +#define MUX_PC27F_TCC0_WO3 5L +#define PINMUX_PC27F_TCC0_WO3 ((PIN_PC27F_TCC0_WO3 << 16) | MUX_PC27F_TCC0_WO3) +#define PORT_PC27F_TCC0_WO3 (1ul << 27) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 5L +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (1ul << 16) +#define PIN_PC28F_TCC0_WO4 92L /**< \brief TCC0 signal: WO4 on PC28 mux F */ +#define MUX_PC28F_TCC0_WO4 5L +#define PINMUX_PC28F_TCC0_WO4 ((PIN_PC28F_TCC0_WO4 << 16) | MUX_PC28F_TCC0_WO4) +#define PORT_PC28F_TCC0_WO4 (1ul << 28) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA27F_TCC0_WO5 27L /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 5L +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (1ul << 27) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 5L +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (1ul << 17) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 5L +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (1ul << 12) +#define PIN_PB24F_TCC0_WO6 56L /**< \brief TCC0 signal: WO6 on PB24 mux F */ +#define MUX_PB24F_TCC0_WO6 5L +#define PINMUX_PB24F_TCC0_WO6 ((PIN_PB24F_TCC0_WO6 << 16) | MUX_PB24F_TCC0_WO6) +#define PORT_PB24F_TCC0_WO6 (1ul << 24) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 5L +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (1ul << 13) +#define PIN_PB25F_TCC0_WO7 57L /**< \brief TCC0 signal: WO7 on PB25 mux F */ +#define MUX_PB25F_TCC0_WO7 5L +#define PINMUX_PB25F_TCC0_WO7 ((PIN_PB25F_TCC0_WO7 << 16) | MUX_PB25F_TCC0_WO7) +#define PORT_PB25F_TCC0_WO7 (1ul << 25) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 4L +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (1ul << 12) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 4L +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (1ul << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 4L +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (1ul << 14) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 4L +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (1ul << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 4L +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (1ul << 16) +#define PIN_PC24E_TC2_WO0 88L /**< \brief TC2 signal: WO0 on PC24 mux E */ +#define MUX_PC24E_TC2_WO0 4L +#define PINMUX_PC24E_TC2_WO0 ((PIN_PC24E_TC2_WO0 << 16) | MUX_PC24E_TC2_WO0) +#define PORT_PC24E_TC2_WO0 (1ul << 24) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 4L +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (1ul << 17) +#define PIN_PC25E_TC2_WO1 89L /**< \brief TC2 signal: WO1 on PC25 mux E */ +#define MUX_PC25E_TC2_WO1 4L +#define PINMUX_PC25E_TC2_WO1 ((PIN_PC25E_TC2_WO1 << 16) | MUX_PC25E_TC2_WO1) +#define PORT_PC25E_TC2_WO1 (1ul << 25) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 4L +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (1ul << 0) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PC26E_TC3_WO0 90L /**< \brief TC3 signal: WO0 on PC26 mux E */ +#define MUX_PC26E_TC3_WO0 4L +#define PINMUX_PC26E_TC3_WO0 ((PIN_PC26E_TC3_WO0 << 16) | MUX_PC26E_TC3_WO0) +#define PORT_PC26E_TC3_WO0 (1ul << 26) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 4L +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (1ul << 1) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +#define PIN_PC27E_TC3_WO1 91L /**< \brief TC3 signal: WO1 on PC27 mux E */ +#define MUX_PC27E_TC3_WO1 4L +#define PINMUX_PC27E_TC3_WO1 ((PIN_PC27E_TC3_WO1 << 16) | MUX_PC27E_TC3_WO1) +#define PORT_PC27E_TC3_WO1 (1ul << 27) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 1L +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (1ul << 0) +#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 1L +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (1ul << 1) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 1L +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (1ul << 4) +#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 1L +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (1ul << 5) +#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 1L +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (1ul << 6) +#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 1L +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (1ul << 7) +#define PIN_PC00B_ADC_AIN16 64L /**< \brief ADC signal: AIN16 on PC00 mux B */ +#define MUX_PC00B_ADC_AIN16 1L +#define PINMUX_PC00B_ADC_AIN16 ((PIN_PC00B_ADC_AIN16 << 16) | MUX_PC00B_ADC_AIN16) +#define PORT_PC00B_ADC_AIN16 (1ul << 0) +#define PIN_PC01B_ADC_AIN17 65L /**< \brief ADC signal: AIN17 on PC01 mux B */ +#define MUX_PC01B_ADC_AIN17 1L +#define PINMUX_PC01B_ADC_AIN17 ((PIN_PC01B_ADC_AIN17 << 16) | MUX_PC01B_ADC_AIN17) +#define PORT_PC01B_ADC_AIN17 (1ul << 1) +#define PIN_PC02B_ADC_AIN18 66L /**< \brief ADC signal: AIN18 on PC02 mux B */ +#define MUX_PC02B_ADC_AIN18 1L +#define PINMUX_PC02B_ADC_AIN18 ((PIN_PC02B_ADC_AIN18 << 16) | MUX_PC02B_ADC_AIN18) +#define PORT_PC02B_ADC_AIN18 (1ul << 2) +#define PIN_PC03B_ADC_AIN19 67L /**< \brief ADC signal: AIN19 on PC03 mux B */ +#define MUX_PC03B_ADC_AIN19 1L +#define PINMUX_PC03B_ADC_AIN19 ((PIN_PC03B_ADC_AIN19 << 16) | MUX_PC03B_ADC_AIN19) +#define PORT_PC03B_ADC_AIN19 (1ul << 3) +#define PIN_PA03B_ADC_VREFA 3L /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA 1L +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (1ul << 3) +#define PIN_PA02B_ADC_VREFB 2L /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB 1L +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (1ul << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 2L /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 1L +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (1ul << 2) +#define PIN_PA03B_AC_AIN1 3L /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 1L +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (1ul << 3) +#define PIN_PB04B_AC_AIN2 36L /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 1L +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (1ul << 4) +#define PIN_PB05B_AC_AIN3 37L /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 1L +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (1ul << 5) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PB24H_AC_CMP0 56L /**< \brief AC signal: CMP0 on PB24 mux H */ +#define MUX_PB24H_AC_CMP0 7L +#define PINMUX_PB24H_AC_CMP0 ((PIN_PB24H_AC_CMP0 << 16) | MUX_PB24H_AC_CMP0) +#define PORT_PB24H_AC_CMP0 (1ul << 24) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +#define PIN_PB25H_AC_CMP1 57L /**< \brief AC signal: CMP1 on PB25 mux H */ +#define MUX_PB25H_AC_CMP1 7L +#define PINMUX_PB25H_AC_CMP1 ((PIN_PB25H_AC_CMP1 << 16) | MUX_PB25H_AC_CMP1) +#define PORT_PB25H_AC_CMP1 (1ul << 25) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 38L /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 1L +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (1ul << 6) +#define PIN_PB07B_SLCD_LP1 39L /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 1L +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (1ul << 7) +#define PIN_PB08B_SLCD_LP2 40L /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 1L +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (1ul << 8) +#define PIN_PB09B_SLCD_LP3 41L /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 1L +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (1ul << 9) +#define PIN_PA04B_SLCD_LP4 4L /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 1L +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (1ul << 4) +#define PIN_PA05B_SLCD_LP5 5L /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 1L +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (1ul << 5) +#define PIN_PA06B_SLCD_LP6 6L /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 1L +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (1ul << 6) +#define PIN_PA07B_SLCD_LP7 7L /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 1L +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (1ul << 7) +#define PIN_PC05B_SLCD_LP8 69L /**< \brief SLCD signal: LP8 on PC05 mux B */ +#define MUX_PC05B_SLCD_LP8 1L +#define PINMUX_PC05B_SLCD_LP8 ((PIN_PC05B_SLCD_LP8 << 16) | MUX_PC05B_SLCD_LP8) +#define PORT_PC05B_SLCD_LP8 (1ul << 5) +#define PIN_PC06B_SLCD_LP9 70L /**< \brief SLCD signal: LP9 on PC06 mux B */ +#define MUX_PC06B_SLCD_LP9 1L +#define PINMUX_PC06B_SLCD_LP9 ((PIN_PC06B_SLCD_LP9 << 16) | MUX_PC06B_SLCD_LP9) +#define PORT_PC06B_SLCD_LP9 (1ul << 6) +#define PIN_PC07B_SLCD_LP10 71L /**< \brief SLCD signal: LP10 on PC07 mux B */ +#define MUX_PC07B_SLCD_LP10 1L +#define PINMUX_PC07B_SLCD_LP10 ((PIN_PC07B_SLCD_LP10 << 16) | MUX_PC07B_SLCD_LP10) +#define PORT_PC07B_SLCD_LP10 (1ul << 7) +#define PIN_PA08B_SLCD_LP11 8L /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 1L +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (1ul << 8) +#define PIN_PA09B_SLCD_LP12 9L /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 1L +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (1ul << 9) +#define PIN_PA10B_SLCD_LP13 10L /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 1L +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (1ul << 10) +#define PIN_PA11B_SLCD_LP14 11L /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 1L +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (1ul << 11) +#define PIN_PC08B_SLCD_LP15 72L /**< \brief SLCD signal: LP15 on PC08 mux B */ +#define MUX_PC08B_SLCD_LP15 1L +#define PINMUX_PC08B_SLCD_LP15 ((PIN_PC08B_SLCD_LP15 << 16) | MUX_PC08B_SLCD_LP15) +#define PORT_PC08B_SLCD_LP15 (1ul << 8) +#define PIN_PC09B_SLCD_LP16 73L /**< \brief SLCD signal: LP16 on PC09 mux B */ +#define MUX_PC09B_SLCD_LP16 1L +#define PINMUX_PC09B_SLCD_LP16 ((PIN_PC09B_SLCD_LP16 << 16) | MUX_PC09B_SLCD_LP16) +#define PORT_PC09B_SLCD_LP16 (1ul << 9) +#define PIN_PC10B_SLCD_LP17 74L /**< \brief SLCD signal: LP17 on PC10 mux B */ +#define MUX_PC10B_SLCD_LP17 1L +#define PINMUX_PC10B_SLCD_LP17 ((PIN_PC10B_SLCD_LP17 << 16) | MUX_PC10B_SLCD_LP17) +#define PORT_PC10B_SLCD_LP17 (1ul << 10) +#define PIN_PC11B_SLCD_LP18 75L /**< \brief SLCD signal: LP18 on PC11 mux B */ +#define MUX_PC11B_SLCD_LP18 1L +#define PINMUX_PC11B_SLCD_LP18 ((PIN_PC11B_SLCD_LP18 << 16) | MUX_PC11B_SLCD_LP18) +#define PORT_PC11B_SLCD_LP18 (1ul << 11) +#define PIN_PC12B_SLCD_LP19 76L /**< \brief SLCD signal: LP19 on PC12 mux B */ +#define MUX_PC12B_SLCD_LP19 1L +#define PINMUX_PC12B_SLCD_LP19 ((PIN_PC12B_SLCD_LP19 << 16) | MUX_PC12B_SLCD_LP19) +#define PORT_PC12B_SLCD_LP19 (1ul << 12) +#define PIN_PC13B_SLCD_LP20 77L /**< \brief SLCD signal: LP20 on PC13 mux B */ +#define MUX_PC13B_SLCD_LP20 1L +#define PINMUX_PC13B_SLCD_LP20 ((PIN_PC13B_SLCD_LP20 << 16) | MUX_PC13B_SLCD_LP20) +#define PORT_PC13B_SLCD_LP20 (1ul << 13) +#define PIN_PB11B_SLCD_LP21 43L /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 1L +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (1ul << 11) +#define PIN_PB12B_SLCD_LP22 44L /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 1L +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (1ul << 12) +#define PIN_PB13B_SLCD_LP23 45L /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 1L +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (1ul << 13) +#define PIN_PB14B_SLCD_LP24 46L /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 1L +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (1ul << 14) +#define PIN_PB15B_SLCD_LP25 47L /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 1L +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (1ul << 15) +#define PIN_PC14B_SLCD_LP26 78L /**< \brief SLCD signal: LP26 on PC14 mux B */ +#define MUX_PC14B_SLCD_LP26 1L +#define PINMUX_PC14B_SLCD_LP26 ((PIN_PC14B_SLCD_LP26 << 16) | MUX_PC14B_SLCD_LP26) +#define PORT_PC14B_SLCD_LP26 (1ul << 14) +#define PIN_PC15B_SLCD_LP27 79L /**< \brief SLCD signal: LP27 on PC15 mux B */ +#define MUX_PC15B_SLCD_LP27 1L +#define PINMUX_PC15B_SLCD_LP27 ((PIN_PC15B_SLCD_LP27 << 16) | MUX_PC15B_SLCD_LP27) +#define PORT_PC15B_SLCD_LP27 (1ul << 15) +#define PIN_PA12B_SLCD_LP28 12L /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 1L +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (1ul << 12) +#define PIN_PA13B_SLCD_LP29 13L /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 1L +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (1ul << 13) +#define PIN_PA14B_SLCD_LP30 14L /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 1L +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (1ul << 14) +#define PIN_PA15B_SLCD_LP31 15L /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 1L +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (1ul << 15) +#define PIN_PA16B_SLCD_LP32 16L /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 1L +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (1ul << 16) +#define PIN_PA17B_SLCD_LP33 17L /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 1L +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (1ul << 17) +#define PIN_PA18B_SLCD_LP34 18L /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 1L +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (1ul << 18) +#define PIN_PA19B_SLCD_LP35 19L /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 1L +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (1ul << 19) +#define PIN_PC16B_SLCD_LP36 80L /**< \brief SLCD signal: LP36 on PC16 mux B */ +#define MUX_PC16B_SLCD_LP36 1L +#define PINMUX_PC16B_SLCD_LP36 ((PIN_PC16B_SLCD_LP36 << 16) | MUX_PC16B_SLCD_LP36) +#define PORT_PC16B_SLCD_LP36 (1ul << 16) +#define PIN_PC17B_SLCD_LP37 81L /**< \brief SLCD signal: LP37 on PC17 mux B */ +#define MUX_PC17B_SLCD_LP37 1L +#define PINMUX_PC17B_SLCD_LP37 ((PIN_PC17B_SLCD_LP37 << 16) | MUX_PC17B_SLCD_LP37) +#define PORT_PC17B_SLCD_LP37 (1ul << 17) +#define PIN_PC18B_SLCD_LP38 82L /**< \brief SLCD signal: LP38 on PC18 mux B */ +#define MUX_PC18B_SLCD_LP38 1L +#define PINMUX_PC18B_SLCD_LP38 ((PIN_PC18B_SLCD_LP38 << 16) | MUX_PC18B_SLCD_LP38) +#define PORT_PC18B_SLCD_LP38 (1ul << 18) +#define PIN_PC19B_SLCD_LP39 83L /**< \brief SLCD signal: LP39 on PC19 mux B */ +#define MUX_PC19B_SLCD_LP39 1L +#define PINMUX_PC19B_SLCD_LP39 ((PIN_PC19B_SLCD_LP39 << 16) | MUX_PC19B_SLCD_LP39) +#define PORT_PC19B_SLCD_LP39 (1ul << 19) +#define PIN_PC20B_SLCD_LP40 84L /**< \brief SLCD signal: LP40 on PC20 mux B */ +#define MUX_PC20B_SLCD_LP40 1L +#define PINMUX_PC20B_SLCD_LP40 ((PIN_PC20B_SLCD_LP40 << 16) | MUX_PC20B_SLCD_LP40) +#define PORT_PC20B_SLCD_LP40 (1ul << 20) +#define PIN_PC21B_SLCD_LP41 85L /**< \brief SLCD signal: LP41 on PC21 mux B */ +#define MUX_PC21B_SLCD_LP41 1L +#define PINMUX_PC21B_SLCD_LP41 ((PIN_PC21B_SLCD_LP41 << 16) | MUX_PC21B_SLCD_LP41) +#define PORT_PC21B_SLCD_LP41 (1ul << 21) +#define PIN_PB16B_SLCD_LP42 48L /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 1L +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (1ul << 16) +#define PIN_PB17B_SLCD_LP43 49L /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 1L +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (1ul << 17) +#define PIN_PB18B_SLCD_LP44 50L /**< \brief SLCD signal: LP44 on PB18 mux B */ +#define MUX_PB18B_SLCD_LP44 1L +#define PINMUX_PB18B_SLCD_LP44 ((PIN_PB18B_SLCD_LP44 << 16) | MUX_PB18B_SLCD_LP44) +#define PORT_PB18B_SLCD_LP44 (1ul << 18) +#define PIN_PB19B_SLCD_LP45 51L /**< \brief SLCD signal: LP45 on PB19 mux B */ +#define MUX_PB19B_SLCD_LP45 1L +#define PINMUX_PB19B_SLCD_LP45 ((PIN_PB19B_SLCD_LP45 << 16) | MUX_PB19B_SLCD_LP45) +#define PORT_PB19B_SLCD_LP45 (1ul << 19) +#define PIN_PB20B_SLCD_LP46 52L /**< \brief SLCD signal: LP46 on PB20 mux B */ +#define MUX_PB20B_SLCD_LP46 1L +#define PINMUX_PB20B_SLCD_LP46 ((PIN_PB20B_SLCD_LP46 << 16) | MUX_PB20B_SLCD_LP46) +#define PORT_PB20B_SLCD_LP46 (1ul << 20) +#define PIN_PB21B_SLCD_LP47 53L /**< \brief SLCD signal: LP47 on PB21 mux B */ +#define MUX_PB21B_SLCD_LP47 1L +#define PINMUX_PB21B_SLCD_LP47 ((PIN_PB21B_SLCD_LP47 << 16) | MUX_PB21B_SLCD_LP47) +#define PORT_PB21B_SLCD_LP47 (1ul << 21) +#define PIN_PA20B_SLCD_LP48 20L /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 1L +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (1ul << 20) +#define PIN_PA21B_SLCD_LP49 21L /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 1L +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (1ul << 21) +#define PIN_PA22B_SLCD_LP50 22L /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 1L +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (1ul << 22) +#define PIN_PA23B_SLCD_LP51 23L /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 1L +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (1ul << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 8L +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (1ul << 0) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 8L +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (1ul << 1) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PC27I_CCL_IN4 91L /**< \brief CCL signal: IN4 on PC27 mux I */ +#define MUX_PC27I_CCL_IN4 8L +#define PINMUX_PC27I_CCL_IN4 ((PIN_PC27I_CCL_IN4 << 16) | MUX_PC27I_CCL_IN4) +#define PORT_PC27I_CCL_IN4 (1ul << 27) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PC28I_CCL_IN5 92L /**< \brief CCL signal: IN5 on PC28 mux I */ +#define MUX_PC28I_CCL_IN5 8L +#define PINMUX_PC28I_CCL_IN5 ((PIN_PC28I_CCL_IN5 << 16) | MUX_PC28I_CCL_IN5) +#define PORT_PC28I_CCL_IN5 (1ul << 28) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 8L +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (1ul << 6) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 8L +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (1ul << 7) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 8L +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (1ul << 14) +#define PIN_PC20I_CCL_IN9 84L /**< \brief CCL signal: IN9 on PC20 mux I */ +#define MUX_PC20I_CCL_IN9 8L +#define PINMUX_PC20I_CCL_IN9 ((PIN_PC20I_CCL_IN9 << 16) | MUX_PC20I_CCL_IN9) +#define PORT_PC20I_CCL_IN9 (1ul << 20) +#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 8L +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (1ul << 15) +#define PIN_PC21I_CCL_IN10 85L /**< \brief CCL signal: IN10 on PC21 mux I */ +#define MUX_PC21I_CCL_IN10 8L +#define PINMUX_PC21I_CCL_IN10 ((PIN_PC21I_CCL_IN10 << 16) | MUX_PC21I_CCL_IN10) +#define PORT_PC21I_CCL_IN10 (1ul << 21) +#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 8L +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (1ul << 16) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) +#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 8L +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (1ul << 17) + +#endif /* _SAML22N18A_PIO_ */ diff --git a/Sensor Watch Starter Project/include/saml22.h b/Sensor Watch Starter Project/include/saml22.h new file mode 100755 index 00000000..c8f5dc6c --- /dev/null +++ b/Sensor Watch Starter Project/include/saml22.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Top header file for SAML22 + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_ +#define _SAML22_ + +/** + * \defgroup SAML22_definitions SAML22 Device Definitions + * \brief SAML22 CMSIS Definitions. + */ + +#if defined(__SAML22G16A__) || defined(__ATSAML22G16A__) + #include "saml22g16a.h" +#elif defined(__SAML22G17A__) || defined(__ATSAML22G17A__) + #include "saml22g17a.h" +#elif defined(__SAML22G18A__) || defined(__ATSAML22G18A__) + #include "saml22g18a.h" +#elif defined(__SAML22J16A__) || defined(__ATSAML22J16A__) + #include "saml22j16a.h" +#elif defined(__SAML22J17A__) || defined(__ATSAML22J17A__) + #include "saml22j17a.h" +#elif defined(__SAML22J18A__) || defined(__ATSAML22J18A__) + #include "saml22j18a.h" +#elif defined(__SAML22N16A__) || defined(__ATSAML22N16A__) + #include "saml22n16a.h" +#elif defined(__SAML22N17A__) || defined(__ATSAML22N17A__) + #include "saml22n17a.h" +#elif defined(__SAML22N18A__) || defined(__ATSAML22N18A__) + #include "saml22n18a.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAML22_ */ diff --git a/Sensor Watch Starter Project/include/saml22g16a.h b/Sensor Watch Starter Project/include/saml22g16a.h new file mode 100755 index 00000000..f6fcb548 --- /dev/null +++ b/Sensor Watch Starter Project/include/saml22g16a.h @@ -0,0 +1,603 @@ +/** + * \file + * + * \brief Header file for SAML22G16A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G16A_ +#define _SAML22G16A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22G16A_definitions SAML22G16A definitions + * This file defines all structures and symbols for SAML22G16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML22G16A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22G16A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML22G16A Main Clock (MCLK) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML22G16A 32k Oscillators Control (OSC32KCTRL) */ + OSCCTRL_IRQn = 0, /**< 0 SAML22G16A Oscillators Control (OSCCTRL) */ + PAC_IRQn = 0, /**< 0 SAML22G16A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML22G16A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML22G16A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML22G16A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML22G16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22G16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22G16A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22G16A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22G16A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22G16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22G16A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22G16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22G16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22G16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22G16A Serial Communication Interface 2 (SERCOM2) */ + TCC0_IRQn = 15, /**< 15 SAML22G16A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22G16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22G16A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22G16A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22G16A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22G16A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22G16A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22G16A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22G16A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22G16A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22G16A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnReserved12; + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TAL 12 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SLCD (0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM_INST_NUM 3 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22g16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x10000UL /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x2000UL /* 8 kB */ + +#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ +#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ +#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ +#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ +#define PPB_ADDR (0xE0000000u) /**< PPB base address */ + +#define DSU_DID_RESETVALUE 0x1082000CUL +#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22G16A_H */ diff --git a/Sensor Watch Starter Project/include/saml22g17a.h b/Sensor Watch Starter Project/include/saml22g17a.h new file mode 100755 index 00000000..4641cadd --- /dev/null +++ b/Sensor Watch Starter Project/include/saml22g17a.h @@ -0,0 +1,603 @@ +/** + * \file + * + * \brief Header file for SAML22G17A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G17A_ +#define _SAML22G17A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22G17A_definitions SAML22G17A definitions + * This file defines all structures and symbols for SAML22G17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML22G17A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22G17A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML22G17A Main Clock (MCLK) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML22G17A 32k Oscillators Control (OSC32KCTRL) */ + OSCCTRL_IRQn = 0, /**< 0 SAML22G17A Oscillators Control (OSCCTRL) */ + PAC_IRQn = 0, /**< 0 SAML22G17A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML22G17A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML22G17A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML22G17A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML22G17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22G17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22G17A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22G17A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22G17A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22G17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22G17A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22G17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22G17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22G17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22G17A Serial Communication Interface 2 (SERCOM2) */ + TCC0_IRQn = 15, /**< 15 SAML22G17A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22G17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22G17A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22G17A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22G17A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22G17A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22G17A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22G17A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22G17A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22G17A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22G17A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnReserved12; + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TAL 12 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SLCD (0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM_INST_NUM 3 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22g17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x20000UL /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x4000UL /* 16 kB */ + +#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ +#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ +#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ +#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ +#define PPB_ADDR (0xE0000000u) /**< PPB base address */ + +#define DSU_DID_RESETVALUE 0x1082000BUL +#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22G17A_H */ diff --git a/Sensor Watch Starter Project/include/saml22g18a.h b/Sensor Watch Starter Project/include/saml22g18a.h new file mode 100755 index 00000000..7204a38c --- /dev/null +++ b/Sensor Watch Starter Project/include/saml22g18a.h @@ -0,0 +1,603 @@ +/** + * \file + * + * \brief Header file for SAML22G18A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G18A_ +#define _SAML22G18A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22G18A_definitions SAML22G18A definitions + * This file defines all structures and symbols for SAML22G18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML22G18A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22G18A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML22G18A Main Clock (MCLK) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML22G18A 32k Oscillators Control (OSC32KCTRL) */ + OSCCTRL_IRQn = 0, /**< 0 SAML22G18A Oscillators Control (OSCCTRL) */ + PAC_IRQn = 0, /**< 0 SAML22G18A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML22G18A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML22G18A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML22G18A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML22G18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22G18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22G18A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22G18A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22G18A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22G18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22G18A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22G18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22G18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22G18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22G18A Serial Communication Interface 2 (SERCOM2) */ + TCC0_IRQn = 15, /**< 15 SAML22G18A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22G18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22G18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22G18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22G18A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22G18A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22G18A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22G18A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22G18A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22G18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22G18A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnReserved12; + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TAL 12 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SLCD (0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM_INST_NUM 3 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22g18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x40000UL /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x8000UL /* 32 kB */ + +#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ +#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ +#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ +#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ +#define PPB_ADDR (0xE0000000u) /**< PPB base address */ + +#define DSU_DID_RESETVALUE 0x1082000AUL +#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22G18A_H */ diff --git a/Sensor Watch Starter Project/include/saml22j16a.h b/Sensor Watch Starter Project/include/saml22j16a.h new file mode 100755 index 00000000..6a530585 --- /dev/null +++ b/Sensor Watch Starter Project/include/saml22j16a.h @@ -0,0 +1,609 @@ +/** + * \file + * + * \brief Header file for SAML22J16A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J16A_ +#define _SAML22J16A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22J16A_definitions SAML22J16A definitions + * This file defines all structures and symbols for SAML22J16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML22J16A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22J16A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML22J16A Main Clock (MCLK) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML22J16A 32k Oscillators Control (OSC32KCTRL) */ + OSCCTRL_IRQn = 0, /**< 0 SAML22J16A Oscillators Control (OSCCTRL) */ + PAC_IRQn = 0, /**< 0 SAML22J16A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML22J16A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML22J16A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML22J16A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML22J16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22J16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22J16A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22J16A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22J16A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22J16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22J16A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22J16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22J16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22J16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22J16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22J16A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAML22J16A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22J16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22J16A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22J16A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22J16A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22J16A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22J16A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22J16A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22J16A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22J16A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22J16A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TAL 12 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SLCD (0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22j16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x10000UL /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x2000UL /* 8 kB */ + +#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ +#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ +#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ +#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ +#define PPB_ADDR (0xE0000000u) /**< PPB base address */ + +#define DSU_DID_RESETVALUE 0x10820007UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22J16A_H */ diff --git a/Sensor Watch Starter Project/include/saml22j17a.h b/Sensor Watch Starter Project/include/saml22j17a.h new file mode 100755 index 00000000..fb6cb4e7 --- /dev/null +++ b/Sensor Watch Starter Project/include/saml22j17a.h @@ -0,0 +1,609 @@ +/** + * \file + * + * \brief Header file for SAML22J17A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J17A_ +#define _SAML22J17A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22J17A_definitions SAML22J17A definitions + * This file defines all structures and symbols for SAML22J17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML22J17A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22J17A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML22J17A Main Clock (MCLK) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML22J17A 32k Oscillators Control (OSC32KCTRL) */ + OSCCTRL_IRQn = 0, /**< 0 SAML22J17A Oscillators Control (OSCCTRL) */ + PAC_IRQn = 0, /**< 0 SAML22J17A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML22J17A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML22J17A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML22J17A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML22J17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22J17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22J17A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22J17A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22J17A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22J17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22J17A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22J17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22J17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22J17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22J17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22J17A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAML22J17A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22J17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22J17A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22J17A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22J17A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22J17A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22J17A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22J17A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22J17A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22J17A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22J17A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TAL 12 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SLCD (0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22j17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x20000UL /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x4000UL /* 16 kB */ + +#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ +#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ +#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ +#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ +#define PPB_ADDR (0xE0000000u) /**< PPB base address */ + +#define DSU_DID_RESETVALUE 0x10820006UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22J17A_H */ diff --git a/Sensor Watch Starter Project/include/saml22j18a.h b/Sensor Watch Starter Project/include/saml22j18a.h new file mode 100755 index 00000000..c1fdc2da --- /dev/null +++ b/Sensor Watch Starter Project/include/saml22j18a.h @@ -0,0 +1,609 @@ +/** + * \file + * + * \brief Header file for SAML22J18A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J18A_ +#define _SAML22J18A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22J18A_definitions SAML22J18A definitions + * This file defines all structures and symbols for SAML22J18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML22J18A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22J18A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML22J18A Main Clock (MCLK) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML22J18A 32k Oscillators Control (OSC32KCTRL) */ + OSCCTRL_IRQn = 0, /**< 0 SAML22J18A Oscillators Control (OSCCTRL) */ + PAC_IRQn = 0, /**< 0 SAML22J18A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML22J18A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML22J18A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML22J18A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML22J18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22J18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22J18A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22J18A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22J18A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22J18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22J18A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22J18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22J18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22J18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22J18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22J18A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAML22J18A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22J18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22J18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22J18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22J18A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22J18A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22J18A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22J18A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22J18A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22J18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22J18A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TAL 12 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SLCD (0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22j18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x40000UL /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x8000UL /* 32 kB */ + +#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ +#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ +#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ +#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ +#define PPB_ADDR (0xE0000000u) /**< PPB base address */ + +#define DSU_DID_RESETVALUE 0x10820005UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22J18A_H */ diff --git a/Sensor Watch Starter Project/include/saml22n16a.h b/Sensor Watch Starter Project/include/saml22n16a.h new file mode 100755 index 00000000..5e9f1282 --- /dev/null +++ b/Sensor Watch Starter Project/include/saml22n16a.h @@ -0,0 +1,621 @@ +/** + * \file + * + * \brief Header file for SAML22N16A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N16A_ +#define _SAML22N16A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22N16A_definitions SAML22N16A definitions + * This file defines all structures and symbols for SAML22N16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML22N16A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22N16A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML22N16A Main Clock (MCLK) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML22N16A 32k Oscillators Control (OSC32KCTRL) */ + OSCCTRL_IRQn = 0, /**< 0 SAML22N16A Oscillators Control (OSCCTRL) */ + PAC_IRQn = 0, /**< 0 SAML22N16A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML22N16A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML22N16A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML22N16A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML22N16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22N16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22N16A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22N16A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22N16A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22N16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22N16A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22N16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22N16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22N16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22N16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22N16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAML22N16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAML22N16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAML22N16A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22N16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22N16A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22N16A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22N16A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22N16A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22N16A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22N16A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22N16A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22N16A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22N16A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TAL 12 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SLCD (0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22n16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x10000UL /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x2000UL /* 8 kB */ + +#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ +#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ +#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ +#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ +#define PPB_ADDR (0xE0000000u) /**< PPB base address */ + +#define DSU_DID_RESETVALUE 0x10820002UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22N16A_H */ diff --git a/Sensor Watch Starter Project/include/saml22n17a.h b/Sensor Watch Starter Project/include/saml22n17a.h new file mode 100755 index 00000000..e550b4c9 --- /dev/null +++ b/Sensor Watch Starter Project/include/saml22n17a.h @@ -0,0 +1,621 @@ +/** + * \file + * + * \brief Header file for SAML22N17A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N17A_ +#define _SAML22N17A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22N17A_definitions SAML22N17A definitions + * This file defines all structures and symbols for SAML22N17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML22N17A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22N17A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML22N17A Main Clock (MCLK) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML22N17A 32k Oscillators Control (OSC32KCTRL) */ + OSCCTRL_IRQn = 0, /**< 0 SAML22N17A Oscillators Control (OSCCTRL) */ + PAC_IRQn = 0, /**< 0 SAML22N17A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML22N17A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML22N17A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML22N17A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML22N17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22N17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22N17A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22N17A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22N17A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22N17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22N17A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22N17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22N17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22N17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22N17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22N17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAML22N17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAML22N17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAML22N17A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22N17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22N17A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22N17A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22N17A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22N17A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22N17A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22N17A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22N17A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22N17A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22N17A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TAL 12 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SLCD (0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22n17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x20000UL /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x4000UL /* 16 kB */ + +#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ +#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ +#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ +#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ +#define PPB_ADDR (0xE0000000u) /**< PPB base address */ + +#define DSU_DID_RESETVALUE 0x10820001UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22N17A_H */ diff --git a/Sensor Watch Starter Project/include/saml22n18a.h b/Sensor Watch Starter Project/include/saml22n18a.h new file mode 100755 index 00000000..e1592c0c --- /dev/null +++ b/Sensor Watch Starter Project/include/saml22n18a.h @@ -0,0 +1,621 @@ +/** + * \file + * + * \brief Header file for SAML22N18A + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N18A_ +#define _SAML22N18A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22N18A_definitions SAML22N18A definitions + * This file defines all structures and symbols for SAML22N18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML22N18A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22N18A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML22N18A Main Clock (MCLK) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML22N18A 32k Oscillators Control (OSC32KCTRL) */ + OSCCTRL_IRQn = 0, /**< 0 SAML22N18A Oscillators Control (OSCCTRL) */ + PAC_IRQn = 0, /**< 0 SAML22N18A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML22N18A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML22N18A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML22N18A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML22N18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22N18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22N18A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22N18A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22N18A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22N18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22N18A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22N18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22N18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22N18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22N18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22N18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAML22N18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAML22N18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAML22N18A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22N18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22N18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22N18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22N18A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22N18A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22N18A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22N18A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22N18A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22N18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22N18A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TAL 12 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SLCD (0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40003000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22n18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x40000UL /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x8000UL /* 32 kB */ + +#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ +#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ +#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ +#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ +#define PPB_ADDR (0xE0000000u) /**< PPB base address */ + +#define DSU_DID_RESETVALUE 0x10820000UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22N18A_H */ diff --git a/Sensor Watch Starter Project/linker/saml22j18.ld b/Sensor Watch Starter Project/linker/saml22j18.ld new file mode 100755 index 00000000..a68c3b14 --- /dev/null +++ b/Sensor Watch Starter Project/linker/saml22j18.ld @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2014-2016, Alex Taradov + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000+0x2000, LENGTH = 0x00040000-0x2000 /* 256k */ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32k */ +} + +__top_flash = ORIGIN(flash) + LENGTH(flash); +__top_ram = ORIGIN(ram) + LENGTH(ram); + +ENTRY(irq_handler_reset) + +SECTIONS +{ + .text : ALIGN(4) + { + FILL(0xff) + KEEP(*(.vectors)) + *(.text*) + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + } > flash + + . = ALIGN(4); + _etext = .; + + .uninit_RESERVED : ALIGN(4) + { + KEEP(*(.bss.$RESERVED*)) + } > ram + + .data : ALIGN(4) + { + FILL(0xff) + _data = .; + *(.ramfunc .ramfunc.*); + *(vtable) + *(.data*) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : ALIGN(4) + { + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + PROVIDE(_end = .); + } > ram + + PROVIDE(_stack_top = __top_ram - 0); +} diff --git a/Sensor Watch Starter Project/main.c b/Sensor Watch Starter Project/main.c new file mode 100755 index 00000000..844b3d88 --- /dev/null +++ b/Sensor Watch Starter Project/main.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2014-2017, Alex Taradov + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +//----------------------------------------------------------------------------- +#include +#include +#include +#include +#include "saml22.h" +#include "hal_gpio.h" + +//----------------------------------------------------------------------------- +#define PERIOD_FAST 100 +#define PERIOD_SLOW 500 + +HAL_GPIO_PIN(LED, A, 21) +HAL_GPIO_PIN(BUTTON, A, 30) +HAL_GPIO_PIN(UART_TX, A, 22) +HAL_GPIO_PIN(UART_RX, A, 23) + +//----------------------------------------------------------------------------- +static void timer_set_period(uint16_t i) +{ + TC3->COUNT16.CC[0].reg = (F_CPU / 1000ul / 256) * i; + TC3->COUNT16.COUNT.reg = 0; +} + +//----------------------------------------------------------------------------- +void irq_handler_tc3(void) +{ + if (TC3->COUNT16.INTFLAG.reg & TC_INTFLAG_MC(1)) + { + HAL_GPIO_LED_toggle(); + TC3->COUNT16.INTFLAG.reg = TC_INTFLAG_MC(1); + } +} + +//----------------------------------------------------------------------------- +static void timer_init(void) +{ + MCLK->APBCMASK.reg |= MCLK_APBCMASK_TC3; + + GCLK->PCHCTRL[TC3_GCLK_ID].reg = GCLK_PCHCTRL_GEN(0) | GCLK_PCHCTRL_CHEN; + while (0 == (GCLK->PCHCTRL[TC3_GCLK_ID].reg & GCLK_PCHCTRL_CHEN)); + + TC3->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 | TC_CTRLA_PRESCALER(6/*DIV256*/) | + TC_CTRLA_PRESCSYNC_RESYNC; + + TC3->COUNT16.WAVE.reg = TC_WAVE_WAVEGEN_MFRQ; + + TC3->COUNT16.COUNT.reg = 0; + + timer_set_period(PERIOD_SLOW); + + TC3->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; + + TC3->COUNT16.INTENSET.reg = TC_INTENSET_MC(1); + NVIC_EnableIRQ(TC3_IRQn); +} + +//----------------------------------------------------------------------------- +static void uart_init(uint32_t baud) +{ + uint64_t br = (uint64_t)65536 * (F_CPU - 16 * baud) / F_CPU; + + HAL_GPIO_UART_TX_out(); + HAL_GPIO_UART_TX_pmuxen(HAL_GPIO_PMUX_C); + HAL_GPIO_UART_RX_in(); + HAL_GPIO_UART_RX_pmuxen(HAL_GPIO_PMUX_C); + + MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0; + + GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN(0) | GCLK_PCHCTRL_CHEN; + while (0 == (GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg & GCLK_PCHCTRL_CHEN)); + + SERCOM0->USART.CTRLA.reg = + SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE(1/*USART_INT_CLK*/) | + SERCOM_USART_CTRLA_RXPO(3/*PAD3*/) | SERCOM_USART_CTRLA_TXPO(1/*PAD2*/); + + SERCOM0->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN | + SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/); + + SERCOM0->USART.BAUD.reg = (uint16_t)br; + + SERCOM0->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; +} + +//----------------------------------------------------------------------------- +static void uart_putc(char c) +{ + while (!(SERCOM0->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)); + SERCOM0->USART.DATA.reg = c; +} + +//----------------------------------------------------------------------------- +static void uart_puts(char *s) +{ + while (*s) + uart_putc(*s++); +} + +//----------------------------------------------------------------------------- +static void sys_init(void) +{ + // Switch to 16MHz clock (disable prescaler) + OSCCTRL->OSC16MCTRL.reg = OSCCTRL_OSC16MCTRL_ENABLE | OSCCTRL_OSC16MCTRL_FSEL_16; + + // Switch to the highest performance level + PM->INTFLAG.reg = PM_INTFLAG_PLRDY; + PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2_Val; + while (!PM->INTFLAG.reg); +} + +//----------------------------------------------------------------------------- +int main(void) +{ + uint32_t cnt = 0; + bool fast = false; + + sys_init(); + timer_init(); + uart_init(115200); + + uart_puts("\r\nHello, world!\r\n"); + + HAL_GPIO_LED_out(); + HAL_GPIO_LED_clr(); + + HAL_GPIO_BUTTON_in(); + HAL_GPIO_BUTTON_pullup(); + + while (1) + { + if (HAL_GPIO_BUTTON_read()) + cnt = 0; + else if (cnt < 5001) + cnt++; + + if (5000 == cnt) + { + fast = !fast; + timer_set_period(fast ? PERIOD_FAST : PERIOD_SLOW); + uart_putc('.'); + } + } + + return 0; +} diff --git a/Sensor Watch Starter Project/make/.gitignore b/Sensor Watch Starter Project/make/.gitignore new file mode 100755 index 00000000..3722ac63 --- /dev/null +++ b/Sensor Watch Starter Project/make/.gitignore @@ -0,0 +1 @@ +build/ diff --git a/Sensor Watch Starter Project/make/Makefile b/Sensor Watch Starter Project/make/Makefile new file mode 100755 index 00000000..034bd4df --- /dev/null +++ b/Sensor Watch Starter Project/make/Makefile @@ -0,0 +1,84 @@ +############################################################################## +BUILD = build +BIN = watch + +############################################################################## +.PHONY: all directory clean size + +CC = arm-none-eabi-gcc +OBJCOPY = arm-none-eabi-objcopy +SIZE = arm-none-eabi-size +UF2 = python uf2conv.py + +ifeq ($(OS), Windows_NT) + MKDIR = gmkdir +else + MKDIR = mkdir +endif + +CFLAGS += -W -Wall --std=gnu99 -Os +CFLAGS += -fno-diagnostics-show-caret +CFLAGS += -fdata-sections -ffunction-sections +CFLAGS += -funsigned-char -funsigned-bitfields +CFLAGS += -mcpu=cortex-m0plus -mthumb +CFLAGS += -MD -MP -MT $(BUILD)/$(*F).o -MF $(BUILD)/$(@F).d + +LDFLAGS += -mcpu=cortex-m0plus -mthumb +LDFLAGS += -Wl,--gc-sections +LDFLAGS += -Wl,--script=../linker/saml22j18.ld + +INCLUDES += \ + -I../include \ + -I.. + +SRCS += \ + ../main.c \ + ../startup_saml22.c + +DEFINES += \ + -D__SAML22J18A__ \ + -DDONT_USE_CMSIS_INIT \ + -DF_CPU=16000000 + +CFLAGS += $(INCLUDES) $(DEFINES) + +OBJS = $(addprefix $(BUILD)/, $(notdir %/$(subst .c,.o, $(SRCS)))) + +all: directory $(BUILD)/$(BIN).elf $(BUILD)/$(BIN).hex $(BUILD)/$(BIN).bin $(BUILD)/$(BIN).uf2 size + +$(BUILD)/$(BIN).elf: $(OBJS) + @echo LD $@ + @$(CC) $(LDFLAGS) $(OBJS) $(LIBS) -o $@ + +$(BUILD)/$(BIN).hex: $(BUILD)/$(BIN).elf + @echo OBJCOPY $@ + @$(OBJCOPY) -O ihex $^ $@ + +$(BUILD)/$(BIN).bin: $(BUILD)/$(BIN).elf + @echo OBJCOPY $@ + @$(OBJCOPY) -O binary $^ $@ + +$(BUILD)/$(BIN).uf2: $(BUILD)/$(BIN).bin + @echo UF2CONV $@ + @$(UF2) $^ -co $@ + +install: + @$(UF2) -D $(BUILD)/$(BIN).uf2 + +%.o: + @echo CC $@ + @$(CC) $(CFLAGS) $(filter %/$(subst .o,.c,$(notdir $@)), $(SRCS)) -c -o $@ + +directory: + @$(MKDIR) -p $(BUILD) + +size: $(BUILD)/$(BIN).elf + @echo size: + @$(SIZE) -t $^ + +clean: + @echo clean + @-rm -rf $(BUILD) + +-include $(wildcard $(BUILD)/*.d) + diff --git a/Sensor Watch Starter Project/make/uf2conv.py b/Sensor Watch Starter Project/make/uf2conv.py new file mode 100644 index 00000000..849e6499 --- /dev/null +++ b/Sensor Watch Starter Project/make/uf2conv.py @@ -0,0 +1,302 @@ +#!/usr/bin/env python3 +import sys +import struct +import subprocess +import re +import os +import os.path +import argparse + + +UF2_MAGIC_START0 = 0x0A324655 # "UF2\n" +UF2_MAGIC_START1 = 0x9E5D5157 # Randomly selected +UF2_MAGIC_END = 0x0AB16F30 # Ditto + +families = { + 'SAMD21': 0x68ed2b88, + 'SAML21': 0x1851780a, + 'SAML22': 0x2c29472f, + 'SAMD51': 0x55114460, + 'NRF52': 0x1b57745f, + 'STM32F1': 0x5ee21072, + 'STM32F4': 0x57755a57, + 'ATMEGA32': 0x16573617, + 'MIMXRT10XX': 0x4FB2D5BD +} + +INFO_FILE = "/INFO_UF2.TXT" + +appstartaddr = 0x2000 +familyid = 0x0 + + +def is_uf2(buf): + w = struct.unpack(" 476: + assert False, "Invalid UF2 data size at " + ptr + newaddr = hd[3] + if curraddr == None: + appstartaddr = newaddr + curraddr = newaddr + padding = newaddr - curraddr + if padding < 0: + assert False, "Block out of order at " + ptr + if padding > 10*1024*1024: + assert False, "More than 10M of padding needed at " + ptr + if padding % 4 != 0: + assert False, "Non-word padding size at " + ptr + while padding > 0: + padding -= 4 + outp += b"\x00\x00\x00\x00" + outp += block[32 : 32 + datalen] + curraddr = newaddr + datalen + return outp + +def convert_to_carray(file_content): + outp = "const unsigned char bindata[] __attribute__((aligned(16))) = {" + for i in range(len(file_content)): + if i % 16 == 0: + outp += "\n" + outp += "0x%02x, " % ord(file_content[i]) + outp += "\n};\n" + return outp + +def convert_to_uf2(file_content): + global familyid + datapadding = b"" + while len(datapadding) < 512 - 256 - 32 - 4: + datapadding += b"\x00\x00\x00\x00" + numblocks = (len(file_content) + 255) // 256 + outp = b"" + for blockno in range(numblocks): + ptr = 256 * blockno + chunk = file_content[ptr:ptr + 256] + flags = 0x0 + if familyid: + flags |= 0x2000 + hd = struct.pack(b"= 3 and words[1] == "2" and words[2] == "FAT": + drives.append(words[0]) + else: + rootpath = "/media" + if sys.platform == "darwin": + rootpath = "/Volumes" + elif sys.platform == "linux": + tmp = rootpath + "/" + os.environ["USER"] + if os.path.isdir(tmp): + rootpath = tmp + for d in os.listdir(rootpath): + drives.append(os.path.join(rootpath, d)) + + + def has_info(d): + try: + return os.path.isfile(d + INFO_FILE) + except: + return False + + return list(filter(has_info, drives)) + + +def board_id(path): + with open(path + INFO_FILE, mode='r') as file: + file_content = file.read() + return re.search("Board-ID: ([^\r\n]*)", file_content).group(1) + + +def list_drives(): + for d in get_drives(): + print(d, board_id(d)) + + +def write_file(name, buf): + with open(name, "wb") as f: + f.write(buf) + print("Wrote %d bytes to %s" % (len(buf), name)) + + +def main(): + global appstartaddr, familyid + def error(msg): + print(msg) + sys.exit(1) + parser = argparse.ArgumentParser(description='Convert to UF2 or flash directly.') + parser.add_argument('input', metavar='INPUT', type=str, nargs='?', + help='input file (HEX, BIN or UF2)') + parser.add_argument('-b' , '--base', dest='base', type=str, + default="0x2000", + help='set base address of application for BIN format (default: 0x2000)') + parser.add_argument('-o' , '--output', metavar="FILE", dest='output', type=str, + help='write output to named file; defaults to "flash.uf2" or "flash.bin" where sensible') + parser.add_argument('-d' , '--device', dest="device_path", + help='select a device path to flash') + parser.add_argument('-l' , '--list', action='store_true', + help='list connected devices') + parser.add_argument('-c' , '--convert', action='store_true', + help='do not flash, just convert') + parser.add_argument('-D' , '--deploy', action='store_true', + help='just flash, do not convert') + parser.add_argument('-f' , '--family', dest='family', type=str, + default="0x0", + help='specify familyID - number or name (default: 0x0)') + parser.add_argument('-C' , '--carray', action='store_true', + help='convert binary file to a C array, not UF2') + args = parser.parse_args() + appstartaddr = int(args.base, 0) + + if args.family.upper() in families: + familyid = families[args.family.upper()] + else: + try: + familyid = int(args.family, 0) + except ValueError: + error("Family ID needs to be a number or one of: " + ", ".join(families.keys())) + + if args.list: + list_drives() + else: + if not args.input: + error("Need input file") + with open(args.input, mode='rb') as f: + inpbuf = f.read() + from_uf2 = is_uf2(inpbuf) + ext = "uf2" + if args.deploy: + outbuf = inpbuf + elif from_uf2: + outbuf = convert_from_uf2(inpbuf) + ext = "bin" + elif is_hex(inpbuf): + outbuf = convert_from_hex_to_uf2(inpbuf.decode("utf-8")) + elif args.carray: + outbuf = convert_to_carray(inpbuf) + ext = "h" + else: + outbuf = convert_to_uf2(inpbuf) + print("Converting to %s, output size: %d, start address: 0x%x" % + (ext, len(outbuf), appstartaddr)) + if args.convert or ext != "uf2": + drives = [] + if args.output == None: + args.output = "flash." + ext + else: + drives = get_drives() + + if args.output: + write_file(args.output, outbuf) + else: + if len(drives) == 0: + error("No drive to deploy.") + for d in drives: + print("Flashing %s (%s)" % (d, board_id(d))) + write_file(d + "/NEW.UF2", outbuf) + + +if __name__ == "__main__": + main() diff --git a/Sensor Watch Starter Project/startup_saml22.c b/Sensor Watch Starter Project/startup_saml22.c new file mode 100755 index 00000000..3941456b --- /dev/null +++ b/Sensor Watch Starter Project/startup_saml22.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2014-2017, Alex Taradov + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +//----------------------------------------------------------------------------- +#include "saml22.h" + +//----------------------------------------------------------------------------- +#define DUMMY __attribute__ ((weak, alias ("irq_handler_dummy"))) + +//----------------------------------------------------------------------------- +void irq_handler_reset(void); +DUMMY void irq_handler_nmi(void); +DUMMY void irq_handler_hard_fault(void); +DUMMY void irq_handler_sv_call(void); +DUMMY void irq_handler_pend_sv(void); +DUMMY void irq_handler_sys_tick(void); + +DUMMY void irq_handler_system(void); +DUMMY void irq_handler_wdt(void); +DUMMY void irq_handler_rtc(void); +DUMMY void irq_handler_eic(void); +DUMMY void irq_handler_freqm(void); +DUMMY void irq_handler_usb(void); +DUMMY void irq_handler_nvmctrl(void); +DUMMY void irq_handler_dmac(void); +DUMMY void irq_handler_evsys(void); +DUMMY void irq_handler_sercom0(void); +DUMMY void irq_handler_sercom1(void); +DUMMY void irq_handler_sercom2(void); +DUMMY void irq_handler_sercom3(void); +DUMMY void irq_handler_sercom4(void); +DUMMY void irq_handler_sercom5(void); +DUMMY void irq_handler_tcc0(void); +DUMMY void irq_handler_tc0(void); +DUMMY void irq_handler_tc1(void); +DUMMY void irq_handler_tc2(void); +DUMMY void irq_handler_tc3(void); +DUMMY void irq_handler_adc(void); +DUMMY void irq_handler_ac(void); +DUMMY void irq_handler_ptc(void); +DUMMY void irq_handler_slcd(void); +DUMMY void irq_handler_aes(void); +DUMMY void irq_handler_trng(void); + +extern int main(void); + +extern void _stack_top(void); +extern unsigned int _etext; +extern unsigned int _data; +extern unsigned int _edata; +extern unsigned int _bss; +extern unsigned int _ebss; + +//----------------------------------------------------------------------------- +__attribute__ ((used, section(".vectors"))) +void (* const vectors[])(void) = +{ + &_stack_top, // 0 - Initial Stack Pointer Value + + // Cortex-M0+ handlers + irq_handler_reset, // 1 - Reset + irq_handler_nmi, // 2 - NMI + irq_handler_hard_fault, // 3 - Hard Fault + 0, // 4 - Reserved + 0, // 5 - Reserved + 0, // 6 - Reserved + 0, // 7 - Reserved + 0, // 8 - Reserved + 0, // 9 - Reserved + 0, // 10 - Reserved + irq_handler_sv_call, // 11 - SVCall + 0, // 12 - Reserved + 0, // 13 - Reserved + irq_handler_pend_sv, // 14 - PendSV + irq_handler_sys_tick, // 15 - SysTick + + // Peripheral handlers + irq_handler_system, // 0 - System Controller + irq_handler_wdt, // 1 - Watchdog Timer + irq_handler_rtc, // 2 - Real-Time Counter + irq_handler_eic, // 3 - External Interrupt Controller + irq_handler_freqm, // 4 - External Interrupt Controller + irq_handler_usb, // 5 - Universal Serial Bus Controller + irq_handler_nvmctrl, // 6 - Non-Volatile Memory Controller + irq_handler_dmac, // 7 - Direct Memory Access Controller + irq_handler_evsys, // 8 - Event System + irq_handler_sercom0, // 9 - Serial Communication Interface 0 + irq_handler_sercom1, // 10 - Serial Communication Interface 1 + irq_handler_sercom2, // 11 - Serial Communication Interface 2 + irq_handler_sercom3, // 12 - Serial Communication Interface 3 + irq_handler_sercom4, // 13 - Serial Communication Interface 4 + irq_handler_sercom5, // 14 - Serial Communication Interface 5 + irq_handler_tcc0, // 15 - Timer/Counter for Control 0 + irq_handler_tc0, // 16 - Timer/Counter 0 + irq_handler_tc1, // 17 - Timer/Counter 1 + irq_handler_tc2, // 18 - Timer/Counter 2 + irq_handler_tc3, // 19 - Timer/Counter 3 + irq_handler_adc, // 20 - Analog-to-Digital Converter + irq_handler_ac, // 21 - Analog Comparator + irq_handler_ptc, // 22 - Peripheral Touch Controller + irq_handler_slcd, // 23 - Segment Liquid Crystal Display Controller + irq_handler_aes, // 24 - Advanced Encryption Standard + irq_handler_trng, // 25 - True Random Number Generator +}; + +//----------------------------------------------------------------------------- +void irq_handler_reset(void) +{ + unsigned int *src, *dst; + + src = &_etext; + dst = &_data; + while (dst < &_edata) + *dst++ = *src++; + + dst = &_bss; + while (dst < &_ebss) + *dst++ = 0; + + SCB->VTOR = (uint32_t)vectors; + + main(); + + while (1); +} + +//----------------------------------------------------------------------------- +void irq_handler_dummy(void) +{ + while (1); +} + +//----------------------------------------------------------------------------- +void _exit(int status) +{ + (void)status; + while (1); +}