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Merge branch 'main' into more-asf-files

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This commit is contained in:
Joey Castillo
2021-10-25 14:52:40 -04:00
parent 24e160611e badb4ba909
commit 22c072ac3f
84 changed files with 24965 additions and 1903 deletions
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7
watch-library/config/hpl_eic_config.h
View File

@@ -271,7 +271,7 @@
// <i> Indicates whether the external interrupt 5 filter is enabled or not
// <id> eic_arch_filten5
#ifndef CONF_EIC_FILTEN5
#define CONF_EIC_FILTEN5 0
#define CONF_EIC_FILTEN5 1
#endif
// <q> External Interrupt 5 Event Output Enable
@@ -723,7 +723,12 @@
// </e>
// my god this is a hack. need to refactor this out of ASF and into our driver. - joey 10/19
#ifdef CRYSTALLESS
#define CONFIG_EIC_EXTINT_MAP {2, PIN_PA02}, {5, PIN_PB05}, {7, PIN_PA07},
#else
#define CONFIG_EIC_EXTINT_MAP {2, PIN_PA02}, {6, PIN_PA22}, {7, PIN_PA23},
#endif
// <<< end of configuration section >>>

5
watch-library/config/hpl_gclk_config.h
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@@ -248,9 +248,14 @@
// <i> This defines the clock source for generic clock generator 3
// <id> gclk_gen_3_oscillator
#ifndef CONF_GCLK_GEN_3_SOURCE
#ifdef CRYSTALLESS
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
#else
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
#endif
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_3_runstdby

4
watch-library/config/hpl_osc32kctrl_config.h
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@@ -17,8 +17,12 @@
// <i> This defines the clock source for RTC
// <id> rtc_source_oscillator
#ifndef CONF_RTCCTRL_SRC
#ifdef CRYSTALLESS
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
#else
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
#endif
#endif
// <q> Use 1 kHz output
// <id> rtc_1khz_selection

46
watch-library/config/hpl_slcd_config.h
View File

@@ -6,6 +6,7 @@
#include <hpl_slcd_cm.h>
#include <peripheral_clk_config.h>
#include "pins.h"
// <h> Standard configuration
@@ -79,7 +80,7 @@
// <3=>128
// <id> slcd_arch_presc
#ifndef CONF_SLCD_PRESC
#define CONF_SLCD_PRESC 2
#define CONF_SLCD_PRESC 1
#endif
// <o> Clock Divider
@@ -94,7 +95,7 @@
// <7=>8
// <id> slcd_arch_ckdiv
#ifndef CONF_SLCD_CKDIV
#define CONF_SLCD_CKDIV 3
#define CONF_SLCD_CKDIV 5
#endif
/* TODO add frame frequency check */
@@ -2729,15 +2730,40 @@
} \
}
#define CONF_SLCD_LPENL \
((uint32_t)1 << 0 | (uint32_t)1 << 1 | (uint32_t)1 << 2 | (uint32_t)1 << 3 | (uint32_t)1 << 4 | (uint32_t)1 << 5 \
| (uint32_t)1 << 6 | (uint32_t)1 << 7 | (uint32_t)1 << 11 | (uint32_t)1 << 12 | (uint32_t)1 << 13 \
| (uint32_t)1 << 14 | (uint32_t)1 << 21 | (uint32_t)1 << 22 | (uint32_t)1 << 23 | (uint32_t)1 << 24 \
| (uint32_t)1 << 25 | (uint32_t)1 << 28 | (uint32_t)1 << 29 | (uint32_t)1 << 30 | (uint32_t)1 << 31 | 0)
#ifndef CONF_SLCD_LPENL
#define CONF_SLCD_LPENL (\
(uint32_t)1 << 0 | \
(uint32_t)1 << 1 | \
(uint32_t)1 << 2 | \
(uint32_t)1 << 3 | \
(uint32_t)1 << 4 | \
(uint32_t)1 << 5 | \
(uint32_t)1 << 6 | \
(uint32_t)1 << 7 | \
(uint32_t)1 << 11 | \
(uint32_t)1 << 12 | \
(uint32_t)1 << 13 | \
(uint32_t)1 << 14 | \
(uint32_t)1 << 21 | \
(uint32_t)1 << 22 | \
(uint32_t)1 << 23 | \
(uint32_t)1 << 24 | \
(uint32_t)1 << 25 | \
(uint32_t)1 << 28 | \
(uint32_t)1 << 29 | \
(uint32_t)1 << 30 | \
(uint32_t)1 << 31 | 0)
#endif // CONF_SLCD_LPENL
#define CONF_SLCD_LPENH \
((uint32_t)1 << 0 | (uint32_t)1 << 1 | (uint32_t)1 << 2 | (uint32_t)1 << 3 | (uint32_t)1 << 10 | (uint32_t)1 << 11 \
| 0) // </e>
#ifndef CONF_SLCD_LPENH
#define CONF_SLCD_LPENH (\
(uint32_t)1 << (32 - 32) | \
(uint32_t)1 << (33 - 32) | \
(uint32_t)1 << (34 - 32) | \
(uint32_t)1 << (35 - 32) | \
(uint32_t)1 << (42 - 32) | \
(uint32_t)1 << (43 - 32) | 0)
#endif // CONF_SLCD_LPENH
// <<< end of configuration section >>>