add more atmel studio framework code
This commit is contained in:
Joey Castillo
38
watch-library/config/hpl_nvmctrl_config.h
Executable file
38
watch-library/config/hpl_nvmctrl_config.h
Executable file
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/* Auto-generated config file hpl_nvmctrl_config.h */
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#ifndef HPL_NVMCTRL_CONFIG_H
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#define HPL_NVMCTRL_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Basic Settings
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// <o> Read Mode Selection
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// <0x00=> No Miss Penalty
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// <0x01=> Low Power
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// <0x02=> Deterministic
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// <id> nvm_arch_read_mode
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#ifndef CONF_NVM_READ_MODE
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#define CONF_NVM_READ_MODE 1
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#endif
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// <o> Power Reduction Mode During Sleep
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// <0x00=> Wake On Access
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// <0x01=> Wake Up Instant
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// <0x03=> Disabled
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// <id> nvm_arch_sleepprm
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#ifndef CONF_NVM_SLEEPPRM
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#define CONF_NVM_SLEEPPRM 0
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#endif
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// <q> Cache Disable
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// <i> Indicate whether cache is disable or not
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// <id> nvm_arch_cache
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#ifndef CONF_NVM_CACHE
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#define CONF_NVM_CACHE 0
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#endif
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// </h>
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// <<< end of configuration section >>>
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#endif // HPL_NVMCTRL_CONFIG_H
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@@ -139,6 +139,165 @@
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#endif
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#endif
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#include <peripheral_clk_config.h>
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// Enable configuration of module
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#ifndef CONF_SERCOM_3_SPI_ENABLE
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#define CONF_SERCOM_3_SPI_ENABLE 0
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#endif
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// Set module in SPI Master mode
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#ifndef CONF_SERCOM_3_SPI_MODE
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#define CONF_SERCOM_3_SPI_MODE 0x03
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#endif
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// <h> Basic Configuration
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// <q> Receive buffer enable
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// <i> Enable receive buffer to receive data from slave (RXEN)
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// <id> spi_master_rx_enable
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#ifndef CONF_SERCOM_3_SPI_RXEN
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#define CONF_SERCOM_3_SPI_RXEN 0x1
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#endif
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// <o> Character Size
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// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
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// <0x0=>8 bits
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// <0x1=>9 bits
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// <id> spi_master_character_size
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#ifndef CONF_SERCOM_3_SPI_CHSIZE
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#define CONF_SERCOM_3_SPI_CHSIZE 0x0
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#endif
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// <o> Baud rate <1-12000000>
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// <i> The SPI data transfer rate
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// <id> spi_master_baud_rate
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#ifndef CONF_SERCOM_3_SPI_BAUD
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#define CONF_SERCOM_3_SPI_BAUD 50000
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#endif
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// </h>
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// <e> Advanced Configuration
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// <id> spi_master_advanced
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#ifndef CONF_SERCOM_3_SPI_ADVANCED
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#define CONF_SERCOM_3_SPI_ADVANCED 0
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#endif
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// <o> Dummy byte <0x00-0x1ff>
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// <id> spi_master_dummybyte
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// <i> Dummy byte used when reading data from the slave without sending any data
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#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE
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#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff
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#endif
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// <o> Data Order
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// <0=>MSB first
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// <1=>LSB first
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// <i> I least significant or most significant bit is shifted out first (DORD)
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// <id> spi_master_arch_dord
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#ifndef CONF_SERCOM_3_SPI_DORD
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#define CONF_SERCOM_3_SPI_DORD 0x0
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#endif
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// <o> Clock Polarity
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// <0=>SCK is low when idle
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// <1=>SCK is high when idle
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// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
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// <id> spi_master_arch_cpol
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#ifndef CONF_SERCOM_3_SPI_CPOL
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#define CONF_SERCOM_3_SPI_CPOL 0x0
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#endif
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// <o> Clock Phase
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// <0x0=>Sample input on leading edge
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// <0x1=>Sample input on trailing edge
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// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
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// <id> spi_master_arch_cpha
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#ifndef CONF_SERCOM_3_SPI_CPHA
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#define CONF_SERCOM_3_SPI_CPHA 0x0
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#endif
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// <o> Immediate Buffer Overflow Notification
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// <i> Controls when OVF is asserted (IBON)
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// <0x0=>In data stream
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// <0x1=>On buffer overflow
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// <id> spi_master_arch_ibon
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#ifndef CONF_SERCOM_3_SPI_IBON
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#define CONF_SERCOM_3_SPI_IBON 0x0
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#endif
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// <q> Run in stand-by
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// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
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// <id> spi_master_arch_runstdby
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#ifndef CONF_SERCOM_3_SPI_RUNSTDBY
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#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0
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#endif
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// <o> Debug Stop Mode
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// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
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// <0=>Keep running
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// <1=>Halt
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// <id> spi_master_arch_dbgstop
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#ifndef CONF_SERCOM_3_SPI_DBGSTOP
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#define CONF_SERCOM_3_SPI_DBGSTOP 0
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#endif
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// </e>
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// Address mode disabled in master mode
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#ifndef CONF_SERCOM_3_SPI_AMODE_EN
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#define CONF_SERCOM_3_SPI_AMODE_EN 0
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#endif
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#ifndef CONF_SERCOM_3_SPI_AMODE
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#define CONF_SERCOM_3_SPI_AMODE 0
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#endif
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#ifndef CONF_SERCOM_3_SPI_ADDR
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#define CONF_SERCOM_3_SPI_ADDR 0
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#endif
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#ifndef CONF_SERCOM_3_SPI_ADDRMASK
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#define CONF_SERCOM_3_SPI_ADDRMASK 0
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#endif
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#ifndef CONF_SERCOM_3_SPI_SSDE
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#define CONF_SERCOM_3_SPI_SSDE 0
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#endif
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#ifndef CONF_SERCOM_3_SPI_MSSEN
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#define CONF_SERCOM_3_SPI_MSSEN 0x0
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#endif
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#ifndef CONF_SERCOM_3_SPI_PLOADEN
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#define CONF_SERCOM_3_SPI_PLOADEN 0
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#endif
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// <o> Receive Data Pinout
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// <0x0=>PAD[0]
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// <0x1=>PAD[1]
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// <0x2=>PAD[2]
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// <0x3=>PAD[3]
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// <id> spi_master_rxpo
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#ifndef CONF_SERCOM_3_SPI_RXPO
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#define CONF_SERCOM_3_SPI_RXPO 2
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#endif
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// <o> Transmit Data Pinout
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// <0x0=>PAD[0,1]_DO_SCK
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// <0x1=>PAD[2,3]_DO_SCK
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// <0x2=>PAD[3,1]_DO_SCK
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// <0x3=>PAD[0,3]_DO_SCK
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// <id> spi_master_txpo
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#ifndef CONF_SERCOM_3_SPI_TXPO
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#define CONF_SERCOM_3_SPI_TXPO 3
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#endif
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// Calculate baud register value from requested baudrate value
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#ifndef CONF_SERCOM_3_SPI_BAUD_RATE
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#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1
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#endif
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// <<< end of configuration section >>>
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#endif // HPL_SERCOM_CONFIG_H
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27
watch-library/config/hpl_trng_config.h
Executable file
27
watch-library/config/hpl_trng_config.h
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/* Auto-generated config file hpl_trng_config.h */
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#ifndef HPL_TRNG_CONFIG_H
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#define HPL_TRNG_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Advanced configurations
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// <q> Run In Standby
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// <i> Indicates whether the TRNG works in standby mode
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// <id> trng_runstdby
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#ifndef CONF_TRNG_RUNSTDBY
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#define CONF_TRNG_RUNSTDBY 0
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#endif
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// <q> Data Ready Event Output Enable
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// <i> Indicates whether the TRNG generates event on Data Ready
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// <id> trng_datardyeo
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#ifndef CONF_TRNG_DATARDYEO
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#define CONF_TRNG_DATARDYEO 0
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#endif
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// </h>
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// <<< end of configuration section >>>
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#endif // HPL_TRNG_CONFIG_H
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51
watch-library/config/nv_storage_config.h
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51
watch-library/config/nv_storage_config.h
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/* Auto-generated config file nv_storage_config.h */
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#ifndef NV_STORAGE_CONFIG_H
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#define NV_STORAGE_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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//<o> Storage start address <0x00000000-0xFFFFFFFF>
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//<i> This defines the start address of device flash for storage.
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//<i> The start address should be in device flash area.
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//<i> The start address and (start address + Item Number * Sector size) cannot beyond device flash area.
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//<id> conf_storage_memory_start
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#ifndef CONF_STORAGE_MEMORY_START
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#define CONF_STORAGE_MEMORY_START 0x10000
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#endif
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//<o> Item number <0-65535>
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//<i> This defines the maximum number of elements stored in persistent storage
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//<id> conf_max_item_number
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#ifndef CONF_MAX_ITEM_NUMBER
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#define CONF_MAX_ITEM_NUMBER 10
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#endif
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//<o> Sector size <0-65535>
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//<i> This defines the size of one storage sector in bytes
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//<id> conf_sector_size
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#ifndef CONF_SECTOR_SIZE
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#define CONF_SECTOR_SIZE 4096
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#endif
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/**
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* Check If the Storage configuration out of the flash area.
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*/
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#ifdef FLASH_SIZE
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#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > FLASH_SIZE
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#error Invalidate storage configuration, make sure the configuration with \
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the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \
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are located within the device flash size.
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#endif
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#endif
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#ifdef IFLASH_SIZE
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#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > IFLASH_SIZE
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#error Invalidate storage configuration, make sure the configuration with \
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the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \
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are located within the device flash size.
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#endif
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#endif
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// <<< end of configuration section >>>
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#endif // NV_STORAGE_CONFIG_H
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@@ -132,6 +132,58 @@
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#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
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#endif
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// <y> Core Clock Source
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// <id> core_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <i> Select the clock source for CORE.
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#ifndef CONF_GCLK_SERCOM3_CORE_SRC
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#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#endif
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// <y> Slow Clock Source
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// <id> slow_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <i> Select the slow clock source.
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#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
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#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#endif
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/**
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* \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
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* \brief SERCOM3's Core Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
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#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 4000000
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#endif
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/**
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* \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
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* \brief SERCOM3's Slow Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
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#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
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#endif
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// <y> TC Clock Source
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// <id> tc_gclk_selection
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