add more atmel studio framework code
This commit is contained in:
Joey Castillo
314
watch-library/hal/src/hal_flash.c
Executable file
314
watch-library/hal/src/hal_flash.c
Executable file
@@ -0,0 +1,314 @@
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/**
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* \file
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*
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* \brief Flash functionality implementation.
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
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||||
*/
|
||||
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#include "hal_flash.h"
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#include <utils_assert.h>
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#include <utils.h>
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#include <hal_atomic.h>
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/**
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* \brief Driver version
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*/
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#define DRIVER_VERSION 0x00000001u
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static void flash_ready(struct _flash_device *device);
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static void flash_error(struct _flash_device *device);
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static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr);
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/**
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* \brief Initialize the FLASH HAL instance and hardware for callback mode.
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*/
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int32_t flash_init(struct flash_descriptor *flash, void *const hw)
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{
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int32_t rc;
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ASSERT(flash && hw);
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rc = _flash_init(&flash->dev, hw);
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if (rc) {
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return rc;
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}
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flash->dev.flash_cb.ready_cb = flash_ready;
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flash->dev.flash_cb.error_cb = flash_error;
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return ERR_NONE;
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}
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/**
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* \brief Deinitialize the FLASH HAL instance.
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*/
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int32_t flash_deinit(struct flash_descriptor *flash)
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{
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ASSERT(flash);
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_flash_deinit(&flash->dev);
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return ERR_NONE;
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}
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/**
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* \brief Reads a number of bytes to a page in the internal Flash
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*/
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int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length)
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{
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ASSERT(flash && buffer && length);
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uint32_t page_size = _flash_get_page_size(&flash->dev);
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uint32_t total_pages = _flash_get_total_pages(&flash->dev);
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/* Check if the address is valid */
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if ((src_addr > page_size * total_pages) || (src_addr + length > page_size * total_pages)) {
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return ERR_BAD_ADDRESS;
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}
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_flash_read(&flash->dev, src_addr, buffer, length);
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return ERR_NONE;
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}
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/**
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* \brief Updates several bytes to the internal Flash
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*/
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int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length)
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{
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ASSERT(flash && buffer && length);
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uint32_t page_size = _flash_get_page_size(&flash->dev);
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uint32_t total_pages = _flash_get_total_pages(&flash->dev);
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/* Check if the address is valid */
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if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) {
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return ERR_BAD_ADDRESS;
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}
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if (_flash_is_locked(&flash->dev, dst_addr)) {
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return ERR_DENIED;
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}
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_flash_write(&flash->dev, dst_addr, buffer, length);
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return ERR_NONE;
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}
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/**
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* \brief Appends a number of bytes to a page in the internal Flash
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*/
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int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length)
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{
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ASSERT(flash && buffer && length);
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uint32_t page_size = _flash_get_page_size(&flash->dev);
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uint32_t total_pages = _flash_get_total_pages(&flash->dev);
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/* Check if the address is valid */
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if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) {
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return ERR_BAD_ADDRESS;
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}
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if (_flash_is_locked(&flash->dev, dst_addr)) {
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return ERR_DENIED;
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}
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_flash_append(&flash->dev, dst_addr, buffer, length);
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return ERR_NONE;
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}
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/**
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* \brief Execute erase in the internal flash
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*/
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int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums)
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{
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ASSERT(flash && page_nums);
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uint32_t page_size = _flash_get_page_size(&flash->dev);
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uint32_t total_pages = _flash_get_total_pages(&flash->dev);
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int32_t rc;
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rc = flash_is_address_aligned(flash, dst_addr);
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if (rc) {
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return rc;
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}
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if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) {
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return ERR_INVALID_ARG;
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}
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_flash_erase(&flash->dev, dst_addr, page_nums);
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return ERR_NONE;
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}
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/**
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* \brief Register a function as FLASH transfer completion callback
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*/
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int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func)
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{
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ASSERT(flash);
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switch (type) {
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case FLASH_CB_READY:
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flash->callbacks.cb_ready = func;
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break;
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case FLASH_CB_ERROR:
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flash->callbacks.cb_error = func;
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break;
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default:
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return ERR_INVALID_ARG;
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}
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_flash_set_irq_state(&flash->dev, (enum _flash_cb_type)type, NULL != func);
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return ERR_NONE;
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}
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/**
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* \brief Execute lock in the internal flash
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*/
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int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums)
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{
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ASSERT(flash && page_nums);
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uint32_t page_size = _flash_get_page_size(&flash->dev);
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uint32_t total_pages = _flash_get_total_pages(&flash->dev);
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int32_t rc;
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rc = flash_is_address_aligned(flash, dst_addr);
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if (rc) {
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return rc;
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}
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if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) {
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return ERR_INVALID_ARG;
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}
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return _flash_lock(&flash->dev, dst_addr, page_nums);
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}
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/**
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* \brief Execute unlock in the internal flash
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*/
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int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums)
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{
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ASSERT(flash && page_nums);
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uint32_t page_size = _flash_get_page_size(&flash->dev);
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uint32_t total_pages = _flash_get_total_pages(&flash->dev);
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int32_t rc;
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rc = flash_is_address_aligned(flash, dst_addr);
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if (rc) {
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return rc;
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}
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if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) {
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return ERR_INVALID_ARG;
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}
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return _flash_unlock(&flash->dev, dst_addr, page_nums);
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}
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/**
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* \brief Get the flash page size.
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*/
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uint32_t flash_get_page_size(struct flash_descriptor *flash)
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{
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ASSERT(flash);
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return _flash_get_page_size(&flash->dev);
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}
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/**
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* \brief Get the numbers of flash page.
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*/
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uint32_t flash_get_total_pages(struct flash_descriptor *flash)
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{
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ASSERT(flash);
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return _flash_get_total_pages(&flash->dev);
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}
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/**
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* \brief Retrieve the current driver version
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*/
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uint32_t flash_get_version(void)
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{
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return DRIVER_VERSION;
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}
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/**
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* \internal check the address whether it is aligned
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* \param[in, out] flash Pointer to the HAL FLASH instance.
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* \param[in] flash_addr address to be check in flash
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*
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* \return whether it is valid
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* \retval 0 Valid.
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* \retval -1 Error, invalid.
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*/
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static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr)
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{
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ASSERT(flash);
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uint32_t page_size = _flash_get_page_size(&flash->dev);
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/* Check if the read address not aligned to the start of a page */
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if (flash_addr & (page_size - 1)) {
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return ERR_BAD_ADDRESS;
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}
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return ERR_NONE;
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}
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/**
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* \internal Ready for a new flash command
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*
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* \param[in] device The pointer to flash device structure
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*/
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static void flash_ready(struct _flash_device *device)
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{
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struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev);
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if (descr->callbacks.cb_ready) {
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descr->callbacks.cb_ready(descr);
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}
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}
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/**
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* \internal Error occurs in flash command
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*
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* \param[in] device The pointer to flash device structure
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*/
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static void flash_error(struct _flash_device *device)
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{
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struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev);
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if (descr->callbacks.cb_error) {
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descr->callbacks.cb_error(descr);
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}
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}
|
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122
watch-library/hal/src/hal_rand_sync.c
Executable file
122
watch-library/hal/src/hal_rand_sync.c
Executable file
@@ -0,0 +1,122 @@
|
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/**
|
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* \file
|
||||
*
|
||||
* \brief Generic Random Number Generator (RNG) functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include <utils.h>
|
||||
#include "hal_rand_sync.h"
|
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|
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#define HAL_RNG_SYNC_VERSION 0x00000001u
|
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int32_t rand_sync_init(struct rand_sync_desc *const desc, void *const hw)
|
||||
{
|
||||
ASSERT(desc);
|
||||
|
||||
return _rand_sync_init(&desc->dev, hw);
|
||||
}
|
||||
|
||||
void rand_sync_deinit(struct rand_sync_desc *const desc)
|
||||
{
|
||||
ASSERT(desc);
|
||||
_rand_sync_deinit(&desc->dev);
|
||||
}
|
||||
|
||||
int32_t rand_sync_enable(struct rand_sync_desc *const desc)
|
||||
{
|
||||
ASSERT(desc);
|
||||
return _rand_sync_enable(&desc->dev);
|
||||
}
|
||||
|
||||
void rand_sync_disable(struct rand_sync_desc *const desc)
|
||||
{
|
||||
ASSERT(desc);
|
||||
_rand_sync_disable(&desc->dev);
|
||||
}
|
||||
|
||||
int32_t rand_sync_set_seed(struct rand_sync_desc *const desc, const uint32_t seed)
|
||||
{
|
||||
ASSERT(desc);
|
||||
return _rand_sync_set_seed(&desc->dev, seed);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Read data bits
|
||||
*/
|
||||
static uint32_t _rand_sync_read_data(const struct _rand_sync_dev *dev, const uint8_t n_bits)
|
||||
{
|
||||
uint8_t r_bits = (dev->n_bits < 1) ? 32 : dev->n_bits;
|
||||
if (r_bits < n_bits) {
|
||||
uint8_t i;
|
||||
uint32_t d = 0;
|
||||
/* Join read bits */
|
||||
for (i = 0; i < n_bits; i += r_bits) {
|
||||
d |= (uint32_t)(_rand_sync_read_one(dev) << i);
|
||||
}
|
||||
return d;
|
||||
} else {
|
||||
return _rand_sync_read_one(dev);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t rand_sync_read8(const struct rand_sync_desc *const desc)
|
||||
{
|
||||
ASSERT(desc);
|
||||
return (uint8_t)_rand_sync_read_data(&desc->dev, 8);
|
||||
}
|
||||
|
||||
uint32_t rand_sync_read32(const struct rand_sync_desc *const desc)
|
||||
{
|
||||
ASSERT(desc);
|
||||
return (uint32_t)_rand_sync_read_data(&desc->dev, 32);
|
||||
}
|
||||
|
||||
void rand_sync_read_buf8(const struct rand_sync_desc *const desc, uint8_t *buf, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
ASSERT(desc && (buf && len));
|
||||
for (i = 0; i < len; i++) {
|
||||
buf[i] = (uint8_t)_rand_sync_read_data(&desc->dev, 8);
|
||||
}
|
||||
}
|
||||
|
||||
void rand_sync_read_buf32(const struct rand_sync_desc *const desc, uint32_t *buf, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
ASSERT(desc && (buf && len));
|
||||
for (i = 0; i < len; i++) {
|
||||
buf[i] = (uint32_t)_rand_sync_read_data(&desc->dev, 32);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t rand_sync_get_version(void)
|
||||
{
|
||||
return HAL_RNG_SYNC_VERSION;
|
||||
}
|
||||
201
watch-library/hal/src/hal_spi_m_sync.c
Executable file
201
watch-library/hal/src/hal_spi_m_sync.c
Executable file
@@ -0,0 +1,201 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I/O SPI related functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hal_spi_m_sync.h"
|
||||
#include <utils_assert.h>
|
||||
#include <utils.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define SPI_M_SYNC_DRIVER_VERSION 0x00000001u
|
||||
|
||||
#define SPI_DEACTIVATE_NEXT 0x8000
|
||||
|
||||
static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length);
|
||||
static int32_t _spi_m_sync_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief Initialize the SPI HAL instance function pointer for HPL APIs.
|
||||
*/
|
||||
void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func)
|
||||
{
|
||||
ASSERT(spi);
|
||||
spi->func = (struct _spi_m_sync_hpl_interface *)func;
|
||||
}
|
||||
|
||||
int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw)
|
||||
{
|
||||
int32_t rc = 0;
|
||||
ASSERT(spi && hw);
|
||||
spi->dev.prvt = (void *)hw;
|
||||
rc = _spi_m_sync_init(&spi->dev, hw);
|
||||
|
||||
if (rc < 0) {
|
||||
return rc;
|
||||
}
|
||||
|
||||
spi->flags = SPI_DEACTIVATE_NEXT;
|
||||
spi->io.read = _spi_m_sync_io_read;
|
||||
spi->io.write = _spi_m_sync_io_write;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi)
|
||||
{
|
||||
ASSERT(spi);
|
||||
_spi_m_sync_deinit(&spi->dev);
|
||||
}
|
||||
|
||||
void spi_m_sync_enable(struct spi_m_sync_descriptor *spi)
|
||||
{
|
||||
ASSERT(spi);
|
||||
_spi_m_sync_enable(&spi->dev);
|
||||
}
|
||||
|
||||
void spi_m_sync_disable(struct spi_m_sync_descriptor *spi)
|
||||
{
|
||||
ASSERT(spi);
|
||||
_spi_m_sync_disable(&spi->dev);
|
||||
}
|
||||
|
||||
int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val)
|
||||
{
|
||||
ASSERT(spi);
|
||||
return _spi_m_sync_set_baudrate(&spi->dev, baud_val);
|
||||
}
|
||||
|
||||
int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode)
|
||||
{
|
||||
ASSERT(spi);
|
||||
return _spi_m_sync_set_mode(&spi->dev, mode);
|
||||
}
|
||||
|
||||
int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size)
|
||||
{
|
||||
ASSERT(spi);
|
||||
return _spi_m_sync_set_char_size(&spi->dev, char_size);
|
||||
}
|
||||
|
||||
int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord)
|
||||
{
|
||||
ASSERT(spi);
|
||||
return _spi_m_sync_set_data_order(&spi->dev, dord);
|
||||
}
|
||||
|
||||
/** \brief Do SPI read in polling way
|
||||
* For SPI master, activate CS, do send 0xFFs and read data, deactivate CS.
|
||||
*
|
||||
* It blocks until all data read or error.
|
||||
*
|
||||
* \param[in, out] spi Pointer to the HAL SPI instance.
|
||||
* \param[out] buf Pointer to the buffer to store read data.
|
||||
* \param[in] size Size of the data in number of characters.
|
||||
* \return Operation status.
|
||||
* \retval size Success.
|
||||
* \retval >=0 Time out, with number of characters read.
|
||||
*/
|
||||
static int32_t _spi_m_sync_io_read(struct io_descriptor *io, uint8_t *buf, const uint16_t length)
|
||||
{
|
||||
ASSERT(io);
|
||||
|
||||
struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io);
|
||||
struct spi_xfer xfer;
|
||||
|
||||
xfer.rxbuf = buf;
|
||||
xfer.txbuf = 0;
|
||||
xfer.size = length;
|
||||
|
||||
return spi_m_sync_transfer(spi, &xfer);
|
||||
}
|
||||
|
||||
/** \brief Do SPI data write in polling way
|
||||
* For SPI master, activate CS, do buffer send and deactivate CS. The data back
|
||||
* is discarded.
|
||||
*
|
||||
* The data read back is discarded.
|
||||
*
|
||||
* It blocks until all data sent or error.
|
||||
*
|
||||
* \param[in, out] spi Pointer to the HAL SPI instance.
|
||||
* \param[in] p_xfer Pointer to the transfer information (\ref spi_transfer).
|
||||
* \return Operation status.
|
||||
* \retval size Success.
|
||||
* \retval >=0 Timeout, with number of characters transferred.
|
||||
*/
|
||||
static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length)
|
||||
{
|
||||
ASSERT(io);
|
||||
|
||||
struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io);
|
||||
struct spi_xfer xfer;
|
||||
|
||||
xfer.rxbuf = 0;
|
||||
xfer.txbuf = (uint8_t *)buf;
|
||||
xfer.size = length;
|
||||
|
||||
return spi_m_sync_transfer(spi, &xfer);
|
||||
}
|
||||
|
||||
int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer)
|
||||
{
|
||||
struct spi_msg msg;
|
||||
|
||||
ASSERT(spi && p_xfer);
|
||||
|
||||
msg.txbuf = p_xfer->txbuf;
|
||||
msg.rxbuf = p_xfer->rxbuf;
|
||||
msg.size = p_xfer->size;
|
||||
return _spi_m_sync_trans(&spi->dev, &msg);
|
||||
}
|
||||
|
||||
int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io)
|
||||
{
|
||||
ASSERT(spi && io);
|
||||
*io = &spi->io;
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t spi_m_sync_get_version(void)
|
||||
{
|
||||
return SPI_M_SYNC_DRIVER_VERSION;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
276
watch-library/hal/src/hal_usart_sync.c
Executable file
276
watch-library/hal/src/hal_usart_sync.c
Executable file
@@ -0,0 +1,276 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I/O USART related functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hal_usart_sync.h"
|
||||
#include <utils_assert.h>
|
||||
#include <utils.h>
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define DRIVER_VERSION 0x00000001u
|
||||
|
||||
static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
|
||||
static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief Initialize usart interface
|
||||
*/
|
||||
int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func)
|
||||
{
|
||||
int32_t init_status;
|
||||
ASSERT(descr && hw);
|
||||
init_status = _usart_sync_init(&descr->device, hw);
|
||||
if (init_status) {
|
||||
return init_status;
|
||||
}
|
||||
|
||||
descr->io.read = usart_sync_read;
|
||||
descr->io.write = usart_sync_write;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Uninitialize usart interface
|
||||
*/
|
||||
int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_deinit(&descr->device);
|
||||
|
||||
descr->io.read = NULL;
|
||||
descr->io.write = NULL;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable usart interface
|
||||
*/
|
||||
int32_t usart_sync_enable(struct usart_sync_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_enable(&descr->device);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable usart interface
|
||||
*/
|
||||
int32_t usart_sync_disable(struct usart_sync_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_disable(&descr->device);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve I/O descriptor
|
||||
*/
|
||||
int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io)
|
||||
{
|
||||
ASSERT(descr && io);
|
||||
|
||||
*io = &descr->io;
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Specify action for flow control pins
|
||||
*/
|
||||
int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr,
|
||||
const union usart_flow_control_state state)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_flow_control_state(&descr->device, state);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart baud rate
|
||||
*/
|
||||
int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_baud_rate(&descr->device, baud_rate);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart data order
|
||||
*/
|
||||
int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_data_order(&descr->device, data_order);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart mode
|
||||
*/
|
||||
int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_mode(&descr->device, mode);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart parity
|
||||
*/
|
||||
int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_parity(&descr->device, parity);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart stop bits
|
||||
*/
|
||||
int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_stop_bits(&descr->device, stop_bits);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart character size
|
||||
*/
|
||||
int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_character_size(&descr->device, size);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the state of flow control pins
|
||||
*/
|
||||
int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr,
|
||||
union usart_flow_control_state *const state)
|
||||
{
|
||||
ASSERT(descr && state);
|
||||
*state = _usart_sync_get_flow_control_state(&descr->device);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Check if the usart transmitter is empty
|
||||
*/
|
||||
int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
return _usart_sync_is_ready_to_send(&descr->device);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Check if the usart receiver is not empty
|
||||
*/
|
||||
int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
return _usart_sync_is_byte_received(&descr->device);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*/
|
||||
uint32_t usart_sync_get_version(void)
|
||||
{
|
||||
return DRIVER_VERSION;
|
||||
}
|
||||
|
||||
/*
|
||||
* \internal Write the given data to usart interface
|
||||
*
|
||||
* \param[in] descr The pointer to an io descriptor
|
||||
* \param[in] buf Data to write to usart
|
||||
* \param[in] length The number of bytes to write
|
||||
*
|
||||
* \return The number of bytes written.
|
||||
*/
|
||||
static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
|
||||
{
|
||||
uint32_t offset = 0;
|
||||
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
|
||||
|
||||
ASSERT(io_descr && buf && length);
|
||||
while (!_usart_sync_is_ready_to_send(&descr->device))
|
||||
;
|
||||
do {
|
||||
_usart_sync_write_byte(&descr->device, buf[offset]);
|
||||
while (!_usart_sync_is_ready_to_send(&descr->device))
|
||||
;
|
||||
} while (++offset < length);
|
||||
while (!_usart_sync_is_transmit_done(&descr->device))
|
||||
;
|
||||
return (int32_t)offset;
|
||||
}
|
||||
|
||||
/*
|
||||
* \internal Read data from usart interface
|
||||
*
|
||||
* \param[in] descr The pointer to an io descriptor
|
||||
* \param[in] buf A buffer to read data to
|
||||
* \param[in] length The size of a buffer
|
||||
*
|
||||
* \return The number of bytes read.
|
||||
*/
|
||||
static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
|
||||
{
|
||||
uint32_t offset = 0;
|
||||
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
|
||||
|
||||
ASSERT(io_descr && buf && length);
|
||||
do {
|
||||
while (!_usart_sync_is_byte_received(&descr->device))
|
||||
;
|
||||
buf[offset] = _usart_sync_read_byte(&descr->device);
|
||||
} while (++offset < length);
|
||||
|
||||
return (int32_t)offset;
|
||||
}
|
||||
Reference in New Issue
Block a user