add more atmel studio framework code
This commit is contained in:
Joey Castillo
782
watch-library/hpl/nvmctrl/hpl_nvmctrl.c
Executable file
782
watch-library/hpl/nvmctrl/hpl_nvmctrl.c
Executable file
@@ -0,0 +1,782 @@
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/**
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* \file
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*
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* \brief Non-Volatile Memory Controller
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <hpl_flash.h>
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#include <hpl_user_area.h>
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#include <string.h>
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#include <utils_assert.h>
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#include <utils.h>
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#include <hpl_nvmctrl_config.h>
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#define NVM_MEMORY ((volatile uint16_t *)FLASH_ADDR)
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/**
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* \brief NVM configuration type
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*/
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struct nvm_configuration {
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hri_nvmctrl_ctrlb_reg_t ctrlb; /*!< Control B Register */
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};
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/**
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* \brief Array of NVM configurations
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*/
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static struct nvm_configuration _nvm
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= {(CONF_NVM_CACHE << NVMCTRL_CTRLB_CACHEDIS_Pos) | (CONF_NVM_READ_MODE << NVMCTRL_CTRLB_READMODE_Pos)
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| (CONF_NVM_SLEEPPRM << NVMCTRL_CTRLB_SLEEPPRM_Pos)};
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/*!< Pointer to hpl device */
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static struct _flash_device *_nvm_dev = NULL;
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static void _flash_erase_row(void *const hw, const uint32_t dst_addr, uint32_t nvmctrl_cmd);
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static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size,
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uint32_t nvmctrl_cmd);
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/**
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* \brief Initialize NVM
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*/
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int32_t _flash_init(struct _flash_device *const device, void *const hw)
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{
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ASSERT(device && (hw == NVMCTRL));
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uint32_t ctrlb;
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device->hw = hw;
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ctrlb = _nvm.ctrlb & ~(NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW);
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ctrlb |= hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW);
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hri_nvmctrl_write_CTRLB_reg(device->hw, ctrlb);
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_nvm_dev = device;
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NVIC_DisableIRQ(NVMCTRL_IRQn);
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NVIC_ClearPendingIRQ(NVMCTRL_IRQn);
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NVIC_EnableIRQ(NVMCTRL_IRQn);
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return ERR_NONE;
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}
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/**
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* \brief De-initialize NVM
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*/
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void _flash_deinit(struct _flash_device *const device)
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{
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device->hw = NULL;
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NVIC_DisableIRQ(NVMCTRL_IRQn);
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}
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/**
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* \brief Get the flash page size.
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*/
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uint32_t _flash_get_page_size(struct _flash_device *const device)
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{
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(void)device;
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return (uint32_t)NVMCTRL_PAGE_SIZE;
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}
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/**
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* \brief Get the numbers of flash page.
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*/
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uint32_t _flash_get_total_pages(struct _flash_device *const device)
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{
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(void)device;
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return (uint32_t)FLASH_NB_OF_PAGES;
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}
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/**
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* \brief Get the number of wait states for read and write operations.
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*/
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uint8_t _flash_get_wait_state(struct _flash_device *const device)
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{
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return hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk);
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}
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/**
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* \brief Set the number of wait states for read and write operations.
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*/
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void _flash_set_wait_state(struct _flash_device *const device, uint8_t state)
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{
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hri_nvmctrl_write_CTRLB_RWS_bf(device->hw, state);
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}
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/**
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* \brief Reads a number of bytes to a page in the internal Flash.
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*/
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void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length)
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{
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uint32_t nvm_address = src_addr / 2;
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uint32_t i;
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uint16_t data;
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/* Check if the module is busy */
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while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) {
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/* Wait until this module isn't busy */
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}
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/* Clear flags */
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hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK);
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/* Check whether byte address is word-aligned*/
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if (src_addr % 2) {
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data = NVM_MEMORY[nvm_address++];
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buffer[0] = data >> 8;
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i = 1;
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} else {
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i = 0;
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}
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/* NVM _must_ be accessed as a series of 16-bit words, perform manual copy
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* to ensure alignment */
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while (i < length) {
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data = NVM_MEMORY[nvm_address++];
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buffer[i] = (data & 0xFF);
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if (i < (length - 1)) {
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buffer[i + 1] = (data >> 8);
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}
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i += 2;
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}
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}
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/**
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* \brief Writes a number of bytes to a page in the internal Flash.
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*/
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void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length)
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{
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uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE];
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uint32_t row_start_addr, row_end_addr;
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uint32_t i, j, k;
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uint32_t wr_start_addr = dst_addr;
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do {
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row_start_addr = wr_start_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1);
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row_end_addr = row_start_addr + NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE - 1;
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/* store the erase data into temp buffer before write */
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for (i = 0; i < NVMCTRL_ROW_PAGES; i++) {
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_flash_read(device, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE);
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}
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/* temp buffer update */
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j = (wr_start_addr - row_start_addr) / NVMCTRL_PAGE_SIZE;
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k = wr_start_addr - row_start_addr - j * NVMCTRL_PAGE_SIZE;
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while ((wr_start_addr <= row_end_addr) && (length > 0)) {
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tmp_buffer[j][k] = *buffer;
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k = (k + 1) % NVMCTRL_PAGE_SIZE;
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if (0 == k) {
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j++;
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}
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wr_start_addr++;
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buffer++;
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length--;
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}
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/* erase row before write */
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_flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_ER);
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/* write buffer to flash */
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for (i = 0; i < NVMCTRL_ROW_PAGES; i++) {
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_flash_program(device->hw,
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row_start_addr + i * NVMCTRL_PAGE_SIZE,
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tmp_buffer[i],
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NVMCTRL_PAGE_SIZE,
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NVMCTRL_CTRLA_CMD_WP);
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}
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} while (row_end_addr < (wr_start_addr + length - 1));
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}
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/**
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* \brief Appends a number of bytes in the internal Flash.
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*/
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void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length)
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{
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uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1);
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uint32_t size;
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uint32_t offset = 0;
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if (dst_addr != page_start_addr) {
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/* Need to write some data to the end of a page */
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size = min(length, NVMCTRL_PAGE_SIZE - (dst_addr - page_start_addr));
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_flash_program(device->hw, dst_addr, buffer, size, NVMCTRL_CTRLA_CMD_WP);
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page_start_addr += NVMCTRL_PAGE_SIZE;
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offset += size;
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}
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while (offset < length) {
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size = min(length - offset, NVMCTRL_PAGE_SIZE);
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_flash_program(device->hw, page_start_addr, buffer + offset, size, NVMCTRL_CTRLA_CMD_WP);
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page_start_addr += NVMCTRL_PAGE_SIZE;
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offset += size;
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}
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}
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/**
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* \brief Execute erase in the internal flash
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*/
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void _flash_erase(struct _flash_device *const device, uint32_t dst_addr, uint32_t page_nums)
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{
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uint8_t tmp_buffer[NVMCTRL_PAGE_SIZE];
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uint32_t row_start_addr;
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uint32_t i;
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row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1);
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memset(tmp_buffer, 0xFF, NVMCTRL_PAGE_SIZE);
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/* when address is not aligned with row start address */
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if (dst_addr != row_start_addr) {
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row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE;
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for (i = 0; i < NVMCTRL_ROW_PAGES - 1; i++) {
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_flash_write(device, dst_addr, tmp_buffer, NVMCTRL_PAGE_SIZE);
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if (--page_nums == 0) {
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return;
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}
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dst_addr += NVMCTRL_PAGE_SIZE;
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if (dst_addr == row_start_addr) {
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break;
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}
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}
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}
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while (page_nums >= NVMCTRL_ROW_PAGES) {
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_flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_ER);
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row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE;
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page_nums -= NVMCTRL_ROW_PAGES;
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}
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if (page_nums != 0) {
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for (i = 0; i < page_nums; i++) {
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_flash_write(device, row_start_addr, tmp_buffer, NVMCTRL_PAGE_SIZE);
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row_start_addr += NVMCTRL_PAGE_SIZE;
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}
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}
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}
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/**
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* \brief Execute lock in the internal flash
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*/
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int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums)
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{
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uint32_t region_pages;
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uint32_t row_start_addr;
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region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE);
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row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1);
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if ((page_nums != region_pages) || (dst_addr != row_start_addr)) {
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return ERR_INVALID_ARG;
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}
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while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) {
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/* Wait until this module isn't busy */
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}
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/* Clear flags */
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hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK);
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hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2);
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hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_LR | NVMCTRL_CTRLA_CMDEX_KEY);
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return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE);
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}
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/**
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* \brief Execute unlock in the internal flash
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*/
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int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums)
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{
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uint32_t region_pages;
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uint32_t row_start_addr;
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region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE);
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row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1);
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if ((page_nums != region_pages) || (dst_addr != row_start_addr)) {
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return ERR_INVALID_ARG;
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}
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while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) {
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/* Wait until this module isn't busy */
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}
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/* Clear flags */
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hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK);
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hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2);
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hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_UR | NVMCTRL_CTRLA_CMDEX_KEY);
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return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE);
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}
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/**
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* \brief check whether the region which is pointed by address
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*/
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bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr)
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{
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uint16_t region_id;
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/* Get region for given page */
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region_id = dst_addr / (NVMCTRL_FLASH_SIZE / 16);
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return !(hri_nvmctrl_get_LOCK_reg(device->hw, 1 << region_id));
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}
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/**
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* \brief Enable/disable Flash interrupt
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*/
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void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state)
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{
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ASSERT(device);
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if (FLASH_DEVICE_CB_READY == type) {
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hri_nvmctrl_write_INTEN_READY_bit(device->hw, state);
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} else if (FLASH_DEVICE_CB_ERROR == type) {
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hri_nvmctrl_write_INTEN_ERROR_bit(device->hw, state);
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}
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}
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/**
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* \internal erase a row in flash
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* \param[in] hw The pointer to hardware instance
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* \param[in] dst_addr Destination page address to erase
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*/
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static void _flash_erase_row(void *const hw, const uint32_t dst_addr, uint32_t nvmctrl_cmd)
|
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{
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while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) {
|
||||
/* Wait until this module isn't busy */
|
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}
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||||
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/* Clear flags */
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hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK);
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||||
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/* Set address and command */
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hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2);
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||||
hri_nvmctrl_write_CTRLA_reg(hw, nvmctrl_cmd | NVMCTRL_CTRLA_CMDEX_KEY);
|
||||
}
|
||||
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/**
|
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* \internal write a page in flash
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* \param[in] hw The pointer to hardware instance
|
||||
* \param[in] dst_addr Destination page address to write
|
||||
* \param[in] buffer Pointer to buffer where the data to
|
||||
* write is stored
|
||||
* \param[in] size The size of data to write to a page
|
||||
*/
|
||||
static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size,
|
||||
uint32_t nvmctrl_cmd)
|
||||
{
|
||||
ASSERT(!(dst_addr % 2));
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||||
|
||||
uint32_t nvm_address = dst_addr / 2;
|
||||
uint16_t i, data;
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||||
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while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) {
|
||||
/* Wait until this module isn't busy */
|
||||
}
|
||||
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||||
hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY);
|
||||
|
||||
while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) {
|
||||
/* Wait until this module isn't busy */
|
||||
}
|
||||
|
||||
/* Clear flags */
|
||||
hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK);
|
||||
|
||||
for (i = 0; i < size; i += 2) {
|
||||
data = buffer[i];
|
||||
if (i < NVMCTRL_PAGE_SIZE - 1) {
|
||||
data |= (buffer[i + 1] << 8);
|
||||
}
|
||||
NVM_MEMORY[nvm_address++] = data;
|
||||
}
|
||||
|
||||
while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) {
|
||||
/* Wait until this module isn't busy */
|
||||
}
|
||||
|
||||
hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2);
|
||||
hri_nvmctrl_write_CTRLA_reg(hw, nvmctrl_cmd | NVMCTRL_CTRLA_CMDEX_KEY);
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal NVM interrupt handler
|
||||
*/
|
||||
void NVMCTRL_Handler(void)
|
||||
{
|
||||
void *const hw = _nvm_dev->hw;
|
||||
|
||||
if (hri_nvmctrl_get_interrupt_READY_bit(hw)) {
|
||||
if (NULL != _nvm_dev->flash_cb.ready_cb) {
|
||||
_nvm_dev->flash_cb.ready_cb(_nvm_dev);
|
||||
}
|
||||
} else if (hri_nvmctrl_get_interrupt_ERROR_bit(hw)) {
|
||||
hri_nvmctrl_clear_interrupt_ERROR_bit(hw);
|
||||
if (NULL != _nvm_dev->flash_cb.error_cb) {
|
||||
_nvm_dev->flash_cb.error_cb(_nvm_dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
The NVM User Row contains calibration data that are automatically read at device
|
||||
power on.
|
||||
The NVM User Row can be read at address 0x804000.
|
||||
*/
|
||||
#ifndef _NVM_USER_ROW_BASE
|
||||
#define _NVM_USER_ROW_BASE 0x804000
|
||||
#endif
|
||||
#define _NVM_USER_ROW_N_BITS 64
|
||||
#define _NVM_USER_ROW_N_BYTES (_NVM_USER_ROW_N_BITS / 8)
|
||||
#define _NVM_USER_ROW_END (((uint8_t *)_NVM_USER_ROW_BASE) + _NVM_USER_ROW_N_BYTES - 1)
|
||||
#define _IS_NVM_USER_ROW(b) \
|
||||
(((uint8_t *)(b) >= (uint8_t *)(_NVM_USER_ROW_BASE)) && ((uint8_t *)(b) <= (uint8_t *)(_NVM_USER_ROW_END)))
|
||||
#define _IN_NVM_USER_ROW(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_USER_ROW_END))
|
||||
|
||||
/*
|
||||
The NVM Software Calibration Area can be read at address 0x806020.
|
||||
The NVM Software Calibration Area can not be written.
|
||||
*/
|
||||
#ifndef _NVM_SW_CALIB_AREA_BASE
|
||||
#define _NVM_SW_CALIB_AREA_BASE 0x806020
|
||||
#endif
|
||||
#define _NVM_SW_CALIB_AREA_N_BITS 128
|
||||
#define _NVM_SW_CALIB_AREA_N_BYTES (_NVM_SW_CALIB_AREA_N_BITS / 8)
|
||||
#define _NVM_SW_CALIB_AREA_END (((uint8_t *)_NVM_SW_CALIB_AREA_BASE) + _NVM_SW_CALIB_AREA_N_BYTES - 1)
|
||||
#define _IS_NVM_SW_CALIB_AREA(b) \
|
||||
(((uint8_t *)(b) >= (uint8_t *)_NVM_SW_CALIB_AREA_BASE) && ((uint8_t *)(b) <= (uint8_t *)_NVM_SW_CALIB_AREA_END))
|
||||
#define _IN_NVM_SW_CALIB_AREA(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_SW_CALIB_AREA_END))
|
||||
|
||||
/**
|
||||
* \internal Read left aligned data bits
|
||||
* \param[in] base Base address for the data
|
||||
* \param[in] bit_offset Offset for the bitfield start
|
||||
* \param[in] n_bits Number of bits in the bitfield
|
||||
*/
|
||||
static inline uint32_t _user_area_read_l32_bits(const volatile uint32_t *base, const uint32_t bit_offset,
|
||||
const uint8_t n_bits)
|
||||
{
|
||||
return base[bit_offset >> 5] & ((1 << n_bits) - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal Read right aligned data bits
|
||||
* \param[in] base Base address for the data
|
||||
* \param[in] bit_offset Offset for the bitfield start
|
||||
* \param[in] n_bits Number of bits in the bitfield
|
||||
*/
|
||||
static inline uint32_t _user_area_read_r32_bits(const volatile uint32_t *base, const uint32_t bit_offset,
|
||||
const uint8_t n_bits)
|
||||
{
|
||||
return (base[bit_offset >> 5] >> (bit_offset & 0x1F)) & ((1 << n_bits) - 1);
|
||||
}
|
||||
|
||||
int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, uint32_t size)
|
||||
{
|
||||
ASSERT(buf);
|
||||
|
||||
/** Parameter check. */
|
||||
if (_IS_NVM_USER_ROW(base)) {
|
||||
if (!_IN_NVM_USER_ROW(base, offset)) {
|
||||
return ERR_BAD_ADDRESS;
|
||||
}
|
||||
/* Cut off if request too many bytes */
|
||||
if (!_IN_NVM_USER_ROW(base, offset + size - 1)) {
|
||||
return ERR_INVALID_ARG;
|
||||
}
|
||||
} else if (_IS_NVM_SW_CALIB_AREA(base)) {
|
||||
if (!_IN_NVM_SW_CALIB_AREA(base, offset)) {
|
||||
return ERR_BAD_ADDRESS;
|
||||
}
|
||||
/* Cut off if request too many bytes */
|
||||
if (!_IN_NVM_SW_CALIB_AREA(base, offset + size - 1)) {
|
||||
return ERR_INVALID_ARG;
|
||||
}
|
||||
} else {
|
||||
return ERR_UNSUPPORTED_OP;
|
||||
}
|
||||
|
||||
/* Copy data */
|
||||
memcpy(buf, ((uint8_t *)base) + offset, size);
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits)
|
||||
{
|
||||
volatile uint32_t *mem_base = (volatile uint32_t *)base;
|
||||
uint32_t l_off, l_bits;
|
||||
uint32_t r_off, r_bits;
|
||||
|
||||
/** Parameter check. */
|
||||
if (_IS_NVM_USER_ROW(base)) {
|
||||
ASSERT(_IN_NVM_USER_ROW(base, bit_offset >> 3) && _IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3));
|
||||
} else if (_IS_NVM_SW_CALIB_AREA(base)) {
|
||||
ASSERT(_IN_NVM_SW_CALIB_AREA(base, bit_offset >> 3)
|
||||
&& _IN_NVM_SW_CALIB_AREA(base, (bit_offset + n_bits - 1) >> 3));
|
||||
} else {
|
||||
ASSERT(false);
|
||||
}
|
||||
|
||||
/* Since the bitfield can cross 32-bits boundaries,
|
||||
* left and right bits are read from 32-bit aligned address
|
||||
* and then combined together. */
|
||||
l_off = bit_offset & (~(32 - 1));
|
||||
r_off = l_off + 32;
|
||||
l_bits = 32 - (bit_offset & (32 - 1));
|
||||
if (n_bits > l_bits) {
|
||||
r_bits = n_bits - l_bits;
|
||||
} else {
|
||||
l_bits = n_bits;
|
||||
r_bits = 0;
|
||||
}
|
||||
return _user_area_read_r32_bits(mem_base, bit_offset, l_bits)
|
||||
+ (_user_area_read_l32_bits(mem_base, r_off, r_bits) << l_bits);
|
||||
}
|
||||
|
||||
/** \internal Write 64-bit user row
|
||||
* \param[in] _row Pointer to 64-bit user row data.
|
||||
*/
|
||||
static int32_t _user_row_write_exec(const uint32_t *_row)
|
||||
{
|
||||
Nvmctrl *hw = NVMCTRL;
|
||||
uint32_t ctrlb = hri_nvmctrl_read_CTRLB_reg(NVMCTRL);
|
||||
|
||||
/* Denie if Security Bit is set */
|
||||
if (hri_nvmctrl_get_STATUS_reg(hw, NVMCTRL_STATUS_SB)) {
|
||||
return ERR_DENIED;
|
||||
}
|
||||
|
||||
/* Do Save */
|
||||
|
||||
/* - Prepare. */
|
||||
while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) {
|
||||
/* Wait until this module isn't busy */
|
||||
}
|
||||
hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK);
|
||||
hri_nvmctrl_set_CTRLB_MANW_bit(hw);
|
||||
|
||||
/* - Erase AUX row. */
|
||||
hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)(_NVM_USER_ROW_BASE / 2));
|
||||
hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_EAR | NVMCTRL_CTRLA_CMDEX_KEY);
|
||||
while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) {
|
||||
/* Wait until this module isn't busy */
|
||||
}
|
||||
|
||||
/* - Page buffer clear & write. */
|
||||
hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY);
|
||||
while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) {
|
||||
/* Wait until this module isn't busy */
|
||||
}
|
||||
*((uint32_t *)NVMCTRL_AUX0_ADDRESS) = _row[0];
|
||||
*(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1) = _row[1];
|
||||
|
||||
/* - Write AUX row. */
|
||||
hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)(_NVM_USER_ROW_BASE / 2));
|
||||
hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_WAP | NVMCTRL_CTRLA_CMDEX_KEY);
|
||||
while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) {
|
||||
/* Wait until this module isn't busy */
|
||||
}
|
||||
|
||||
/* Restore CTRLB */
|
||||
hri_nvmctrl_write_CTRLB_reg(NVMCTRL, ctrlb);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size)
|
||||
{
|
||||
uint32_t _row[2]; /* Copy of user row. */
|
||||
|
||||
/** Parameter check. */
|
||||
if (_IS_NVM_USER_ROW(base)) {
|
||||
if (!_IN_NVM_USER_ROW(base, offset)) {
|
||||
return ERR_BAD_ADDRESS;
|
||||
} else if (!_IN_NVM_USER_ROW(base, offset + size - 1)) {
|
||||
return ERR_INVALID_ARG;
|
||||
}
|
||||
} else if (_IS_NVM_SW_CALIB_AREA(base)) {
|
||||
return ERR_DENIED;
|
||||
} else {
|
||||
return ERR_UNSUPPORTED_OP;
|
||||
}
|
||||
|
||||
memcpy(_row, base, 8); /* Store previous data. */
|
||||
memcpy((uint8_t *)_row + offset, buf, size); /* Modify with buf data. */
|
||||
|
||||
return _user_row_write_exec(_row);
|
||||
}
|
||||
|
||||
int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits)
|
||||
{
|
||||
uint32_t _row[2]; /* Copy of user row. */
|
||||
uint32_t l_off, l_bits;
|
||||
uint32_t r_off, r_bits;
|
||||
|
||||
/** Parameter check. */
|
||||
if (_IS_NVM_USER_ROW(base)) {
|
||||
if (!_IN_NVM_USER_ROW(base, bit_offset >> 3)) {
|
||||
return ERR_BAD_ADDRESS;
|
||||
} else if (!_IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)) {
|
||||
return ERR_INVALID_ARG;
|
||||
}
|
||||
} else if (_IS_NVM_SW_CALIB_AREA(base)) {
|
||||
return ERR_DENIED;
|
||||
} else {
|
||||
return ERR_UNSUPPORTED_OP;
|
||||
}
|
||||
|
||||
/* Since the bitfield can cross 32-bits boundaries,
|
||||
* left and right bits are splitted for 32-bit aligned address
|
||||
* and then saved. */
|
||||
l_off = bit_offset & (~(32 - 1));
|
||||
r_off = l_off + 32;
|
||||
l_bits = 32 - (bit_offset & (32 - 1));
|
||||
if (n_bits > l_bits) {
|
||||
r_bits = n_bits - l_bits;
|
||||
} else {
|
||||
l_bits = n_bits;
|
||||
r_bits = 0;
|
||||
}
|
||||
|
||||
memcpy(_row, base, 8); /* Store previous data. */
|
||||
if (l_bits) {
|
||||
uint32_t l_mask = ((1 << l_bits) - 1) << (bit_offset & (32 - 1));
|
||||
_row[bit_offset >> 5] &= ~l_mask;
|
||||
_row[bit_offset >> 5] |= (bits << (bit_offset & (32 - 1))) & l_mask;
|
||||
}
|
||||
if (r_bits) {
|
||||
uint32_t r_mask = (1 << r_bits) - 1;
|
||||
_row[r_off >> 5] &= ~r_mask;
|
||||
_row[r_off >> 5] |= bits >> l_bits;
|
||||
}
|
||||
return _user_row_write_exec(_row);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Return if given address is in Flash RWWEE array range.
|
||||
*/
|
||||
static bool _is_valid_rww_flash_address(uint32_t addr)
|
||||
{
|
||||
#define RWWEE_ADDR_START NVMCTRL_RWW_EEPROM_ADDR
|
||||
#define RWWEE_ADDR_END (NVMCTRL_RWW_EEPROM_ADDR + NVMCTRL_PAGE_SIZE * NVMCTRL_RWWEE_PAGES)
|
||||
|
||||
if ((addr < NVMCTRL_RWW_EEPROM_ADDR)
|
||||
|| (addr > (NVMCTRL_RWW_EEPROM_ADDR + NVMCTRL_PAGE_SIZE * NVMCTRL_RWWEE_PAGES))) {
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get the RWWEE flash page size.
|
||||
*/
|
||||
uint32_t _rww_flash_get_page_size(struct _flash_device *const device)
|
||||
{
|
||||
(void)device;
|
||||
return (uint32_t)NVMCTRL_PAGE_SIZE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get the total page numbers of RWWEE flash.
|
||||
*/
|
||||
uint32_t _rww_flash_get_total_pages(struct _flash_device *const device)
|
||||
{
|
||||
(void)device;
|
||||
return (uint32_t)NVMCTRL_RWWEE_PAGES;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Reads a number of bytes in the internal RWWEE Flash.
|
||||
*/
|
||||
int32_t _rww_flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
/* Check if the address is valid */
|
||||
if (!_is_valid_rww_flash_address(src_addr) || !_is_valid_rww_flash_address(src_addr + length)) {
|
||||
return ERR_BAD_ADDRESS;
|
||||
}
|
||||
|
||||
_flash_read(device, src_addr, buffer, length);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Writes a number of bytes in the internal RWWEE Flash.
|
||||
*/
|
||||
int32_t _rww_flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE];
|
||||
uint32_t row_start_addr, row_end_addr;
|
||||
uint32_t i, j, k;
|
||||
uint32_t wr_start_addr = dst_addr;
|
||||
|
||||
/* Check if the address is valid */
|
||||
if (!_is_valid_rww_flash_address(dst_addr) || !_is_valid_rww_flash_address(dst_addr + length)) {
|
||||
return ERR_BAD_ADDRESS;
|
||||
}
|
||||
|
||||
do {
|
||||
row_start_addr = wr_start_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1);
|
||||
row_end_addr = row_start_addr + NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE - 1;
|
||||
|
||||
/* store the erase data into temp buffer before write */
|
||||
for (i = 0; i < NVMCTRL_ROW_PAGES; i++) {
|
||||
_rww_flash_read(device, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE);
|
||||
}
|
||||
|
||||
/* temp buffer update */
|
||||
j = (wr_start_addr - row_start_addr) / NVMCTRL_PAGE_SIZE;
|
||||
k = wr_start_addr - row_start_addr - j * NVMCTRL_PAGE_SIZE;
|
||||
while ((wr_start_addr <= row_end_addr) && (length > 0)) {
|
||||
tmp_buffer[j][k] = *buffer;
|
||||
k = (k + 1) % NVMCTRL_PAGE_SIZE;
|
||||
if (0 == k) {
|
||||
j++;
|
||||
}
|
||||
wr_start_addr++;
|
||||
buffer++;
|
||||
length--;
|
||||
}
|
||||
|
||||
/* erase row before write */
|
||||
_flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_RWWEEER);
|
||||
|
||||
/* write buffer to flash */
|
||||
for (i = 0; i < NVMCTRL_ROW_PAGES; i++) {
|
||||
_flash_program(device->hw,
|
||||
row_start_addr + i * NVMCTRL_PAGE_SIZE,
|
||||
tmp_buffer[i],
|
||||
NVMCTRL_PAGE_SIZE,
|
||||
NVMCTRL_CTRLA_CMD_RWWEEWP);
|
||||
}
|
||||
|
||||
} while (row_end_addr < (wr_start_addr + length - 1));
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
Reference in New Issue
Block a user