major project reorg, move library one level up

watch-library/config/peripheral_clk_config.h

@@ -0,0 +1,214 @@
+/* Auto-generated config file peripheral_clk_config.h */
+#ifndef PERIPHERAL_CLK_CONFIG_H
+#define PERIPHERAL_CLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <y> ADC Clock Source
+// <id> adc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the clock source for ADC.
+#ifndef CONF_GCLK_ADC_SRC
+#define CONF_GCLK_ADC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_ADC_FREQUENCY
+ * \brief ADC's Clock frequency
+ */
+#ifndef CONF_GCLK_ADC_FREQUENCY
+#define CONF_GCLK_ADC_FREQUENCY 4000000
+#endif
+
+// <y> EIC Clock Source
+// <id> eic_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the clock source for EIC.
+#ifndef CONF_GCLK_EIC_SRC
+#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EIC_FREQUENCY
+ * \brief EIC's Clock frequency
+ */
+#ifndef CONF_GCLK_EIC_FREQUENCY
+#define CONF_GCLK_EIC_FREQUENCY 32768
+#endif
+
+/**
+ * \def CONF_CPU_FREQUENCY
+ * \brief CPU's Clock frequency
+ */
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 4000000
+#endif
+
+// <y> RTC Clock Source
+// <id> rtc_clk_selection
+// <RTC_CLOCK_SOURCE"> RTC source
+// <i> Select the clock source for RTC.
+#ifndef CONF_GCLK_RTC_SRC
+#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
+#endif
+
+/**
+ * \def CONF_GCLK_RTC_FREQUENCY
+ * \brief RTC's Clock frequency
+ */
+#ifndef CONF_GCLK_RTC_FREQUENCY
+#define CONF_GCLK_RTC_FREQUENCY 1024
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM1_CORE_SRC
+#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
+#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
+ * \brief SERCOM1's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 4000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+ * \brief SERCOM1's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
+#endif
+
+// <y> TC Clock Source
+// <id> tc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the clock source for TC.
+#ifndef CONF_GCLK_TC3_SRC
+#define CONF_GCLK_TC3_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TC3_FREQUENCY
+ * \brief TC3's Clock frequency
+ */
+#ifndef CONF_GCLK_TC3_FREQUENCY
+#define CONF_GCLK_TC3_FREQUENCY 32768
+#endif
+
+// <y> TCC Clock Source
+// <id> tcc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the clock source for TCC.
+#ifndef CONF_GCLK_TCC0_SRC
+#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TCC0_FREQUENCY
+ * \brief TCC0's Clock frequency
+ */
+#ifndef CONF_GCLK_TCC0_FREQUENCY
+#define CONF_GCLK_TCC0_FREQUENCY 32768
+#endif
+
+#include <hpl_osc32kctrl_config.h>
+
+// <y> SLCD Clock Source
+// <id> slcd_clk_selection
+// <SLCD_CLOCK_SOURCE"> SLCD source
+// <i> Select the clock source for SLCD.
+#ifndef CONF_GCLK_SLCD_SRC
+#define CONF_GCLK_SLCD_SRC SLCD_CLOCK_SOURCE
+#endif
+
+/**
+ * \def CONF_GCLK_SLCD_FREQUENCY
+ * \brief SLCD's Clock frequency
+ */
+#ifndef CONF_GCLK_SLCD_FREQUENCY
+#define CONF_GCLK_SLCD_FREQUENCY 32768
+#endif
+
+#ifndef SLCD_FRAME_FREQUENCY
+#define SLCD_FRAME_FREQUENCY                                                                                           \
+	(CONF_GCLK_SLCD_FREQUENCY                                                                                          \
+	 / (((CONF_SLCD_PRESC + 1) * 16) * (CONF_SLCD_CKDIV + 1)                                                           \
+	    * ((CONF_SLCD_COM_NUM == 4) ? 6 : ((CONF_SLCD_COM_NUM == 5) ? 8 : (CONF_SLCD_COM_NUM + 1)))))
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // PERIPHERAL_CLK_CONFIG_H