major project reorg, move library one level up
This commit is contained in:
Joey Castillo
200
watch-library/hpl/core/hpl_core_m0plus_base.c
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200
watch-library/hpl/core/hpl_core_m0plus_base.c
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/**
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* \file
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*
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* \brief Core related functionality implementation.
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*
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* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <hpl_core.h>
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#include <hpl_irq.h>
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#include <hpl_reset.h>
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#include <hpl_sleep.h>
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#include <hpl_delay.h>
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#ifndef _UNIT_TEST_
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#include <utils.h>
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#endif
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#include <utils_assert.h>
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#include <peripheral_clk_config.h>
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#ifndef CONF_CPU_FREQUENCY
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#define CONF_CPU_FREQUENCY 1000000
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#endif
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#if CONF_CPU_FREQUENCY < 1000
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#define CPU_FREQ_POWER 3
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#elif CONF_CPU_FREQUENCY < 10000
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#define CPU_FREQ_POWER 4
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#elif CONF_CPU_FREQUENCY < 100000
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#define CPU_FREQ_POWER 5
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#elif CONF_CPU_FREQUENCY < 1000000
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#define CPU_FREQ_POWER 6
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#elif CONF_CPU_FREQUENCY < 10000000
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#define CPU_FREQ_POWER 7
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#elif CONF_CPU_FREQUENCY < 100000000
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#define CPU_FREQ_POWER 8
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#endif
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/**
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* \brief The array of interrupt handlers
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*/
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struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn];
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/**
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* \brief Reset MCU
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*/
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void _reset_mcu(void)
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{
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NVIC_SystemReset();
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}
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/**
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* \brief Put MCU to sleep
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*/
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void _go_to_sleep(void)
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{
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__DSB();
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__WFI();
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}
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/**
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* \brief Retrieve current IRQ number
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*/
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uint8_t _irq_get_current(void)
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{
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return (uint8_t)__get_IPSR() - 16;
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}
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/**
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* \brief Disable the given IRQ
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*/
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void _irq_disable(uint8_t n)
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{
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NVIC_DisableIRQ((IRQn_Type)n);
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}
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/**
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* \brief Set the given IRQ
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*/
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void _irq_set(uint8_t n)
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{
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NVIC_SetPendingIRQ((IRQn_Type)n);
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}
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/**
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* \brief Clear the given IRQ
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*/
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void _irq_clear(uint8_t n)
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{
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NVIC_ClearPendingIRQ((IRQn_Type)n);
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}
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/**
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* \brief Enable the given IRQ
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*/
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void _irq_enable(uint8_t n)
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{
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NVIC_EnableIRQ((IRQn_Type)n);
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}
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/**
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* \brief Register IRQ handler
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*/
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void _irq_register(const uint8_t n, struct _irq_descriptor *const irq)
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{
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ASSERT(n < PERIPH_COUNT_IRQn);
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_irq_table[n] = irq;
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}
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/**
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* \brief Default interrupt handler for unused IRQs.
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*/
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void Default_Handler(void)
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{
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while (1) {
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}
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}
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/**
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* \brief Retrieve the amount of cycles to delay for the given amount of us
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*/
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static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power)
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{
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switch (power) {
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case 8:
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return (us * (freq / 100000) - 1) / 10 + 1;
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case 7:
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return (us * (freq / 10000) - 1) / 100 + 1;
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case 6:
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return (us * (freq / 1000) - 1) / 1000 + 1;
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case 5:
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return (us * (freq / 100) - 1) / 10000 + 1;
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case 4:
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return (us * (freq / 10) - 1) / 100000 + 1;
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default:
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return (us * freq - 1) / 1000000 + 1;
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}
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}
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/**
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* \brief Retrieve the amount of cycles to delay for the given amount of us
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*/
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uint32_t _get_cycles_for_us(const uint16_t us)
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{
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return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER);
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}
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/**
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* \brief Retrieve the amount of cycles to delay for the given amount of ms
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*/
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static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power)
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{
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switch (power) {
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case 8:
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return (ms * (freq / 100000)) * 100;
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case 7:
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return (ms * (freq / 10000)) * 10;
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case 6:
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return (ms * (freq / 1000));
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case 5:
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return (ms * (freq / 100) - 1) / 10 + 1;
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case 4:
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return (ms * (freq / 10) - 1) / 100 + 1;
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default:
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return (ms * freq - 1) / 1000 + 1;
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}
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}
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/**
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* \brief Retrieve the amount of cycles to delay for the given amount of ms
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*/
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uint32_t _get_cycles_for_ms(const uint16_t ms)
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{
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return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER);
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}
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61
watch-library/hpl/core/hpl_core_port.h
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61
watch-library/hpl/core/hpl_core_port.h
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@@ -0,0 +1,61 @@
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/**
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* \file
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*
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* \brief Core related functionality implementation.
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
|
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* may accompany Microchip software.
|
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _HPL_CORE_PORT_H_INCLUDED
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#define _HPL_CORE_PORT_H_INCLUDED
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#include <peripheral_clk_config.h>
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/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR
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* portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h),
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* there will be assembling errors.
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* So the following things are not included for assembling.
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*/
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#ifndef _UNIT_TEST_
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#include <compiler.h>
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#endif
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/**
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* \brief Check if it's in ISR handling
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* \return \c true if it's in ISR
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*/
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static inline bool _is_in_isr(void)
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{
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return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
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}
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _HPL_CORE_PORT_H_INCLUDED */
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74
watch-library/hpl/core/hpl_init.c
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74
watch-library/hpl/core/hpl_init.c
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@@ -0,0 +1,74 @@
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/**
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* \file
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*
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* \brief HPL initialization related functionality implementation.
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*
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* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <hpl_gpio.h>
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#include <hpl_init.h>
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#include <hpl_gclk_base.h>
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#include <hpl_mclk_config.h>
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#include <hpl_dma.h>
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#include <hpl_dmac_config.h>
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/* Referenced GCLKs (out of 0~4), should be initialized firstly
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*/
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#define _GCLK_INIT_1ST 0x00000000
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/* Not referenced GCLKs, initialized last */
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#define _GCLK_INIT_LAST 0x0000001F
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/**
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* \brief Initialize the hardware abstraction layer
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*/
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void _init_chip(void)
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{
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hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
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_set_performance_level(2);
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_osc32kctrl_init_sources();
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_oscctrl_init_sources();
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_mclk_init();
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#if _GCLK_INIT_1ST
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_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
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#endif
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_oscctrl_init_referenced_generators();
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_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
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#if CONF_DMAC_ENABLE
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hri_mclk_set_AHBMASK_DMAC_bit(MCLK);
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_dma_init();
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#endif
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#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
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_port_event_init();
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#endif
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}
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