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remove timer; tick based on RTC PER7 interrupt

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This commit is contained in:
Joey Castillo
2021-05-02 15:45:40 -04:00
parent 9b381ef6ae
commit 88a38cc235
17 changed files with 18 additions and 979 deletions
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8
Smol Watch Project/My Project/hpl/rtc/hpl_rtc.c
View File

@@ -316,10 +316,10 @@ int32_t _tamper_register_callback(struct calendar_dev *const dev, tamper_drv_cb_
NVIC_EnableIRQ(RTC_IRQn);
/* enable tamper interrupt */
hri_rtcmode0_set_INTEN_TAMPER_bit(dev->hw);
hri_rtcmode0_set_INTEN_PER7_bit(dev->hw);
} else {
/* disable tamper interrupt */
hri_rtcmode0_clear_INTEN_TAMPER_bit(dev->hw);
hri_rtcmode0_clear_INTEN_PER7_bit(dev->hw);
/* disable RTC_IRQn */
NVIC_DisableIRQ(RTC_IRQn);
@@ -372,11 +372,11 @@ static void _rtc_interrupt_handler(struct calendar_dev *dev)
/* Clear interrupt flag */
hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw);
} else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) {
} else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_PER7) {
dev->callback_tamper(dev);
/* Clear interrupt flag */
hri_rtcmode0_clear_interrupt_TAMPER_bit(dev->hw);
hri_rtcmode0_clear_interrupt_PER7_bit(dev->hw);
}
}
/**

153
Smol Watch Project/My Project/hpl/tc/hpl_tc.c
View File

@@ -139,59 +139,11 @@ static struct _pwm_hpl_interface _tc_pwm_functions = {
_tc_pwm_set_irq_state,
};
static struct _timer_device *_tc0_dev = NULL;
static struct _pwm_device *_tc3_dev = NULL;
static int8_t get_tc_index(const void *const hw);
static void _tc_init_irq_param(const void *const hw, void *dev);
static inline uint8_t _get_hardware_offset(const void *const hw);
/**
* \brief Initialize TC
*/
int32_t _timer_init(struct _timer_device *const device, void *const hw)
{
int8_t i = get_tc_index(hw);
device->hw = hw;
ASSERT(ARRAY_SIZE(_tcs));
if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) {
if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) {
hri_tc_clear_CTRLA_ENABLE_bit(hw);
hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE);
}
hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST);
}
hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a);
hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl);
hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl);
hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MFRQ);
if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0);
hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) {
hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0);
hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1);
} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) {
hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0);
hri_tccount8_write_CC_reg(hw, 1, (uint8_t)_tcs[i].cc1);
hri_tccount8_write_PER_reg(hw, _tcs[i].per);
}
hri_tc_set_INTEN_OVF_bit(hw);
_tc_init_irq_param(hw, (void *)device);
NVIC_DisableIRQ(_tcs[i].irq);
NVIC_ClearPendingIRQ(_tcs[i].irq);
NVIC_EnableIRQ(_tcs[i].irq);
return ERR_NONE;
}
/**
* \brief Initialize TC for PWM mode
*/
@@ -232,20 +184,6 @@ int32_t _tc_pwm_init(struct _pwm_device *const device, void *const hw)
return 0;
}
/**
* \brief De-initialize TC
*/
void _timer_deinit(struct _timer_device *const device)
{
void *const hw = device->hw;
int8_t i = get_tc_index(hw);
ASSERT(ARRAY_SIZE(_tcs));
NVIC_DisableIRQ(_tcs[i].irq);
hri_tc_clear_CTRLA_ENABLE_bit(hw);
hri_tc_set_CTRLA_SWRST_bit(hw);
}
/**
* \brief De-initialize TC for PWM mode
*/
@@ -260,13 +198,6 @@ void _tc_pwm_deinit(struct _pwm_device *const device)
hri_tc_clear_CTRLA_ENABLE_bit(hw);
hri_tc_set_CTRLA_SWRST_bit(hw);
}
/**
* \brief Start hardware timer
*/
void _timer_start(struct _timer_device *const device)
{
hri_tc_set_CTRLA_ENABLE_bit(device->hw);
}
/**
* \brief Start PWM
*/
@@ -274,13 +205,6 @@ void _tc_start_pwm(struct _pwm_device *const device)
{
hri_tc_set_CTRLA_ENABLE_bit(device->hw);
}
/**
* \brief Stop hardware timer
*/
void _timer_stop(struct _timer_device *const device)
{
hri_tc_clear_CTRLA_ENABLE_bit(device->hw);
}
/**
* \brief Stop PWM
*/
@@ -288,21 +212,6 @@ void _tc_stop_pwm(struct _pwm_device *const device)
{
hri_tc_clear_CTRLA_ENABLE_bit(device->hw);
}
/**
* \brief Set timer period
*/
void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles)
{
void *const hw = device->hw;
if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
hri_tccount32_write_CC_reg(hw, 0, clock_cycles);
} else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
hri_tccount16_write_CC_reg(hw, 0, (uint16_t)clock_cycles);
} else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
hri_tccount8_write_PER_reg(hw, clock_cycles);
}
}
/**
* \brief Set PWM parameter
*/
@@ -355,30 +264,6 @@ uint32_t _tc_pwm_get_duty(const struct _pwm_device *const device)
return ((duty_cycle * 1000) / per);
}
/**
* \brief Retrieve timer period
*/
uint32_t _timer_get_period(const struct _timer_device *const device)
{
void *const hw = device->hw;
if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
return hri_tccount32_read_CC_reg(hw, 0);
} else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
return hri_tccount16_read_CC_reg(hw, 0);
} else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
return hri_tccount8_read_PER_reg(hw);
}
return 0;
}
/**
* \brief Check if timer is running
*/
bool _timer_is_started(const struct _timer_device *const device)
{
return hri_tc_get_CTRLA_ENABLE_bit(device->hw);
}
/**
* \brief Check if PWM is running
*/
@@ -415,33 +300,6 @@ struct _pwm_hpl_interface *_tc_get_pwm(void)
{
return &_tc_pwm_functions;
}
/**
* \brief Set timer IRQ
*
* \param[in] hw The pointer to hardware instance
*/
void _timer_set_irq(struct _timer_device *const device)
{
void *const hw = device->hw;
int8_t i = get_tc_index(hw);
ASSERT(ARRAY_SIZE(_tcs));
_irq_set(_tcs[i].irq);
}
/**
* \internal TC interrupt handler for Timer
*
* \param[in] instance TC instance number
*/
static void tc_interrupt_handler(struct _timer_device *device)
{
void *const hw = device->hw;
if (hri_tc_get_interrupt_OVF_bit(hw)) {
hri_tc_clear_interrupt_OVF_bit(hw);
device->timer_cb.period_expired(device);
}
}
/**
* \internal TC interrupt handler for PWM
*
@@ -465,14 +323,6 @@ static void tc_pwm_interrupt_handler(struct _pwm_device *device)
}
}
/**
* \brief TC interrupt handler
*/
void TC0_Handler(void)
{
tc_interrupt_handler(_tc0_dev);
}
/**
* \brief TC interrupt handler
*/
@@ -508,9 +358,6 @@ static int8_t get_tc_index(const void *const hw)
*/
static void _tc_init_irq_param(const void *const hw, void *dev)
{
if (hw == TC0) {
_tc0_dev = (struct _timer_device *)dev;
}
if (hw == TC3) {
_tc3_dev = (struct _pwm_device *)dev;
}