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Sensor Watch Simulator (#35)

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* Put something on screen

* Use the 32bit watch_date_time repr to pass from JS

* Implement periodic callbacks

* Clear display on enabling

* Hook up watch_set_led_color() to SVG (green-only)

* Make debug output full-width

* Remove default Emscripten canvas

* Implement sleep and button clicks

* Fix time zone conversion bug in beats-time app

* Clean up warnings

* Fix pin levels

* Set time zone to browser value (if available)

* Add basic backup data saving

* Silence format specifier warnings in both targets

* Remove unnecessary, copied files

* Use RTC pointer to clear callbacks (if available)

* Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES

* Change each face to const preprocessor definition

* Remove Intl.DateTimeFormat usage

* Update shell.html title, header

* Add touch start/end event handlers on SVG buttons

* Update shell.html

* Update folder structure (shared, simulator, hardware under watch-library)

* Tease out shared components from watch_slcd

* Clean up simulator watch_slcd.c inline JS calls

* Fix missing newlines at end of file

* Add simulator warnings (except format, unused-paremter)

* Implement remaining watch_rtc functions

* Fix button bug on mouse down then drag out

* Implement remaining watch_slcd functions

* Link keyboard events to buttons (for keys A, L, M)

* Rewrite event handling (mouse, touch, keyboard) in C

* Set explicit text UTF-8 charset in shell.html

* Address PR comments

* Remove unused directories from include paths
This commit is contained in:
Alexsander Akers
2022-01-25 15:03:22 -05:00
committed by GitHub
parent 9e24f6c336
commit b8de35658f
327 changed files with 2303 additions and 570 deletions
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/**
* \file
*
* \brief SAM CCL
*
* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_CCL_COMPONENT_
#ifndef _HRI_CCL_L22_H_INCLUDED_
#define _HRI_CCL_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_CCL_CRITICAL_SECTIONS)
#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define CCL_CRITICAL_SECTION_ENTER()
#define CCL_CRITICAL_SECTION_LEAVE()
#endif
typedef uint32_t hri_ccl_lutctrl_reg_t;
typedef uint8_t hri_ccl_ctrl_reg_t;
typedef uint8_t hri_ccl_seqctrl_reg_t;
static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw)
{
uint8_t tmp;
tmp = ((Ccl *)hw)->CTRL.reg;
tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos;
return (bool)tmp;
}
static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw)
{
uint8_t tmp;
tmp = ((Ccl *)hw)->CTRL.reg;
tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos;
return (bool)tmp;
}
static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value)
{
uint8_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->CTRL.reg;
tmp &= ~CCL_CTRL_ENABLE;
tmp |= value << CCL_CTRL_ENABLE_Pos;
((Ccl *)hw)->CTRL.reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw)
{
uint8_t tmp;
tmp = ((Ccl *)hw)->CTRL.reg;
tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos;
return (bool)tmp;
}
static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value)
{
uint8_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->CTRL.reg;
tmp &= ~CCL_CTRL_RUNSTDBY;
tmp |= value << CCL_CTRL_RUNSTDBY_Pos;
((Ccl *)hw)->CTRL.reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->CTRL.reg |= mask;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
{
uint8_t tmp;
tmp = ((Ccl *)hw)->CTRL.reg;
tmp &= mask;
return tmp;
}
static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->CTRL.reg = data;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->CTRL.reg &= ~mask;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->CTRL.reg ^= mask;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw)
{
return ((Ccl *)hw)->CTRL.reg;
}
static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index,
hri_ccl_seqctrl_reg_t mask)
{
uint8_t tmp;
tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos;
return tmp;
}
static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
{
uint8_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
tmp &= ~CCL_SEQCTRL_SEQSEL_Msk;
tmp |= CCL_SEQCTRL_SEQSEL(data);
((Ccl *)hw)->SEQCTRL[index].reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index)
{
uint8_t tmp;
tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos;
return tmp;
}
static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->SEQCTRL[index].reg |= mask;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index,
hri_ccl_seqctrl_reg_t mask)
{
uint8_t tmp;
tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
tmp &= mask;
return tmp;
}
static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->SEQCTRL[index].reg = data;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->SEQCTRL[index].reg &= ~mask;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->SEQCTRL[index].reg ^= mask;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index)
{
return ((Ccl *)hw)->SEQCTRL[index].reg;
}
static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos;
return (bool)tmp;
}
static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp &= ~CCL_LUTCTRL_ENABLE;
tmp |= value << CCL_LUTCTRL_ENABLE_Pos;
((Ccl *)hw)->LUTCTRL[index].reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos;
return (bool)tmp;
}
static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp &= ~CCL_LUTCTRL_EDGESEL;
tmp |= value << CCL_LUTCTRL_EDGESEL_Pos;
((Ccl *)hw)->LUTCTRL[index].reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos;
return (bool)tmp;
}
static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp &= ~CCL_LUTCTRL_INVEI;
tmp |= value << CCL_LUTCTRL_INVEI_Pos;
((Ccl *)hw)->LUTCTRL[index].reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos;
return (bool)tmp;
}
static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp &= ~CCL_LUTCTRL_LUTEI;
tmp |= value << CCL_LUTCTRL_LUTEI_Pos;
((Ccl *)hw)->LUTCTRL[index].reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos;
return (bool)tmp;
}
static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp &= ~CCL_LUTCTRL_LUTEO;
tmp |= value << CCL_LUTCTRL_LUTEO_Pos;
((Ccl *)hw)->LUTCTRL[index].reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index,
hri_ccl_lutctrl_reg_t mask)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos;
return tmp;
}
static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
{
uint32_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp &= ~CCL_LUTCTRL_FILTSEL_Msk;
tmp |= CCL_LUTCTRL_FILTSEL(data);
((Ccl *)hw)->LUTCTRL[index].reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos;
return tmp;
}
static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index,
hri_ccl_lutctrl_reg_t mask)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos;
return tmp;
}
static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
{
uint32_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp &= ~CCL_LUTCTRL_INSEL0_Msk;
tmp |= CCL_LUTCTRL_INSEL0(data);
((Ccl *)hw)->LUTCTRL[index].reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos;
return tmp;
}
static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index,
hri_ccl_lutctrl_reg_t mask)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos;
return tmp;
}
static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
{
uint32_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp &= ~CCL_LUTCTRL_INSEL1_Msk;
tmp |= CCL_LUTCTRL_INSEL1(data);
((Ccl *)hw)->LUTCTRL[index].reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos;
return tmp;
}
static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index,
hri_ccl_lutctrl_reg_t mask)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos;
return tmp;
}
static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
{
uint32_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp &= ~CCL_LUTCTRL_INSEL2_Msk;
tmp |= CCL_LUTCTRL_INSEL2(data);
((Ccl *)hw)->LUTCTRL[index].reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos;
return tmp;
}
static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index,
hri_ccl_lutctrl_reg_t mask)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos;
return tmp;
}
static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
{
uint32_t tmp;
CCL_CRITICAL_SECTION_ENTER();
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp &= ~CCL_LUTCTRL_TRUTH_Msk;
tmp |= CCL_LUTCTRL_TRUTH(data);
((Ccl *)hw)->LUTCTRL[index].reg = tmp;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask);
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos;
return tmp;
}
static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg |= mask;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index,
hri_ccl_lutctrl_reg_t mask)
{
uint32_t tmp;
tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
tmp &= mask;
return tmp;
}
static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg = data;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg &= ~mask;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
{
CCL_CRITICAL_SECTION_ENTER();
((Ccl *)hw)->LUTCTRL[index].reg ^= mask;
CCL_CRITICAL_SECTION_LEAVE();
}
static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index)
{
return ((Ccl *)hw)->LUTCTRL[index].reg;
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_CCL_L22_H_INCLUDED */
#endif /* _SAML22_CCL_COMPONENT_ */

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/**
* \file
*
* \brief SAM FREQM
*
* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_FREQM_COMPONENT_
#ifndef _HRI_FREQM_L22_H_INCLUDED_
#define _HRI_FREQM_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_FREQM_CRITICAL_SECTIONS)
#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define FREQM_CRITICAL_SECTION_ENTER()
#define FREQM_CRITICAL_SECTION_LEAVE()
#endif
typedef uint16_t hri_freqm_cfga_reg_t;
typedef uint32_t hri_freqm_syncbusy_reg_t;
typedef uint32_t hri_freqm_value_reg_t;
typedef uint8_t hri_freqm_ctrla_reg_t;
typedef uint8_t hri_freqm_ctrlb_reg_t;
typedef uint8_t hri_freqm_intenset_reg_t;
typedef uint8_t hri_freqm_intflag_reg_t;
typedef uint8_t hri_freqm_status_reg_t;
static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg)
{
while (((Freqm *)hw)->SYNCBUSY.reg & reg) {
};
}
static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg)
{
return ((Freqm *)hw)->SYNCBUSY.reg & reg;
}
static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw)
{
return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
}
static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw)
{
((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
}
static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw)
{
return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
}
static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw)
{
((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
}
static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
{
uint8_t tmp;
tmp = ((Freqm *)hw)->INTFLAG.reg;
tmp &= mask;
return tmp;
}
static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw)
{
return ((Freqm *)hw)->INTFLAG.reg;
}
static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
{
((Freqm *)hw)->INTFLAG.reg = mask;
}
static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw)
{
((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
}
static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw)
{
return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos;
}
static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value)
{
if (value == 0x0) {
((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
} else {
((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
}
}
static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw)
{
((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
}
static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
{
((Freqm *)hw)->INTENSET.reg = mask;
}
static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
{
uint8_t tmp;
tmp = ((Freqm *)hw)->INTENSET.reg;
tmp &= mask;
return tmp;
}
static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw)
{
return ((Freqm *)hw)->INTENSET.reg;
}
static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data)
{
((Freqm *)hw)->INTENSET.reg = data;
((Freqm *)hw)->INTENCLR.reg = ~data;
}
static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
{
((Freqm *)hw)->INTENCLR.reg = mask;
}
static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw)
{
return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos;
}
static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
{
return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos;
}
static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask)
{
uint32_t tmp;
tmp = ((Freqm *)hw)->SYNCBUSY.reg;
tmp &= mask;
return tmp;
}
static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw)
{
return ((Freqm *)hw)->SYNCBUSY.reg;
}
static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask)
{
return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos;
}
static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw)
{
return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos;
}
static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask)
{
uint32_t tmp;
tmp = ((Freqm *)hw)->VALUE.reg;
tmp &= mask;
return tmp;
}
static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw)
{
return ((Freqm *)hw)->VALUE.reg;
}
static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw)
{
uint8_t tmp;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
tmp = ((Freqm *)hw)->CTRLA.reg;
tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos;
return (bool)tmp;
}
static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw)
{
uint8_t tmp;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
tmp = ((Freqm *)hw)->CTRLA.reg;
tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos;
return (bool)tmp;
}
static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
{
uint8_t tmp;
FREQM_CRITICAL_SECTION_ENTER();
tmp = ((Freqm *)hw)->CTRLA.reg;
tmp &= ~FREQM_CTRLA_ENABLE;
tmp |= value << FREQM_CTRLA_ENABLE_Pos;
((Freqm *)hw)->CTRLA.reg = tmp;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CTRLA.reg |= mask;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
{
uint8_t tmp;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
tmp = ((Freqm *)hw)->CTRLA.reg;
tmp &= mask;
return tmp;
}
static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CTRLA.reg = data;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CTRLA.reg &= ~mask;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CTRLA.reg ^= mask;
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw)
{
hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
return ((Freqm *)hw)->CTRLA.reg;
}
static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
{
uint16_t tmp;
tmp = ((Freqm *)hw)->CFGA.reg;
tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos;
return tmp;
}
static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data)
{
uint16_t tmp;
FREQM_CRITICAL_SECTION_ENTER();
tmp = ((Freqm *)hw)->CFGA.reg;
tmp &= ~FREQM_CFGA_REFNUM_Msk;
tmp |= FREQM_CFGA_REFNUM(data);
((Freqm *)hw)->CFGA.reg = tmp;
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask);
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw)
{
uint16_t tmp;
tmp = ((Freqm *)hw)->CFGA.reg;
tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos;
return tmp;
}
static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CFGA.reg |= mask;
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
{
uint16_t tmp;
tmp = ((Freqm *)hw)->CFGA.reg;
tmp &= mask;
return tmp;
}
static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CFGA.reg = data;
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CFGA.reg &= ~mask;
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CFGA.reg ^= mask;
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw)
{
return ((Freqm *)hw)->CFGA.reg;
}
static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw)
{
return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos;
}
static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY;
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw)
{
return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos;
}
static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF;
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
{
uint8_t tmp;
tmp = ((Freqm *)hw)->STATUS.reg;
tmp &= mask;
return tmp;
}
static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->STATUS.reg = mask;
FREQM_CRITICAL_SECTION_LEAVE();
}
static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw)
{
return ((Freqm *)hw)->STATUS.reg;
}
static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data)
{
FREQM_CRITICAL_SECTION_ENTER();
((Freqm *)hw)->CTRLB.reg = data;
FREQM_CRITICAL_SECTION_LEAVE();
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_FREQM_L22_H_INCLUDED */
#endif /* _SAML22_FREQM_COMPONENT_ */

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watch-library/hardware/hri/hri_gclk_l22.h Normal file
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/**
* \file
*
* \brief SAM GCLK
*
* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_GCLK_COMPONENT_
#ifndef _HRI_GCLK_L22_H_INCLUDED_
#define _HRI_GCLK_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_GCLK_CRITICAL_SECTIONS)
#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define GCLK_CRITICAL_SECTION_ENTER()
#define GCLK_CRITICAL_SECTION_LEAVE()
#endif
typedef uint32_t hri_gclk_genctrl_reg_t;
typedef uint32_t hri_gclk_pchctrl_reg_t;
typedef uint32_t hri_gclk_syncbusy_reg_t;
typedef uint8_t hri_gclk_ctrla_reg_t;
static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg)
{
while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
};
}
static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg)
{
return ((Gclk *)hw)->SYNCBUSY.reg & reg;
}
static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw)
{
return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos;
}
static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw)
{
return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos;
}
static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw)
{
return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos;
}
static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw)
{
return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos;
}
static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw)
{
return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos;
}
static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw)
{
return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos;
}
static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->SYNCBUSY.reg;
tmp &= mask;
return tmp;
}
static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw)
{
return ((Gclk *)hw)->SYNCBUSY.reg;
}
static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw)
{
uint8_t tmp;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
tmp = ((Gclk *)hw)->CTRLA.reg;
tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos;
return (bool)tmp;
}
static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->CTRLA.reg |= mask;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
{
uint8_t tmp;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
tmp = ((Gclk *)hw)->CTRLA.reg;
tmp &= mask;
return tmp;
}
static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->CTRLA.reg = data;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->CTRLA.reg &= ~mask;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->CTRLA.reg ^= mask;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw)
{
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
return ((Gclk *)hw)->CTRLA.reg;
}
static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos;
return (bool)tmp;
}
static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
GCLK_CRITICAL_SECTION_ENTER();
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp &= ~GCLK_GENCTRL_GENEN;
tmp |= value << GCLK_GENCTRL_GENEN_Pos;
((Gclk *)hw)->GENCTRL[index].reg = tmp;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos;
return (bool)tmp;
}
static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
GCLK_CRITICAL_SECTION_ENTER();
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp &= ~GCLK_GENCTRL_IDC;
tmp |= value << GCLK_GENCTRL_IDC_Pos;
((Gclk *)hw)->GENCTRL[index].reg = tmp;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos;
return (bool)tmp;
}
static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
GCLK_CRITICAL_SECTION_ENTER();
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp &= ~GCLK_GENCTRL_OOV;
tmp |= value << GCLK_GENCTRL_OOV_Pos;
((Gclk *)hw)->GENCTRL[index].reg = tmp;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos;
return (bool)tmp;
}
static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
GCLK_CRITICAL_SECTION_ENTER();
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp &= ~GCLK_GENCTRL_OE;
tmp |= value << GCLK_GENCTRL_OE_Pos;
((Gclk *)hw)->GENCTRL[index].reg = tmp;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos;
return (bool)tmp;
}
static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
GCLK_CRITICAL_SECTION_ENTER();
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp &= ~GCLK_GENCTRL_DIVSEL;
tmp |= value << GCLK_GENCTRL_DIVSEL_Pos;
((Gclk *)hw)->GENCTRL[index].reg = tmp;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos;
return (bool)tmp;
}
static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
GCLK_CRITICAL_SECTION_ENTER();
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp &= ~GCLK_GENCTRL_RUNSTDBY;
tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos;
((Gclk *)hw)->GENCTRL[index].reg = tmp;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask);
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index,
hri_gclk_genctrl_reg_t mask)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos;
return tmp;
}
static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
{
uint32_t tmp;
GCLK_CRITICAL_SECTION_ENTER();
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp &= ~GCLK_GENCTRL_SRC_Msk;
tmp |= GCLK_GENCTRL_SRC(data);
((Gclk *)hw)->GENCTRL[index].reg = tmp;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask);
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask);
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos;
return tmp;
}
static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask);
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index,
hri_gclk_genctrl_reg_t mask)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos;
return tmp;
}
static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
{
uint32_t tmp;
GCLK_CRITICAL_SECTION_ENTER();
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp &= ~GCLK_GENCTRL_DIV_Msk;
tmp |= GCLK_GENCTRL_DIV(data);
((Gclk *)hw)->GENCTRL[index].reg = tmp;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask);
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask);
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos;
return tmp;
}
static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg |= mask;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index,
hri_gclk_genctrl_reg_t mask)
{
uint32_t tmp;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
tmp &= mask;
return tmp;
}
static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg = data;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg &= ~mask;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg ^= mask;
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index)
{
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
return ((Gclk *)hw)->GENCTRL[index].reg;
}
static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos;
return (bool)tmp;
}
static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
GCLK_CRITICAL_SECTION_ENTER();
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
tmp &= ~GCLK_PCHCTRL_CHEN;
tmp |= value << GCLK_PCHCTRL_CHEN_Pos;
((Gclk *)hw)->PCHCTRL[index].reg = tmp;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos;
return (bool)tmp;
}
static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value)
{
uint32_t tmp;
GCLK_CRITICAL_SECTION_ENTER();
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
tmp &= ~GCLK_PCHCTRL_WRTLOCK;
tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos;
((Gclk *)hw)->PCHCTRL[index].reg = tmp;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index,
hri_gclk_pchctrl_reg_t mask)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos;
return tmp;
}
static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
{
uint32_t tmp;
GCLK_CRITICAL_SECTION_ENTER();
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
tmp &= ~GCLK_PCHCTRL_GEN_Msk;
tmp |= GCLK_PCHCTRL_GEN(data);
((Gclk *)hw)->PCHCTRL[index].reg = tmp;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask);
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos;
return tmp;
}
static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg |= mask;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index,
hri_gclk_pchctrl_reg_t mask)
{
uint32_t tmp;
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
tmp &= mask;
return tmp;
}
static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg = data;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg &= ~mask;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg ^= mask;
GCLK_CRITICAL_SECTION_LEAVE();
}
static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index)
{
return ((Gclk *)hw)->PCHCTRL[index].reg;
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_GCLK_L22_H_INCLUDED */
#endif /* _SAML22_GCLK_COMPONENT_ */

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/**
* \file
*
* \brief SAM L22 HRI top-level header file
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HRI_L22_H_INCLUDED_
#define _HRI_L22_H_INCLUDED_
#include <sam.h>
#include <hri_ac_l22.h>
#include <hri_adc_l22.h>
#include <hri_aes_l22.h>
#include <hri_ccl_l22.h>
#include <hri_dmac_l22.h>
#include <hri_dsu_l22.h>
#include <hri_eic_l22.h>
#include <hri_evsys_l22.h>
#include <hri_freqm_l22.h>
#include <hri_gclk_l22.h>
#include <hri_mclk_l22.h>
#include <hri_mtb_l22.h>
#include <hri_nvic_l22.h>
#include <hri_nvmctrl_l22.h>
#include <hri_osc32kctrl_l22.h>
#include <hri_oscctrl_l22.h>
#include <hri_pac_l22.h>
#include <hri_pm_l22.h>
#include <hri_port_l22.h>
#include <hri_rstc_l22.h>
#include <hri_rtc_l22.h>
#include <hri_sercom_l22.h>
#include <hri_slcd_l22.h>
#include <hri_supc_l22.h>
#include <hri_systemcontrol_l22.h>
#include <hri_systick_l22.h>
#include <hri_tc_l22.h>
#include <hri_tcc_l22.h>
#include <hri_trng_l22.h>
#include <hri_usb_l22.h>
#include <hri_wdt_l22.h>
#endif /* _HRI_L22_H_INCLUDED_ */

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/**
* \file
*
* \brief SAM MTB
*
* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_MTB_COMPONENT_
#ifndef _HRI_MTB_L22_H_INCLUDED_
#define _HRI_MTB_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_MTB_CRITICAL_SECTIONS)
#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define MTB_CRITICAL_SECTION_ENTER()
#define MTB_CRITICAL_SECTION_LEAVE()
#endif
typedef uint32_t hri_mtb_authstatus_reg_t;
typedef uint32_t hri_mtb_base_reg_t;
typedef uint32_t hri_mtb_cid0_reg_t;
typedef uint32_t hri_mtb_cid1_reg_t;
typedef uint32_t hri_mtb_cid2_reg_t;
typedef uint32_t hri_mtb_cid3_reg_t;
typedef uint32_t hri_mtb_claimset_reg_t;
typedef uint32_t hri_mtb_devarch_reg_t;
typedef uint32_t hri_mtb_devid_reg_t;
typedef uint32_t hri_mtb_devtype_reg_t;
typedef uint32_t hri_mtb_flow_reg_t;
typedef uint32_t hri_mtb_itctrl_reg_t;
typedef uint32_t hri_mtb_lockaccess_reg_t;
typedef uint32_t hri_mtb_lockstatus_reg_t;
typedef uint32_t hri_mtb_master_reg_t;
typedef uint32_t hri_mtb_pid0_reg_t;
typedef uint32_t hri_mtb_pid1_reg_t;
typedef uint32_t hri_mtb_pid2_reg_t;
typedef uint32_t hri_mtb_pid3_reg_t;
typedef uint32_t hri_mtb_pid4_reg_t;
typedef uint32_t hri_mtb_pid5_reg_t;
typedef uint32_t hri_mtb_pid6_reg_t;
typedef uint32_t hri_mtb_pid7_reg_t;
typedef uint32_t hri_mtb_position_reg_t;
static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
{
((Mtb *)hw)->CLAIMSET.reg = mask;
}
static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->CLAIMSET.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw)
{
return ((Mtb *)hw)->CLAIMSET.reg;
}
static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data)
{
((Mtb *)hw)->CLAIMSET.reg = data;
((Mtb *)hw)->CLAIMCLR.reg = ~data;
}
static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
{
((Mtb *)hw)->CLAIMCLR.reg = mask;
}
static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->BASE.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw)
{
return ((Mtb *)hw)->BASE.reg;
}
static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->LOCKSTATUS.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw)
{
return ((Mtb *)hw)->LOCKSTATUS.reg;
}
static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->AUTHSTATUS.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw)
{
return ((Mtb *)hw)->AUTHSTATUS.reg;
}
static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->DEVARCH.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw)
{
return ((Mtb *)hw)->DEVARCH.reg;
}
static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->DEVID.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw)
{
return ((Mtb *)hw)->DEVID.reg;
}
static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->DEVTYPE.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw)
{
return ((Mtb *)hw)->DEVTYPE.reg;
}
static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->PID4.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw)
{
return ((Mtb *)hw)->PID4.reg;
}
static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->PID5.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw)
{
return ((Mtb *)hw)->PID5.reg;
}
static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->PID6.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw)
{
return ((Mtb *)hw)->PID6.reg;
}
static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->PID7.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw)
{
return ((Mtb *)hw)->PID7.reg;
}
static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->PID0.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw)
{
return ((Mtb *)hw)->PID0.reg;
}
static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->PID1.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw)
{
return ((Mtb *)hw)->PID1.reg;
}
static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->PID2.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw)
{
return ((Mtb *)hw)->PID2.reg;
}
static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->PID3.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw)
{
return ((Mtb *)hw)->PID3.reg;
}
static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->CID0.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw)
{
return ((Mtb *)hw)->CID0.reg;
}
static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->CID1.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw)
{
return ((Mtb *)hw)->CID1.reg;
}
static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->CID2.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw)
{
return ((Mtb *)hw)->CID2.reg;
}
static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->CID3.reg;
tmp &= mask;
return tmp;
}
static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw)
{
return ((Mtb *)hw)->CID3.reg;
}
static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->POSITION.reg |= mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->POSITION.reg;
tmp &= mask;
return tmp;
}
static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->POSITION.reg = data;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->POSITION.reg &= ~mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->POSITION.reg ^= mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw)
{
return ((Mtb *)hw)->POSITION.reg;
}
static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->MASTER.reg |= mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->MASTER.reg;
tmp &= mask;
return tmp;
}
static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->MASTER.reg = data;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->MASTER.reg &= ~mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->MASTER.reg ^= mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw)
{
return ((Mtb *)hw)->MASTER.reg;
}
static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->FLOW.reg |= mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->FLOW.reg;
tmp &= mask;
return tmp;
}
static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->FLOW.reg = data;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->FLOW.reg &= ~mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->FLOW.reg ^= mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw)
{
return ((Mtb *)hw)->FLOW.reg;
}
static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->ITCTRL.reg |= mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->ITCTRL.reg;
tmp &= mask;
return tmp;
}
static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->ITCTRL.reg = data;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->ITCTRL.reg &= ~mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->ITCTRL.reg ^= mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw)
{
return ((Mtb *)hw)->ITCTRL.reg;
}
static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->LOCKACCESS.reg |= mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
{
uint32_t tmp;
tmp = ((Mtb *)hw)->LOCKACCESS.reg;
tmp &= mask;
return tmp;
}
static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->LOCKACCESS.reg = data;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->LOCKACCESS.reg &= ~mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
{
MTB_CRITICAL_SECTION_ENTER();
((Mtb *)hw)->LOCKACCESS.reg ^= mask;
MTB_CRITICAL_SECTION_LEAVE();
}
static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw)
{
return ((Mtb *)hw)->LOCKACCESS.reg;
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_MTB_L22_H_INCLUDED */
#endif /* _SAML22_MTB_COMPONENT_ */

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/**
* \file
*
* \brief SAM NVIC
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_NVIC_COMPONENT_
#ifndef _HRI_NVIC_L22_H_INCLUDED_
#define _HRI_NVIC_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_NVIC_CRITICAL_SECTIONS)
#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define NVIC_CRITICAL_SECTION_ENTER()
#define NVIC_CRITICAL_SECTION_LEAVE()
#endif
typedef uint32_t hri_nvic_icer_reg_t;
typedef uint32_t hri_nvic_icpr_reg_t;
typedef uint32_t hri_nvic_ipr_reg_t;
typedef uint32_t hri_nvic_iser_reg_t;
typedef uint32_t hri_nvic_ispr_reg_t;
static inline void hri_nvic_set_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISER.reg |= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
{
uint32_t tmp;
tmp = ((Nvic *)hw)->ISER.reg;
tmp &= mask;
return tmp;
}
static inline void hri_nvic_write_ISER_reg(const void *const hw, hri_nvic_iser_reg_t data)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISER.reg = data;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_clear_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISER.reg &= ~mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_toggle_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISER.reg ^= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw)
{
return ((Nvic *)hw)->ISER.reg;
}
static inline void hri_nvic_set_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICER.reg |= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
{
uint32_t tmp;
tmp = ((Nvic *)hw)->ICER.reg;
tmp &= mask;
return tmp;
}
static inline void hri_nvic_write_ICER_reg(const void *const hw, hri_nvic_icer_reg_t data)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICER.reg = data;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_clear_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICER.reg &= ~mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_toggle_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICER.reg ^= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw)
{
return ((Nvic *)hw)->ICER.reg;
}
static inline void hri_nvic_set_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISPR.reg |= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
{
uint32_t tmp;
tmp = ((Nvic *)hw)->ISPR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_nvic_write_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t data)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISPR.reg = data;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_clear_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISPR.reg &= ~mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISPR.reg ^= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw)
{
return ((Nvic *)hw)->ISPR.reg;
}
static inline void hri_nvic_set_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICPR.reg |= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
{
uint32_t tmp;
tmp = ((Nvic *)hw)->ICPR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_nvic_write_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t data)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICPR.reg = data;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_clear_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICPR.reg &= ~mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICPR.reg ^= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw)
{
return ((Nvic *)hw)->ICPR.reg;
}
static inline void hri_nvic_set_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->IPR[index].reg |= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_ipr_reg_t hri_nvic_get_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
{
uint32_t tmp;
tmp = ((Nvic *)hw)->IPR[index].reg;
tmp &= mask;
return tmp;
}
static inline void hri_nvic_write_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t data)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->IPR[index].reg = data;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_clear_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->IPR[index].reg &= ~mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_toggle_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->IPR[index].reg ^= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_ipr_reg_t hri_nvic_read_IPR_reg(const void *const hw, uint8_t index)
{
return ((Nvic *)hw)->IPR[index].reg;
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_NVIC_L22_H_INCLUDED */
#endif /* _SAML22_NVIC_COMPONENT_ */

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/**
* \file
*
* \brief SAM PM
*
* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_PM_COMPONENT_
#ifndef _HRI_PM_L22_H_INCLUDED_
#define _HRI_PM_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_PM_CRITICAL_SECTIONS)
#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define PM_CRITICAL_SECTION_ENTER()
#define PM_CRITICAL_SECTION_LEAVE()
#endif
typedef uint16_t hri_pm_stdbycfg_reg_t;
typedef uint8_t hri_pm_ctrla_reg_t;
typedef uint8_t hri_pm_intenset_reg_t;
typedef uint8_t hri_pm_intflag_reg_t;
typedef uint8_t hri_pm_plcfg_reg_t;
typedef uint8_t hri_pm_sleepcfg_reg_t;
static inline bool hri_pm_get_INTFLAG_PLRDY_bit(const void *const hw)
{
return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos;
}
static inline void hri_pm_clear_INTFLAG_PLRDY_bit(const void *const hw)
{
((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY;
}
static inline bool hri_pm_get_interrupt_PLRDY_bit(const void *const hw)
{
return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos;
}
static inline void hri_pm_clear_interrupt_PLRDY_bit(const void *const hw)
{
((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY;
}
static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
{
uint8_t tmp;
tmp = ((Pm *)hw)->INTFLAG.reg;
tmp &= mask;
return tmp;
}
static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw)
{
return ((Pm *)hw)->INTFLAG.reg;
}
static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
{
((Pm *)hw)->INTFLAG.reg = mask;
}
static inline void hri_pm_set_INTEN_PLRDY_bit(const void *const hw)
{
((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY;
}
static inline bool hri_pm_get_INTEN_PLRDY_bit(const void *const hw)
{
return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_PLRDY) >> PM_INTENSET_PLRDY_Pos;
}
static inline void hri_pm_write_INTEN_PLRDY_bit(const void *const hw, bool value)
{
if (value == 0x0) {
((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY;
} else {
((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY;
}
}
static inline void hri_pm_clear_INTEN_PLRDY_bit(const void *const hw)
{
((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY;
}
static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
{
((Pm *)hw)->INTENSET.reg = mask;
}
static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
{
uint8_t tmp;
tmp = ((Pm *)hw)->INTENSET.reg;
tmp &= mask;
return tmp;
}
static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw)
{
return ((Pm *)hw)->INTENSET.reg;
}
static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data)
{
((Pm *)hw)->INTENSET.reg = data;
((Pm *)hw)->INTENCLR.reg = ~data;
}
static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
{
((Pm *)hw)->INTENCLR.reg = mask;
}
static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET;
PM_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw)
{
uint8_t tmp;
tmp = ((Pm *)hw)->CTRLA.reg;
tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos;
return (bool)tmp;
}
static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value)
{
uint8_t tmp;
PM_CRITICAL_SECTION_ENTER();
tmp = ((Pm *)hw)->CTRLA.reg;
tmp &= ~PM_CTRLA_IORET;
tmp |= value << PM_CTRLA_IORET_Pos;
((Pm *)hw)->CTRLA.reg = tmp;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->CTRLA.reg |= mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
{
uint8_t tmp;
tmp = ((Pm *)hw)->CTRLA.reg;
tmp &= mask;
return tmp;
}
static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->CTRLA.reg = data;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->CTRLA.reg &= ~mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->CTRLA.reg ^= mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw)
{
return ((Pm *)hw)->CTRLA.reg;
}
static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
{
uint8_t tmp;
tmp = ((Pm *)hw)->SLEEPCFG.reg;
tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos;
return tmp;
}
static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data)
{
uint8_t tmp;
PM_CRITICAL_SECTION_ENTER();
tmp = ((Pm *)hw)->SLEEPCFG.reg;
tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk;
tmp |= PM_SLEEPCFG_SLEEPMODE(data);
((Pm *)hw)->SLEEPCFG.reg = tmp;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw)
{
uint8_t tmp;
tmp = ((Pm *)hw)->SLEEPCFG.reg;
tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos;
return tmp;
}
static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->SLEEPCFG.reg |= mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
{
uint8_t tmp;
tmp = ((Pm *)hw)->SLEEPCFG.reg;
tmp &= mask;
return tmp;
}
static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->SLEEPCFG.reg = data;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->SLEEPCFG.reg &= ~mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->SLEEPCFG.reg ^= mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw)
{
return ((Pm *)hw)->SLEEPCFG.reg;
}
static inline void hri_pm_set_PLCFG_PLDIS_bit(const void *const hw)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLDIS;
PM_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_pm_get_PLCFG_PLDIS_bit(const void *const hw)
{
uint8_t tmp;
tmp = ((Pm *)hw)->PLCFG.reg;
tmp = (tmp & PM_PLCFG_PLDIS) >> PM_PLCFG_PLDIS_Pos;
return (bool)tmp;
}
static inline void hri_pm_write_PLCFG_PLDIS_bit(const void *const hw, bool value)
{
uint8_t tmp;
PM_CRITICAL_SECTION_ENTER();
tmp = ((Pm *)hw)->PLCFG.reg;
tmp &= ~PM_PLCFG_PLDIS;
tmp |= value << PM_PLCFG_PLDIS_Pos;
((Pm *)hw)->PLCFG.reg = tmp;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_clear_PLCFG_PLDIS_bit(const void *const hw)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLDIS;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_toggle_PLCFG_PLDIS_bit(const void *const hw)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLDIS;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_set_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLSEL(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
{
uint8_t tmp;
tmp = ((Pm *)hw)->PLCFG.reg;
tmp = (tmp & PM_PLCFG_PLSEL(mask)) >> PM_PLCFG_PLSEL_Pos;
return tmp;
}
static inline void hri_pm_write_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t data)
{
uint8_t tmp;
PM_CRITICAL_SECTION_ENTER();
tmp = ((Pm *)hw)->PLCFG.reg;
tmp &= ~PM_PLCFG_PLSEL_Msk;
tmp |= PM_PLCFG_PLSEL(data);
((Pm *)hw)->PLCFG.reg = tmp;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_clear_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLSEL(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_toggle_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLSEL(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_PLSEL_bf(const void *const hw)
{
uint8_t tmp;
tmp = ((Pm *)hw)->PLCFG.reg;
tmp = (tmp & PM_PLCFG_PLSEL_Msk) >> PM_PLCFG_PLSEL_Pos;
return tmp;
}
static inline void hri_pm_set_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->PLCFG.reg |= mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
{
uint8_t tmp;
tmp = ((Pm *)hw)->PLCFG.reg;
tmp &= mask;
return tmp;
}
static inline void hri_pm_write_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t data)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->PLCFG.reg = data;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_clear_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->PLCFG.reg &= ~mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_toggle_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->PLCFG.reg ^= mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_reg(const void *const hw)
{
return ((Pm *)hw)->PLCFG.reg;
}
static inline void hri_pm_set_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_VREGSMOD(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
uint16_t tmp;
tmp = ((Pm *)hw)->STDBYCFG.reg;
tmp = (tmp & PM_STDBYCFG_VREGSMOD(mask)) >> PM_STDBYCFG_VREGSMOD_Pos;
return tmp;
}
static inline void hri_pm_write_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
{
uint16_t tmp;
PM_CRITICAL_SECTION_ENTER();
tmp = ((Pm *)hw)->STDBYCFG.reg;
tmp &= ~PM_STDBYCFG_VREGSMOD_Msk;
tmp |= PM_STDBYCFG_VREGSMOD(data);
((Pm *)hw)->STDBYCFG.reg = tmp;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_clear_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_VREGSMOD(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_toggle_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_VREGSMOD(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_VREGSMOD_bf(const void *const hw)
{
uint16_t tmp;
tmp = ((Pm *)hw)->STDBYCFG.reg;
tmp = (tmp & PM_STDBYCFG_VREGSMOD_Msk) >> PM_STDBYCFG_VREGSMOD_Pos;
return tmp;
}
static inline void hri_pm_set_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASHS(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
uint16_t tmp;
tmp = ((Pm *)hw)->STDBYCFG.reg;
tmp = (tmp & PM_STDBYCFG_BBIASHS(mask)) >> PM_STDBYCFG_BBIASHS_Pos;
return tmp;
}
static inline void hri_pm_write_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
{
uint16_t tmp;
PM_CRITICAL_SECTION_ENTER();
tmp = ((Pm *)hw)->STDBYCFG.reg;
tmp &= ~PM_STDBYCFG_BBIASHS_Msk;
tmp |= PM_STDBYCFG_BBIASHS(data);
((Pm *)hw)->STDBYCFG.reg = tmp;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_clear_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASHS(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_toggle_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASHS(mask);
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASHS_bf(const void *const hw)
{
uint16_t tmp;
tmp = ((Pm *)hw)->STDBYCFG.reg;
tmp = (tmp & PM_STDBYCFG_BBIASHS_Msk) >> PM_STDBYCFG_BBIASHS_Pos;
return tmp;
}
static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->STDBYCFG.reg |= mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
uint16_t tmp;
tmp = ((Pm *)hw)->STDBYCFG.reg;
tmp &= mask;
return tmp;
}
static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->STDBYCFG.reg = data;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->STDBYCFG.reg &= ~mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->STDBYCFG.reg ^= mask;
PM_CRITICAL_SECTION_LEAVE();
}
static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw)
{
return ((Pm *)hw)->STDBYCFG.reg;
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_PM_L22_H_INCLUDED */
#endif /* _SAML22_PM_COMPONENT_ */

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watch-library/hardware/hri/hri_rstc_l22.h Normal file
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/**
* \file
*
* \brief SAM RSTC
*
* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_RSTC_COMPONENT_
#ifndef _HRI_RSTC_L22_H_INCLUDED_
#define _HRI_RSTC_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_RSTC_CRITICAL_SECTIONS)
#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define RSTC_CRITICAL_SECTION_ENTER()
#define RSTC_CRITICAL_SECTION_LEAVE()
#endif
typedef uint8_t hri_rstc_bkupexit_reg_t;
typedef uint8_t hri_rstc_rcause_reg_t;
static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw)
{
return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos;
}
static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw)
{
return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos;
}
static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw)
{
return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos;
}
static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw)
{
return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos;
}
static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw)
{
return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos;
}
static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw)
{
return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos;
}
static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw)
{
return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos;
}
static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask)
{
uint8_t tmp;
tmp = ((Rstc *)hw)->RCAUSE.reg;
tmp &= mask;
return tmp;
}
static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw)
{
return ((Rstc *)hw)->RCAUSE.reg;
}
static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw)
{
return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos;
}
static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw)
{
return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos;
}
static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask)
{
uint8_t tmp;
tmp = ((Rstc *)hw)->BKUPEXIT.reg;
tmp &= mask;
return tmp;
}
static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw)
{
return ((Rstc *)hw)->BKUPEXIT.reg;
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_RSTC_L22_H_INCLUDED */
#endif /* _SAML22_RSTC_COMPONENT_ */

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/**
* \file
*
* \brief SAM SystemControl
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_SystemControl_COMPONENT_
#ifndef _HRI_SystemControl_L22_H_INCLUDED_
#define _HRI_SystemControl_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS)
#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define SystemControl_CRITICAL_SECTION_ENTER()
#define SystemControl_CRITICAL_SECTION_LEAVE()
#endif
typedef uint32_t hri_systemcontrol_aircr_reg_t;
typedef uint32_t hri_systemcontrol_ccr_reg_t;
typedef uint32_t hri_systemcontrol_cpuid_reg_t;
typedef uint32_t hri_systemcontrol_dfsr_reg_t;
typedef uint32_t hri_systemcontrol_icsr_reg_t;
typedef uint32_t hri_systemcontrol_scr_reg_t;
typedef uint32_t hri_systemcontrol_shcsr_reg_t;
typedef uint32_t hri_systemcontrol_shpr2_reg_t;
typedef uint32_t hri_systemcontrol_shpr3_reg_t;
typedef uint32_t hri_systemcontrol_vtor_reg_t;
static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw,
hri_systemcontrol_cpuid_reg_t mask)
{
return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0;
}
static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw)
{
return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0;
}
static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw,
hri_systemcontrol_cpuid_reg_t mask)
{
return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4;
}
static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw)
{
return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4;
}
static inline hri_systemcontrol_cpuid_reg_t
hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
{
return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16;
}
static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw)
{
return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16;
}
static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw,
hri_systemcontrol_cpuid_reg_t mask)
{
return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20;
}
static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw)
{
return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20;
}
static inline hri_systemcontrol_cpuid_reg_t
hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
{
return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24;
}
static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw)
{
return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24;
}
static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw,
hri_systemcontrol_cpuid_reg_t mask)
{
uint32_t tmp;
tmp = ((Systemcontrol *)hw)->CPUID.reg;
tmp &= mask;
return tmp;
}
static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw)
{
return ((Systemcontrol *)hw)->CPUID.reg;
}
static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw)
{
return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_UNALIGN_TRP) >> 3;
}
static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw)
{
return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_STKALIGN) >> 9;
}
static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw,
hri_systemcontrol_ccr_reg_t mask)
{
uint32_t tmp;
tmp = ((Systemcontrol *)hw)->CCR.reg;
tmp &= mask;
return tmp;
}
static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw)
{
return ((Systemcontrol *)hw)->CCR.reg;
}
static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->ICSR.reg |= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw,
hri_systemcontrol_icsr_reg_t mask)
{
uint32_t tmp;
tmp = ((Systemcontrol *)hw)->ICSR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->ICSR.reg = data;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->ICSR.reg &= ~mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->ICSR.reg ^= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw)
{
return ((Systemcontrol *)hw)->ICSR.reg;
}
static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->VTOR.reg |= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw,
hri_systemcontrol_vtor_reg_t mask)
{
uint32_t tmp;
tmp = ((Systemcontrol *)hw)->VTOR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->VTOR.reg = data;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->VTOR.reg &= ~mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->VTOR.reg ^= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw)
{
return ((Systemcontrol *)hw)->VTOR.reg;
}
static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->AIRCR.reg |= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw,
hri_systemcontrol_aircr_reg_t mask)
{
uint32_t tmp;
tmp = ((Systemcontrol *)hw)->AIRCR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->AIRCR.reg = data;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->AIRCR.reg &= ~mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->AIRCR.reg ^= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw)
{
return ((Systemcontrol *)hw)->AIRCR.reg;
}
static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SCR.reg |= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw,
hri_systemcontrol_scr_reg_t mask)
{
uint32_t tmp;
tmp = ((Systemcontrol *)hw)->SCR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SCR.reg = data;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SCR.reg &= ~mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SCR.reg ^= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw)
{
return ((Systemcontrol *)hw)->SCR.reg;
}
static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHPR2.reg |= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw,
hri_systemcontrol_shpr2_reg_t mask)
{
uint32_t tmp;
tmp = ((Systemcontrol *)hw)->SHPR2.reg;
tmp &= mask;
return tmp;
}
static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHPR2.reg = data;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHPR2.reg &= ~mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHPR2.reg ^= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw)
{
return ((Systemcontrol *)hw)->SHPR2.reg;
}
static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHPR3.reg |= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw,
hri_systemcontrol_shpr3_reg_t mask)
{
uint32_t tmp;
tmp = ((Systemcontrol *)hw)->SHPR3.reg;
tmp &= mask;
return tmp;
}
static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHPR3.reg = data;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHPR3.reg &= ~mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHPR3.reg ^= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw)
{
return ((Systemcontrol *)hw)->SHPR3.reg;
}
static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHCSR.reg |= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const hw,
hri_systemcontrol_shcsr_reg_t mask)
{
uint32_t tmp;
tmp = ((Systemcontrol *)hw)->SHCSR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHCSR.reg = data;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHCSR.reg &= ~mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->SHCSR.reg ^= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw)
{
return ((Systemcontrol *)hw)->SHCSR.reg;
}
static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->DFSR.reg |= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const hw,
hri_systemcontrol_dfsr_reg_t mask)
{
uint32_t tmp;
tmp = ((Systemcontrol *)hw)->DFSR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->DFSR.reg = data;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->DFSR.reg &= ~mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
{
SystemControl_CRITICAL_SECTION_ENTER();
((Systemcontrol *)hw)->DFSR.reg ^= mask;
SystemControl_CRITICAL_SECTION_LEAVE();
}
static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw)
{
return ((Systemcontrol *)hw)->DFSR.reg;
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_SystemControl_L22_H_INCLUDED */
#endif /* _SAML22_SystemControl_COMPONENT_ */

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/**
* \file
*
* \brief SAM SysTick
*
* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_SysTick_COMPONENT_
#ifndef _HRI_SysTick_L22_H_INCLUDED_
#define _HRI_SysTick_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_SysTick_CRITICAL_SECTIONS)
#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define SysTick_CRITICAL_SECTION_ENTER()
#define SysTick_CRITICAL_SECTION_LEAVE()
#endif
typedef uint32_t hri_systick_calib_reg_t;
typedef uint32_t hri_systick_csr_reg_t;
typedef uint32_t hri_systick_cvr_reg_t;
typedef uint32_t hri_systick_rvr_reg_t;
static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw)
{
return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_SKEW) >> 30;
}
static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw)
{
return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_NOREF) >> 31;
}
static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask)
{
return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS(mask)) >> 0;
}
static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw)
{
return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS_Msk) >> 0;
}
static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask)
{
uint32_t tmp;
tmp = ((Systick *)hw)->CALIB.reg;
tmp &= mask;
return tmp;
}
static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw)
{
return ((Systick *)hw)->CALIB.reg;
}
static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->CSR.reg |= mask;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
{
uint32_t tmp;
tmp = ((Systick *)hw)->CSR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->CSR.reg = data;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->CSR.reg &= ~mask;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->CSR.reg ^= mask;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw)
{
return ((Systick *)hw)->CSR.reg;
}
static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->RVR.reg |= mask;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
{
uint32_t tmp;
tmp = ((Systick *)hw)->RVR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->RVR.reg = data;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->RVR.reg &= ~mask;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->RVR.reg ^= mask;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw)
{
return ((Systick *)hw)->RVR.reg;
}
static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->CVR.reg |= mask;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
{
uint32_t tmp;
tmp = ((Systick *)hw)->CVR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->CVR.reg = data;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->CVR.reg &= ~mask;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
{
SysTick_CRITICAL_SECTION_ENTER();
((Systick *)hw)->CVR.reg ^= mask;
SysTick_CRITICAL_SECTION_LEAVE();
}
static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw)
{
return ((Systick *)hw)->CVR.reg;
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_SysTick_L22_H_INCLUDED */
#endif /* _SAML22_SysTick_COMPONENT_ */

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/**
* \file
*
* \brief SAM TRNG
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_TRNG_COMPONENT_
#ifndef _HRI_TRNG_L22_H_INCLUDED_
#define _HRI_TRNG_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_TRNG_CRITICAL_SECTIONS)
#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define TRNG_CRITICAL_SECTION_ENTER()
#define TRNG_CRITICAL_SECTION_LEAVE()
#endif
typedef uint32_t hri_trng_data_reg_t;
typedef uint8_t hri_trng_ctrla_reg_t;
typedef uint8_t hri_trng_evctrl_reg_t;
typedef uint8_t hri_trng_intenset_reg_t;
typedef uint8_t hri_trng_intflag_reg_t;
static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw)
{
return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
}
static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw)
{
((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
}
static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw)
{
return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
}
static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw)
{
((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
}
static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
{
uint8_t tmp;
tmp = ((Trng *)hw)->INTFLAG.reg;
tmp &= mask;
return tmp;
}
static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw)
{
return ((Trng *)hw)->INTFLAG.reg;
}
static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
{
((Trng *)hw)->INTFLAG.reg = mask;
}
static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw)
{
((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
}
static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw)
{
return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos;
}
static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value)
{
if (value == 0x0) {
((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
} else {
((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
}
}
static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw)
{
((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
}
static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
{
((Trng *)hw)->INTENSET.reg = mask;
}
static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
{
uint8_t tmp;
tmp = ((Trng *)hw)->INTENSET.reg;
tmp &= mask;
return tmp;
}
static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw)
{
return ((Trng *)hw)->INTENSET.reg;
}
static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data)
{
((Trng *)hw)->INTENSET.reg = data;
((Trng *)hw)->INTENCLR.reg = ~data;
}
static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
{
((Trng *)hw)->INTENCLR.reg = mask;
}
static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask)
{
return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos;
}
static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw)
{
return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos;
}
static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask)
{
uint32_t tmp;
tmp = ((Trng *)hw)->DATA.reg;
tmp &= mask;
return tmp;
}
static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw)
{
return ((Trng *)hw)->DATA.reg;
}
static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw)
{
uint8_t tmp;
tmp = ((Trng *)hw)->CTRLA.reg;
tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos;
return (bool)tmp;
}
static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
{
uint8_t tmp;
TRNG_CRITICAL_SECTION_ENTER();
tmp = ((Trng *)hw)->CTRLA.reg;
tmp &= ~TRNG_CTRLA_ENABLE;
tmp |= value << TRNG_CTRLA_ENABLE_Pos;
((Trng *)hw)->CTRLA.reg = tmp;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw)
{
uint8_t tmp;
tmp = ((Trng *)hw)->CTRLA.reg;
tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos;
return (bool)tmp;
}
static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
{
uint8_t tmp;
TRNG_CRITICAL_SECTION_ENTER();
tmp = ((Trng *)hw)->CTRLA.reg;
tmp &= ~TRNG_CTRLA_RUNSTDBY;
tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos;
((Trng *)hw)->CTRLA.reg = tmp;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->CTRLA.reg |= mask;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
{
uint8_t tmp;
tmp = ((Trng *)hw)->CTRLA.reg;
tmp &= mask;
return tmp;
}
static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->CTRLA.reg = data;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->CTRLA.reg &= ~mask;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->CTRLA.reg ^= mask;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw)
{
return ((Trng *)hw)->CTRLA.reg;
}
static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw)
{
uint8_t tmp;
tmp = ((Trng *)hw)->EVCTRL.reg;
tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos;
return (bool)tmp;
}
static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value)
{
uint8_t tmp;
TRNG_CRITICAL_SECTION_ENTER();
tmp = ((Trng *)hw)->EVCTRL.reg;
tmp &= ~TRNG_EVCTRL_DATARDYEO;
tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos;
((Trng *)hw)->EVCTRL.reg = tmp;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->EVCTRL.reg |= mask;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
{
uint8_t tmp;
tmp = ((Trng *)hw)->EVCTRL.reg;
tmp &= mask;
return tmp;
}
static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->EVCTRL.reg = data;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->EVCTRL.reg &= ~mask;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
{
TRNG_CRITICAL_SECTION_ENTER();
((Trng *)hw)->EVCTRL.reg ^= mask;
TRNG_CRITICAL_SECTION_LEAVE();
}
static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw)
{
return ((Trng *)hw)->EVCTRL.reg;
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_TRNG_L22_H_INCLUDED */
#endif /* _SAML22_TRNG_COMPONENT_ */

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/**
* \file
*
* \brief SAM WDT
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_WDT_COMPONENT_
#ifndef _HRI_WDT_L22_H_INCLUDED_
#define _HRI_WDT_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_WDT_CRITICAL_SECTIONS)
#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define WDT_CRITICAL_SECTION_ENTER()
#define WDT_CRITICAL_SECTION_LEAVE()
#endif
typedef uint32_t hri_wdt_syncbusy_reg_t;
typedef uint8_t hri_wdt_clear_reg_t;
typedef uint8_t hri_wdt_config_reg_t;
typedef uint8_t hri_wdt_ctrla_reg_t;
typedef uint8_t hri_wdt_ewctrl_reg_t;
typedef uint8_t hri_wdt_intenset_reg_t;
typedef uint8_t hri_wdt_intflag_reg_t;
static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg)
{
while (((Wdt *)hw)->SYNCBUSY.reg & reg) {
};
}
static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg)
{
return ((Wdt *)hw)->SYNCBUSY.reg & reg;
}
static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw)
{
return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
}
static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw)
{
((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
}
static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw)
{
return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
}
static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw)
{
((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
}
static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
{
uint8_t tmp;
tmp = ((Wdt *)hw)->INTFLAG.reg;
tmp &= mask;
return tmp;
}
static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw)
{
return ((Wdt *)hw)->INTFLAG.reg;
}
static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
{
((Wdt *)hw)->INTFLAG.reg = mask;
}
static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw)
{
((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
}
static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw)
{
return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos;
}
static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value)
{
if (value == 0x0) {
((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
} else {
((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
}
}
static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw)
{
((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
}
static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
{
((Wdt *)hw)->INTENSET.reg = mask;
}
static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
{
uint8_t tmp;
tmp = ((Wdt *)hw)->INTENSET.reg;
tmp &= mask;
return tmp;
}
static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw)
{
return ((Wdt *)hw)->INTENSET.reg;
}
static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data)
{
((Wdt *)hw)->INTENSET.reg = data;
((Wdt *)hw)->INTENCLR.reg = ~data;
}
static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
{
((Wdt *)hw)->INTENCLR.reg = mask;
}
static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw)
{
return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos;
}
static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw)
{
return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos;
}
static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw)
{
return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos;
}
static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw)
{
return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos;
}
static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask)
{
uint32_t tmp;
tmp = ((Wdt *)hw)->SYNCBUSY.reg;
tmp &= mask;
return tmp;
}
static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw)
{
return ((Wdt *)hw)->SYNCBUSY.reg;
}
static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw)
{
uint8_t tmp;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
tmp = ((Wdt *)hw)->CTRLA.reg;
tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos;
return (bool)tmp;
}
static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
{
uint8_t tmp;
WDT_CRITICAL_SECTION_ENTER();
tmp = ((Wdt *)hw)->CTRLA.reg;
tmp &= ~WDT_CTRLA_ENABLE;
tmp |= value << WDT_CTRLA_ENABLE_Pos;
((Wdt *)hw)->CTRLA.reg = tmp;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw)
{
uint8_t tmp;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
tmp = ((Wdt *)hw)->CTRLA.reg;
tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos;
return (bool)tmp;
}
static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value)
{
uint8_t tmp;
WDT_CRITICAL_SECTION_ENTER();
tmp = ((Wdt *)hw)->CTRLA.reg;
tmp &= ~WDT_CTRLA_WEN;
tmp |= value << WDT_CTRLA_WEN_Pos;
((Wdt *)hw)->CTRLA.reg = tmp;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw)
{
uint8_t tmp;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
tmp = ((Wdt *)hw)->CTRLA.reg;
tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos;
return (bool)tmp;
}
static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value)
{
uint8_t tmp;
WDT_CRITICAL_SECTION_ENTER();
tmp = ((Wdt *)hw)->CTRLA.reg;
tmp &= ~WDT_CTRLA_ALWAYSON;
tmp |= value << WDT_CTRLA_ALWAYSON_Pos;
((Wdt *)hw)->CTRLA.reg = tmp;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg |= mask;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
{
uint8_t tmp;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
tmp = ((Wdt *)hw)->CTRLA.reg;
tmp &= mask;
return tmp;
}
static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg = data;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg &= ~mask;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CTRLA.reg ^= mask;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw)
{
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
return ((Wdt *)hw)->CTRLA.reg;
}
static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
{
uint8_t tmp;
tmp = ((Wdt *)hw)->CONFIG.reg;
tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos;
return tmp;
}
static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data)
{
uint8_t tmp;
WDT_CRITICAL_SECTION_ENTER();
tmp = ((Wdt *)hw)->CONFIG.reg;
tmp &= ~WDT_CONFIG_PER_Msk;
tmp |= WDT_CONFIG_PER(data);
((Wdt *)hw)->CONFIG.reg = tmp;
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw)
{
uint8_t tmp;
tmp = ((Wdt *)hw)->CONFIG.reg;
tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos;
return tmp;
}
static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
{
uint8_t tmp;
tmp = ((Wdt *)hw)->CONFIG.reg;
tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos;
return tmp;
}
static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data)
{
uint8_t tmp;
WDT_CRITICAL_SECTION_ENTER();
tmp = ((Wdt *)hw)->CONFIG.reg;
tmp &= ~WDT_CONFIG_WINDOW_Msk;
tmp |= WDT_CONFIG_WINDOW(data);
((Wdt *)hw)->CONFIG.reg = tmp;
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw)
{
uint8_t tmp;
tmp = ((Wdt *)hw)->CONFIG.reg;
tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos;
return tmp;
}
static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CONFIG.reg |= mask;
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
{
uint8_t tmp;
tmp = ((Wdt *)hw)->CONFIG.reg;
tmp &= mask;
return tmp;
}
static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CONFIG.reg = data;
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CONFIG.reg &= ~mask;
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CONFIG.reg ^= mask;
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw)
{
return ((Wdt *)hw)->CONFIG.reg;
}
static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
{
uint8_t tmp;
tmp = ((Wdt *)hw)->EWCTRL.reg;
tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos;
return tmp;
}
static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data)
{
uint8_t tmp;
WDT_CRITICAL_SECTION_ENTER();
tmp = ((Wdt *)hw)->EWCTRL.reg;
tmp &= ~WDT_EWCTRL_EWOFFSET_Msk;
tmp |= WDT_EWCTRL_EWOFFSET(data);
((Wdt *)hw)->EWCTRL.reg = tmp;
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask);
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw)
{
uint8_t tmp;
tmp = ((Wdt *)hw)->EWCTRL.reg;
tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos;
return tmp;
}
static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->EWCTRL.reg |= mask;
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
{
uint8_t tmp;
tmp = ((Wdt *)hw)->EWCTRL.reg;
tmp &= mask;
return tmp;
}
static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->EWCTRL.reg = data;
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->EWCTRL.reg &= ~mask;
WDT_CRITICAL_SECTION_LEAVE();
}
static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->EWCTRL.reg ^= mask;
WDT_CRITICAL_SECTION_LEAVE();
}
static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw)
{
return ((Wdt *)hw)->EWCTRL.reg;
}
static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data)
{
WDT_CRITICAL_SECTION_ENTER();
((Wdt *)hw)->CLEAR.reg = data;
hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR);
WDT_CRITICAL_SECTION_LEAVE();
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_WDT_L22_H_INCLUDED */
#endif /* _SAML22_WDT_COMPONENT_ */