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Sensor Watch Simulator (#35)

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* Put something on screen

* Use the 32bit watch_date_time repr to pass from JS

* Implement periodic callbacks

* Clear display on enabling

* Hook up watch_set_led_color() to SVG (green-only)

* Make debug output full-width

* Remove default Emscripten canvas

* Implement sleep and button clicks

* Fix time zone conversion bug in beats-time app

* Clean up warnings

* Fix pin levels

* Set time zone to browser value (if available)

* Add basic backup data saving

* Silence format specifier warnings in both targets

* Remove unnecessary, copied files

* Use RTC pointer to clear callbacks (if available)

* Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES

* Change each face to const preprocessor definition

* Remove Intl.DateTimeFormat usage

* Update shell.html title, header

* Add touch start/end event handlers on SVG buttons

* Update shell.html

* Update folder structure (shared, simulator, hardware under watch-library)

* Tease out shared components from watch_slcd

* Clean up simulator watch_slcd.c inline JS calls

* Fix missing newlines at end of file

* Add simulator warnings (except format, unused-paremter)

* Implement remaining watch_rtc functions

* Fix button bug on mouse down then drag out

* Implement remaining watch_slcd functions

* Link keyboard events to buttons (for keys A, L, M)

* Rewrite event handling (mouse, touch, keyboard) in C

* Set explicit text UTF-8 charset in shell.html

* Address PR comments

* Remove unused directories from include paths
This commit is contained in:
Alexsander Akers
2022-01-25 15:03:22 -05:00
committed by GitHub
parent 9e24f6c336
commit b8de35658f
327 changed files with 2303 additions and 570 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
watch-library/shared/config/RTE_Components.h Normal file
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/**
* \file
*
* \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
*
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
*
* \acme_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \acme_license_stop
*
* Project: My Project
* Target: ATSAML22J18A
*
**/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#define ATMEL_START
#endif /* RTE_COMPONENTS_H */

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watch-library/shared/config/hpl_dmac_config.h Normal file
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watch-library/shared/config/hpl_eic_config.h Normal file
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/* Auto-generated config file hpl_eic_config.h */
#ifndef HPL_EIC_CONFIG_H
#define HPL_EIC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Settings
// <o> Clock Selection
// <i> Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or
// <i> either by CLK_ULP32K when power consumption is the priority.
// <0x0=> Clocked by GCLK
// <0x1=> Clocked by ULPOSC32K
// <id> eic_arch_cksel
#ifndef CONF_EIC_CKSEL
#define CONF_EIC_CKSEL 0
#endif
// </h>
// <e> Non-Maskable Interrupt Control
// <id> eic_arch_nmi_ctrl
#ifndef CONF_EIC_ENABLE_NMI_CTRL
#define CONF_EIC_ENABLE_NMI_CTRL 0
#endif
// <q> Non-Maskable Interrupt Filter Enable
// <i> Indicates whether the mon-maskable interrupt filter is enabled or not
// <id> eic_arch_nmifilten
#ifndef CONF_EIC_NMIFILTEN
#define CONF_EIC_NMIFILTEN 0
#endif
// <y> Non-Maskable Interrupt Sense
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines non-maskable interrupt sense
// <id> eic_arch_nmisense
#ifndef CONF_EIC_NMISENSE
#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> Asynchronous Edge Detection Mode
// <i> Indicates the interrupt detection mode operated synchronously or asynchronousl
// <id> eic_arch_nmiasynch
#ifndef CONF_EIC_NMIASYNCH
#define CONF_EIC_NMIASYNCH 0
#endif
// </e>
// <e> Interrupt 0 Settings
// <id> eic_arch_enable_irq_setting0
#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
#define CONF_EIC_ENABLE_IRQ_SETTING0 0
#endif
// <q> External Interrupt 0 Filter Enable
// <i> Indicates whether the external interrupt 0 filter is enabled or not
// <id> eic_arch_filten0
#ifndef CONF_EIC_FILTEN0
#define CONF_EIC_FILTEN0 1
#endif
// <q> External Interrupt 0 Event Output Enable
// <i> Indicates whether the external interrupt 0 event output is enabled or not
// <id> eic_arch_extinteo0
#ifndef CONF_EIC_EXTINTEO0
#define CONF_EIC_EXTINTEO0 0
#endif
// <y> Input 0 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense0
#ifndef CONF_EIC_SENSE0
#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 0 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch0
#ifndef CONF_EIC_ASYNCH0
#define CONF_EIC_ASYNCH0 0
#endif
// </e>
// <e> Interrupt 1 Settings
// <id> eic_arch_enable_irq_setting1
#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
#define CONF_EIC_ENABLE_IRQ_SETTING1 0
#endif
// <q> External Interrupt 1 Filter Enable
// <i> Indicates whether the external interrupt 1 filter is enabled or not
// <id> eic_arch_filten1
#ifndef CONF_EIC_FILTEN1
#define CONF_EIC_FILTEN1 1
#endif
// <q> External Interrupt 1 Event Output Enable
// <i> Indicates whether the external interrupt 1 event output is enabled or not
// <id> eic_arch_extinteo1
#ifndef CONF_EIC_EXTINTEO1
#define CONF_EIC_EXTINTEO1 0
#endif
// <y> Input 1 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense1
#ifndef CONF_EIC_SENSE1
#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 1 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch1
#ifndef CONF_EIC_ASYNCH1
#define CONF_EIC_ASYNCH1 0
#endif
// </e>
// <e> Interrupt 2 Settings
// <id> eic_arch_enable_irq_setting2
#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
#define CONF_EIC_ENABLE_IRQ_SETTING2 0
#endif
// <q> External Interrupt 2 Filter Enable
// <i> Indicates whether the external interrupt 2 filter is enabled or not
// <id> eic_arch_filten2
#ifndef CONF_EIC_FILTEN2
#define CONF_EIC_FILTEN2 1
#endif
// <q> External Interrupt 2 Event Output Enable
// <i> Indicates whether the external interrupt 2 event output is enabled or not
// <id> eic_arch_extinteo2
#ifndef CONF_EIC_EXTINTEO2
#define CONF_EIC_EXTINTEO2 0
#endif
// <y> Input 2 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense2
#ifndef CONF_EIC_SENSE2
#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 2 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch2
#ifndef CONF_EIC_ASYNCH2
#define CONF_EIC_ASYNCH2 0
#endif
// </e>
// <e> Interrupt 3 Settings
// <id> eic_arch_enable_irq_setting3
#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
#define CONF_EIC_ENABLE_IRQ_SETTING3 0
#endif
// <q> External Interrupt 3 Filter Enable
// <i> Indicates whether the external interrupt 3 filter is enabled or not
// <id> eic_arch_filten3
#ifndef CONF_EIC_FILTEN3
#define CONF_EIC_FILTEN3 1
#endif
// <q> External Interrupt 3 Event Output Enable
// <i> Indicates whether the external interrupt 3 event output is enabled or not
// <id> eic_arch_extinteo3
#ifndef CONF_EIC_EXTINTEO3
#define CONF_EIC_EXTINTEO3 0
#endif
// <y> Input 3 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense3
#ifndef CONF_EIC_SENSE3
#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 3 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch3
#ifndef CONF_EIC_ASYNCH3
#define CONF_EIC_ASYNCH3 0
#endif
// </e>
// <e> Interrupt 4 Settings
// <id> eic_arch_enable_irq_setting4
#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
#define CONF_EIC_ENABLE_IRQ_SETTING4 0
#endif
// <q> External Interrupt 4 Filter Enable
// <i> Indicates whether the external interrupt 4 filter is enabled or not
// <id> eic_arch_filten4
#ifndef CONF_EIC_FILTEN4
#define CONF_EIC_FILTEN4 1
#endif
// <q> External Interrupt 4 Event Output Enable
// <i> Indicates whether the external interrupt 4 event output is enabled or not
// <id> eic_arch_extinteo4
#ifndef CONF_EIC_EXTINTEO4
#define CONF_EIC_EXTINTEO4 0
#endif
// <y> Input 4 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense4
#ifndef CONF_EIC_SENSE4
#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 4 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch4
#ifndef CONF_EIC_ASYNCH4
#define CONF_EIC_ASYNCH4 0
#endif
// </e>
// <e> Interrupt 5 Settings
// <id> eic_arch_enable_irq_setting5
#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
#define CONF_EIC_ENABLE_IRQ_SETTING5 0
#endif
// <q> External Interrupt 5 Filter Enable
// <i> Indicates whether the external interrupt 5 filter is enabled or not
// <id> eic_arch_filten5
#ifndef CONF_EIC_FILTEN5
#define CONF_EIC_FILTEN5 1
#endif
// <q> External Interrupt 5 Event Output Enable
// <i> Indicates whether the external interrupt 5 event output is enabled or not
// <id> eic_arch_extinteo5
#ifndef CONF_EIC_EXTINTEO5
#define CONF_EIC_EXTINTEO5 0
#endif
// <y> Input 5 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense5
#ifndef CONF_EIC_SENSE5
#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 5 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch5
#ifndef CONF_EIC_ASYNCH5
#define CONF_EIC_ASYNCH5 0
#endif
// </e>
// <e> Interrupt 6 Settings
// <id> eic_arch_enable_irq_setting6
#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
#define CONF_EIC_ENABLE_IRQ_SETTING6 0
#endif
// <q> External Interrupt 6 Filter Enable
// <i> Indicates whether the external interrupt 6 filter is enabled or not
// <id> eic_arch_filten6
#ifndef CONF_EIC_FILTEN6
#define CONF_EIC_FILTEN6 1
#endif
// <q> External Interrupt 6 Event Output Enable
// <i> Indicates whether the external interrupt 6 event output is enabled or not
// <id> eic_arch_extinteo6
#ifndef CONF_EIC_EXTINTEO6
#define CONF_EIC_EXTINTEO6 0
#endif
// <y> Input 6 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense6
#ifndef CONF_EIC_SENSE6
#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 6 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch6
#ifndef CONF_EIC_ASYNCH6
#define CONF_EIC_ASYNCH6 0
#endif
// </e>
// <e> Interrupt 7 Settings
// <id> eic_arch_enable_irq_setting7
#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
#define CONF_EIC_ENABLE_IRQ_SETTING7 0
#endif
// <q> External Interrupt 7 Filter Enable
// <i> Indicates whether the external interrupt 7 filter is enabled or not
// <id> eic_arch_filten7
#ifndef CONF_EIC_FILTEN7
#define CONF_EIC_FILTEN7 1
#endif
// <q> External Interrupt 7 Event Output Enable
// <i> Indicates whether the external interrupt 7 event output is enabled or not
// <id> eic_arch_extinteo7
#ifndef CONF_EIC_EXTINTEO7
#define CONF_EIC_EXTINTEO7 0
#endif
// <y> Input 7 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense7
#ifndef CONF_EIC_SENSE7
#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 7 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch7
#ifndef CONF_EIC_ASYNCH7
#define CONF_EIC_ASYNCH7 0
#endif
// </e>
// <e> Interrupt 8 Settings
// <id> eic_arch_enable_irq_setting8
#ifndef CONF_EIC_ENABLE_IRQ_SETTING8
#define CONF_EIC_ENABLE_IRQ_SETTING8 0
#endif
// <q> External Interrupt 8 Filter Enable
// <i> Indicates whether the external interrupt 8 filter is enabled or not
// <id> eic_arch_filten8
#ifndef CONF_EIC_FILTEN8
#define CONF_EIC_FILTEN8 0
#endif
// <q> External Interrupt 8 Event Output Enable
// <i> Indicates whether the external interrupt 8 event output is enabled or not
// <id> eic_arch_extinteo8
#ifndef CONF_EIC_EXTINTEO8
#define CONF_EIC_EXTINTEO8 0
#endif
// <y> Input 8 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense8
#ifndef CONF_EIC_SENSE8
#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 8 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch8
#ifndef CONF_EIC_ASYNCH8
#define CONF_EIC_ASYNCH8 0
#endif
// </e>
// <e> Interrupt 9 Settings
// <id> eic_arch_enable_irq_setting9
#ifndef CONF_EIC_ENABLE_IRQ_SETTING9
#define CONF_EIC_ENABLE_IRQ_SETTING9 0
#endif
// <q> External Interrupt 9 Filter Enable
// <i> Indicates whether the external interrupt 9 filter is enabled or not
// <id> eic_arch_filten9
#ifndef CONF_EIC_FILTEN9
#define CONF_EIC_FILTEN9 0
#endif
// <q> External Interrupt 9 Event Output Enable
// <i> Indicates whether the external interrupt 9 event output is enabled or not
// <id> eic_arch_extinteo9
#ifndef CONF_EIC_EXTINTEO9
#define CONF_EIC_EXTINTEO9 0
#endif
// <y> Input 9 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense9
#ifndef CONF_EIC_SENSE9
#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 9 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch9
#ifndef CONF_EIC_ASYNCH9
#define CONF_EIC_ASYNCH9 0
#endif
// </e>
// <e> Interrupt 10 Settings
// <id> eic_arch_enable_irq_setting10
#ifndef CONF_EIC_ENABLE_IRQ_SETTING10
#define CONF_EIC_ENABLE_IRQ_SETTING10 0
#endif
// <q> External Interrupt 10 Filter Enable
// <i> Indicates whether the external interrupt 10 filter is enabled or not
// <id> eic_arch_filten10
#ifndef CONF_EIC_FILTEN10
#define CONF_EIC_FILTEN10 0
#endif
// <q> External Interrupt 10 Event Output Enable
// <i> Indicates whether the external interrupt 10 event output is enabled or not
// <id> eic_arch_extinteo10
#ifndef CONF_EIC_EXTINTEO10
#define CONF_EIC_EXTINTEO10 0
#endif
// <y> Input 10 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense10
#ifndef CONF_EIC_SENSE10
#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 10 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch10
#ifndef CONF_EIC_ASYNCH10
#define CONF_EIC_ASYNCH10 0
#endif
// </e>
// <e> Interrupt 11 Settings
// <id> eic_arch_enable_irq_setting11
#ifndef CONF_EIC_ENABLE_IRQ_SETTING11
#define CONF_EIC_ENABLE_IRQ_SETTING11 0
#endif
// <q> External Interrupt 11 Filter Enable
// <i> Indicates whether the external interrupt 11 filter is enabled or not
// <id> eic_arch_filten11
#ifndef CONF_EIC_FILTEN11
#define CONF_EIC_FILTEN11 0
#endif
// <q> External Interrupt 11 Event Output Enable
// <i> Indicates whether the external interrupt 11 event output is enabled or not
// <id> eic_arch_extinteo11
#ifndef CONF_EIC_EXTINTEO11
#define CONF_EIC_EXTINTEO11 0
#endif
// <y> Input 11 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense11
#ifndef CONF_EIC_SENSE11
#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 11 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch11
#ifndef CONF_EIC_ASYNCH11
#define CONF_EIC_ASYNCH11 0
#endif
// </e>
// <e> Interrupt 12 Settings
// <id> eic_arch_enable_irq_setting12
#ifndef CONF_EIC_ENABLE_IRQ_SETTING12
#define CONF_EIC_ENABLE_IRQ_SETTING12 0
#endif
// <q> External Interrupt 12 Filter Enable
// <i> Indicates whether the external interrupt 12 filter is enabled or not
// <id> eic_arch_filten12
#ifndef CONF_EIC_FILTEN12
#define CONF_EIC_FILTEN12 0
#endif
// <q> External Interrupt 12 Event Output Enable
// <i> Indicates whether the external interrupt 12 event output is enabled or not
// <id> eic_arch_extinteo12
#ifndef CONF_EIC_EXTINTEO12
#define CONF_EIC_EXTINTEO12 0
#endif
// <y> Input 12 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense12
#ifndef CONF_EIC_SENSE12
#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 12 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch12
#ifndef CONF_EIC_ASYNCH12
#define CONF_EIC_ASYNCH12 0
#endif
// </e>
// <e> Interrupt 13 Settings
// <id> eic_arch_enable_irq_setting13
#ifndef CONF_EIC_ENABLE_IRQ_SETTING13
#define CONF_EIC_ENABLE_IRQ_SETTING13 0
#endif
// <q> External Interrupt 13 Filter Enable
// <i> Indicates whether the external interrupt 13 filter is enabled or not
// <id> eic_arch_filten13
#ifndef CONF_EIC_FILTEN13
#define CONF_EIC_FILTEN13 0
#endif
// <q> External Interrupt 13 Event Output Enable
// <i> Indicates whether the external interrupt 13 event output is enabled or not
// <id> eic_arch_extinteo13
#ifndef CONF_EIC_EXTINTEO13
#define CONF_EIC_EXTINTEO13 0
#endif
// <y> Input 13 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense13
#ifndef CONF_EIC_SENSE13
#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 13 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch13
#ifndef CONF_EIC_ASYNCH13
#define CONF_EIC_ASYNCH13 0
#endif
// </e>
// <e> Interrupt 14 Settings
// <id> eic_arch_enable_irq_setting14
#ifndef CONF_EIC_ENABLE_IRQ_SETTING14
#define CONF_EIC_ENABLE_IRQ_SETTING14 0
#endif
// <q> External Interrupt 14 Filter Enable
// <i> Indicates whether the external interrupt 14 filter is enabled or not
// <id> eic_arch_filten14
#ifndef CONF_EIC_FILTEN14
#define CONF_EIC_FILTEN14 0
#endif
// <q> External Interrupt 14 Event Output Enable
// <i> Indicates whether the external interrupt 14 event output is enabled or not
// <id> eic_arch_extinteo14
#ifndef CONF_EIC_EXTINTEO14
#define CONF_EIC_EXTINTEO14 0
#endif
// <y> Input 14 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense14
#ifndef CONF_EIC_SENSE14
#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 14 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch14
#ifndef CONF_EIC_ASYNCH14
#define CONF_EIC_ASYNCH14 0
#endif
// </e>
// <e> Interrupt 15 Settings
// <id> eic_arch_enable_irq_setting15
#ifndef CONF_EIC_ENABLE_IRQ_SETTING15
#define CONF_EIC_ENABLE_IRQ_SETTING15 0
#endif
// <q> External Interrupt 15 Filter Enable
// <i> Indicates whether the external interrupt 15 filter is enabled or not
// <id> eic_arch_filten15
#ifndef CONF_EIC_FILTEN15
#define CONF_EIC_FILTEN15 0
#endif
// <q> External Interrupt 15 Event Output Enable
// <i> Indicates whether the external interrupt 15 event output is enabled or not
// <id> eic_arch_extinteo15
#ifndef CONF_EIC_EXTINTEO15
#define CONF_EIC_EXTINTEO15 0
#endif
// <y> Input 15 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense15
#ifndef CONF_EIC_SENSE15
#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 15 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch15
#ifndef CONF_EIC_ASYNCH15
#define CONF_EIC_ASYNCH15 0
#endif
// </e>
// this is still a hack: if the user wants to use PA02 (alarm button) as an RTC interrupt pin and PB02 (9-pin A2) on the EIC, we don't support that.
// TODO item: refactor out our reliance on the ASF external interrupt driver. - joey 11/30
#ifdef CRYSTALLESS
#define CONFIG_EIC_EXTINT_MAP {0, PIN_PB00}, {1, PIN_PB01}, {2, PIN_PA02}, {3, PIN_PB03}, {5, PIN_PB05}, {7, PIN_PA07},
#else
#define CONFIG_EIC_EXTINT_MAP {0, PIN_PB00}, {1, PIN_PB01}, {2, PIN_PA02}, {3, PIN_PB03}, {6, PIN_PA22}, {7, PIN_PA23},
#endif
// <<< end of configuration section >>>
#endif // HPL_EIC_CONFIG_H

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/* Auto-generated config file hpl_gclk_config.h */
#ifndef HPL_GCLK_CONFIG_H
#define HPL_GCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> Generic clock generator 0 configuration
// <i> Indicates whether generic clock 0 configuration is enabled or not
// <id> enable_gclk_gen_0
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
#define CONF_GCLK_GENERATOR_0_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 0 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 0
// <id> gclk_gen_0_oscillator
#ifndef CONF_GCLK_GEN_0_SOURCE
#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_0_runstdby
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
#define CONF_GCLK_GEN_0_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_0_div_sel
#ifndef CONF_GCLK_GEN_0_DIVSEL
#define CONF_GCLK_GEN_0_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_0_oe
#ifndef CONF_GCLK_GEN_0_OE
#define CONF_GCLK_GEN_0_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_0_oov
#ifndef CONF_GCLK_GEN_0_OOV
#define CONF_GCLK_GEN_0_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_0_idc
#ifndef CONF_GCLK_GEN_0_IDC
#define CONF_GCLK_GEN_0_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_0_enable
#ifndef CONF_GCLK_GEN_0_GENEN
#define CONF_GCLK_GEN_0_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
// <id> gclk_gen_0_div
#ifndef CONF_GCLK_GEN_0_DIV
#define CONF_GCLK_GEN_0_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 1 configuration
// <i> Indicates whether generic clock 1 configuration is enabled or not
// <id> enable_gclk_gen_1
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
#define CONF_GCLK_GENERATOR_1_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 1 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 1
// <id> gclk_gen_1_oscillator
#ifndef CONF_GCLK_GEN_1_SOURCE
#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_1_runstdby
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
#define CONF_GCLK_GEN_1_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_1_div_sel
#ifndef CONF_GCLK_GEN_1_DIVSEL
#define CONF_GCLK_GEN_1_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_1_oe
#ifndef CONF_GCLK_GEN_1_OE
#define CONF_GCLK_GEN_1_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_1_oov
#ifndef CONF_GCLK_GEN_1_OOV
#define CONF_GCLK_GEN_1_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_1_idc
#ifndef CONF_GCLK_GEN_1_IDC
#define CONF_GCLK_GEN_1_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_1_enable
#ifndef CONF_GCLK_GEN_1_GENEN
#define CONF_GCLK_GEN_1_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
// <id> gclk_gen_1_div
#ifndef CONF_GCLK_GEN_1_DIV
#define CONF_GCLK_GEN_1_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 2 configuration
// <i> Indicates whether generic clock 2 configuration is enabled or not
// <id> enable_gclk_gen_2
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
#define CONF_GCLK_GENERATOR_2_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 2 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 2
// <id> gclk_gen_2_oscillator
#ifndef CONF_GCLK_GEN_2_SOURCE
#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_2_runstdby
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
#define CONF_GCLK_GEN_2_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_2_div_sel
#ifndef CONF_GCLK_GEN_2_DIVSEL
#define CONF_GCLK_GEN_2_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_2_oe
#ifndef CONF_GCLK_GEN_2_OE
#define CONF_GCLK_GEN_2_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_2_oov
#ifndef CONF_GCLK_GEN_2_OOV
#define CONF_GCLK_GEN_2_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_2_idc
#ifndef CONF_GCLK_GEN_2_IDC
#define CONF_GCLK_GEN_2_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_2_enable
#ifndef CONF_GCLK_GEN_2_GENEN
#define CONF_GCLK_GEN_2_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
// <id> gclk_gen_2_div
#ifndef CONF_GCLK_GEN_2_DIV
#define CONF_GCLK_GEN_2_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 3 configuration
// <i> Indicates whether generic clock 3 configuration is enabled or not
// <id> enable_gclk_gen_3
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
#define CONF_GCLK_GENERATOR_3_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 3 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 3
// <id> gclk_gen_3_oscillator
#ifndef CONF_GCLK_GEN_3_SOURCE
#ifdef CRYSTALLESS
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
#else
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
#endif
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_3_runstdby
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
#define CONF_GCLK_GEN_3_RUNSTDBY 1
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_3_div_sel
#ifndef CONF_GCLK_GEN_3_DIVSEL
#define CONF_GCLK_GEN_3_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_3_oe
#ifndef CONF_GCLK_GEN_3_OE
#define CONF_GCLK_GEN_3_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_3_oov
#ifndef CONF_GCLK_GEN_3_OOV
#define CONF_GCLK_GEN_3_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_3_idc
#ifndef CONF_GCLK_GEN_3_IDC
#define CONF_GCLK_GEN_3_IDC 1
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_3_enable
#ifndef CONF_GCLK_GEN_3_GENEN
#define CONF_GCLK_GEN_3_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
// <id> gclk_gen_3_div
#ifndef CONF_GCLK_GEN_3_DIV
#define CONF_GCLK_GEN_3_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 4 configuration
// <i> Indicates whether generic clock 4 configuration is enabled or not
// <id> enable_gclk_gen_4
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
#define CONF_GCLK_GENERATOR_4_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 4 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 4
// <id> gclk_gen_4_oscillator
#ifndef CONF_GCLK_GEN_4_SOURCE
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_4_runstdby
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
#define CONF_GCLK_GEN_4_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_4_div_sel
#ifndef CONF_GCLK_GEN_4_DIVSEL
#define CONF_GCLK_GEN_4_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_4_oe
#ifndef CONF_GCLK_GEN_4_OE
#define CONF_GCLK_GEN_4_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_4_oov
#ifndef CONF_GCLK_GEN_4_OOV
#define CONF_GCLK_GEN_4_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_4_idc
#ifndef CONF_GCLK_GEN_4_IDC
#define CONF_GCLK_GEN_4_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_4_enable
#ifndef CONF_GCLK_GEN_4_GENEN
#define CONF_GCLK_GEN_4_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
// <id> gclk_gen_4_div
#ifndef CONF_GCLK_GEN_4_DIV
#define CONF_GCLK_GEN_4_DIV 1
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_GCLK_CONFIG_H

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/* Auto-generated config file hpl_mclk_config.h */
#ifndef HPL_MCLK_CONFIG_H
#define HPL_MCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <e> System Configuration
// <i> Indicates whether configuration for system is enabled or not
// <id> enable_cpu_clock
#ifndef CONF_SYSTEM_CONFIG
#define CONF_SYSTEM_CONFIG 1
#endif
// <h> Basic settings
// <y> CPU Clock source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <i> This defines the clock source for the CPU
// <id> cpu_clock_source
#ifndef CONF_CPU_SRC
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> CPU Clock Division Factor
// <MCLK_CPUDIV_CPUDIV_DIV1_Val"> 1
// <MCLK_CPUDIV_CPUDIV_DIV2_Val"> 2
// <MCLK_CPUDIV_CPUDIV_DIV4_Val"> 4
// <MCLK_CPUDIV_CPUDIV_DIV8_Val"> 8
// <MCLK_CPUDIV_CPUDIV_DIV16_Val"> 16
// <MCLK_CPUDIV_CPUDIV_DIV32_Val"> 32
// <MCLK_CPUDIV_CPUDIV_DIV64_Val"> 64
// <MCLK_CPUDIV_CPUDIV_DIV128_Val"> 128
// <i> Prescalar for CPU clock
// <id> cpu_div
#ifndef CONF_MCLK_CPUDIV
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val
#endif
// <y> Backup Clock Division
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_bupdiv
#ifndef CONF_MCLK_BUPDIV
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV1_Val
#endif
// </h>
// <h> NVM Settings
// <o> NVM Wait States
// <i> These bits select the number of wait states for a read operation.
// <0=> 0
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <7=> 7
// <8=> 8
// <9=> 9
// <10=> 10
// <11=> 11
// <12=> 12
// <13=> 13
// <14=> 14
// <15=> 15
// <id> nvm_wait_states
#ifndef CONF_NVM_WAIT_STATE
#define CONF_NVM_WAIT_STATE 0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_MCLK_CONFIG_H

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/* Auto-generated config file hpl_nvmctrl_config.h */
#ifndef HPL_NVMCTRL_CONFIG_H
#define HPL_NVMCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Settings
// <o> Read Mode Selection
// <0x00=> No Miss Penalty
// <0x01=> Low Power
// <0x02=> Deterministic
// <id> nvm_arch_read_mode
#ifndef CONF_NVM_READ_MODE
#define CONF_NVM_READ_MODE 1
#endif
// <o> Power Reduction Mode During Sleep
// <0x00=> Wake On Access
// <0x01=> Wake Up Instant
// <0x03=> Disabled
// <id> nvm_arch_sleepprm
#ifndef CONF_NVM_SLEEPPRM
#define CONF_NVM_SLEEPPRM 0
#endif
// <q> Cache Disable
// <i> Indicate whether cache is disable or not
// <id> nvm_arch_cache
#ifndef CONF_NVM_CACHE
#define CONF_NVM_CACHE 0
#endif
// </h>
// <<< end of configuration section >>>
#endif // HPL_NVMCTRL_CONFIG_H

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/* Auto-generated config file hpl_osc32kctrl_config.h */
#ifndef HPL_OSC32KCTRL_CONFIG_H
#define HPL_OSC32KCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> RTC Source configuration
// <id> enable_rtc_source
#ifndef CONF_RTCCTRL_CONFIG
#define CONF_RTCCTRL_CONFIG 0
#endif
// <h> RTC source control
// <y> RTC Clock Source Selection
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <i> This defines the clock source for RTC
// <id> rtc_source_oscillator
#ifndef CONF_RTCCTRL_SRC
#ifdef CRYSTALLESS
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
#else
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
#endif
#endif
// <q> Use 1 kHz output
// <id> rtc_1khz_selection
#ifndef CONF_RTCCTRL_1KHZ
#define CONF_RTCCTRL_1KHZ 1
#endif
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
#else
#error unexpected CONF_RTCCTRL_SRC
#endif
// </h>
// </e>
// <e> SLCD Source configuration
// <id> enable_slcd_source
#ifndef CONF_SLCDCTRL_CONFIG
#define CONF_SLCDCTRL_CONFIG 0
#endif
// <h> SLCD source control
// <y> SLCD Clock Source Selection
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <i> This defines the clock source for SLCD
// <id> slcd_source_oscillator
#ifndef CONF_SLCDCTRL_SRC
#define CONF_SLCDCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
#endif
// </h>
// </e>
// <e> 32kHz External Crystal Oscillator Configuration
// <i> Indicates whether configuration for External 32K Osc is enabled or not
// <id> enable_xosc32k
#ifndef CONF_XOSC32K_CONFIG
#define CONF_XOSC32K_CONFIG 1
#endif
// <h> 32kHz External Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
// <id> xosc32k_arch_enable
#ifndef CONF_XOSC32K_ENABLE
#define CONF_XOSC32K_ENABLE 1
#endif
// <o> Start-Up Time
// <0x0=>62592us
// <0x1=>125092us
// <0x2=>500092us
// <0x3=>1000092us
// <0x4=>2000092us
// <0x5=>4000092us
// <0x6=>8000092us
// <id> xosc32k_arch_startup
#ifndef CONF_XOSC32K_STARTUP
#define CONF_XOSC32K_STARTUP 0x3
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc32k_arch_ondemand
#ifndef CONF_XOSC32K_ONDEMAND
#define CONF_XOSC32K_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc32k_arch_runstdby
#ifndef CONF_XOSC32K_RUNSTDBY
#define CONF_XOSC32K_RUNSTDBY 1
#endif
// <q> 1kHz Output Enable
// <i> Indicates whether 1kHz Output is enabled or not
// <id> xosc32k_arch_en1k
#ifndef CONF_XOSC32K_EN1K
#define CONF_XOSC32K_EN1K 1
#endif
// <q> 32kHz Output Enable
// <i> Indicates whether 32kHz Output is enabled or not
// <id> xosc32k_arch_en32k
#ifndef CONF_XOSC32K_EN32K
#define CONF_XOSC32K_EN32K 1
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc32k_arch_swben
#ifndef CONF_XOSC32K_SWBEN
#define CONF_XOSC32K_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc32k_arch_cfden
#ifndef CONF_XOSC32K_CFDEN
#define CONF_XOSC32K_CFDEN 0
#endif
// <q> Clock Failure Detector Event Out
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
// <id> xosc32k_arch_cfdeo
#ifndef CONF_XOSC32K_CFDEO
#define CONF_XOSC32K_CFDEO 0
#endif
// <q> Crystal connected to XIN32/XOUT32 Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc32k_arch_xtalen
#ifndef CONF_XOSC32K_XTALEN
#define CONF_XOSC32K_XTALEN 1
#endif
// </h>
// </e>
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
// <i> Indicates whether configuration for OSCULP32K is enabled or not
// <id> enable_osculp32k
#ifndef CONF_OSCULP32K_CONFIG
#define CONF_OSCULP32K_CONFIG 1
#endif
// <h> 32kHz Ultra Low Power Internal Oscillator Control
// <q> Oscillator Calibration Control
// <i> Indicates whether Oscillator Calibration is enabled or not
// <id> osculp32k_calib_enable
#ifndef CONF_OSCULP32K_CALIB_ENABLE
#define CONF_OSCULP32K_CALIB_ENABLE 0
#endif
// <o> Oscillator Calibration <0x0-0x1F>
// <id> osculp32k_calib
#ifndef CONF_OSCULP32K_CALIB
#define CONF_OSCULP32K_CALIB 0x0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_OSC32KCTRL_CONFIG_H

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/* Auto-generated config file hpl_oscctrl_config.h */
#ifndef HPL_OSCCTRL_CONFIG_H
#define HPL_OSCCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> External Multipurpose Crystal Oscillator Configuration
// <i> Indicates whether configuration for XOSC is enabled or not
// <id> enable_xosc
#ifndef CONF_XOSC_CONFIG
#define CONF_XOSC_CONFIG 0
#endif
// <o> Frequency <400000-32000000>
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
// <id> xosc_frequency
#ifndef CONF_XOSC_FREQUENCY
#define CONF_XOSC_FREQUENCY 400000
#endif
// <h> External Multipurpose Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
// <id> xosc_arch_enable
#ifndef CONF_XOSC_ENABLE
#define CONF_XOSC_ENABLE 0
#endif
// <o> Start-Up Time
// <0x0=>31us
// <0x1=>61us
// <0x2=>122us
// <0x3=>244us
// <0x4=>488us
// <0x5=>977us
// <0x6=>1953us
// <0x7=>3906us
// <0x8=>7813us
// <0x9=>15625us
// <0xA=>31250us
// <0xB=>62500us
// <0xC=>125000us
// <0xD=>250000us
// <0xE=>500000us
// <0xF=>1000000us
// <id> xosc_arch_startup
#ifndef CONF_XOSC_STARTUP
#define CONF_XOSC_STARTUP 0x0
#endif
// <q> Automatic Amplitude Gain Control
// <i> Indicates whether Automatic Amplitude Gain Control is enabled or not
// <id> xosc_arch_ampgc
#ifndef CONF_XOSC_AMPGC
#define CONF_XOSC_AMPGC 0
#endif
// <o> External Multipurpose Crystal Oscillator Gain
// <0x0=>2MHz
// <0x1=>4MHz
// <0x2=>8MHz
// <0x3=>16MHz
// <0x4=>30MHz
// <id> xosc_arch_gain
#ifndef CONF_XOSC_GAIN
#define CONF_XOSC_GAIN 0x0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc_arch_ondemand
#ifndef CONF_XOSC_ONDEMAND
#define CONF_XOSC_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc_arch_runstdby
#ifndef CONF_XOSC_RUNSTDBY
#define CONF_XOSC_RUNSTDBY 0
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc_arch_swben
#ifndef CONF_XOSC_SWBEN
#define CONF_XOSC_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc_arch_cfden
#ifndef CONF_XOSC_CFDEN
#define CONF_XOSC_CFDEN 0
#endif
// <q> Clock Failure Detector Event Out
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
// <id> xosc_arch_cfdeo
#ifndef CONF_XOSC_CFDEO
#define CONF_XOSC_CFDEO 0
#endif
// <q> Crystal connected to XIN/XOUT Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc_arch_xtalen
#ifndef CONF_XOSC_XTALEN
#define CONF_XOSC_XTALEN 0
#endif
//</h>
//</e>
// <e> 16MHz Internal Oscillator Configuration
// <i> Indicates whether configuration for OSC8M is enabled or not
// <id> enable_osc16m
#ifndef CONF_OSC16M_CONFIG
#define CONF_OSC16M_CONFIG 1
#endif
// <h> 16MHz Internal Oscillator Control
// <q> Enable
// <i> Indicates whether 16MHz Internal Oscillator is enabled or not
// <id> osc16m_arch_enable
#ifndef CONF_OSC16M_ENABLE
#define CONF_OSC16M_ENABLE 1
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> osc16m_arch_ondemand
#ifndef CONF_OSC16M_ONDEMAND
#define CONF_OSC16M_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> osc16m_arch_runstdby
#ifndef CONF_OSC16M_RUNSTDBY
#define CONF_OSC16M_RUNSTDBY 0
#endif
// <y> Oscillator Frequency Selection(Mhz)
// <OSCCTRL_OSC16MCTRL_FSEL_4_Val"> 4
// <OSCCTRL_OSC16MCTRL_FSEL_8_Val"> 8
// <OSCCTRL_OSC16MCTRL_FSEL_12_Val"> 12
// <OSCCTRL_OSC16MCTRL_FSEL_16_Val"> 16
// <i> This defines the oscillator frequency (Mhz)
// <id> osc16m_freq
#ifndef CONF_OSC16M_FSEL
#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val
#endif
// <q> Oscillator Calibration Control
// <i> Indicates whether Oscillator Calibration is enabled or not
// <id> osc16m_arch_calib_enable
#ifndef CONF_OSC16M_CALIB_ENABLE
#define CONF_OSC16M_CALIB_ENABLE 0
#endif
// <o> 4MHz Frequency Calibration <0x0-0x3F>
// <id> osc16m_arch_4m_fcal
#ifndef CONF_OSC16M_FCAL
#define CONF_OSC16M_4M_FCAL 0
#endif
// <o> 4MHz Temperature Calibration <0x0-0x3F>
// <id> osc16m_arch_4m_tcal
#ifndef CONF_OSC16M_TCAL
#define CONF_OSC16M_4M_TCAL 0
#endif
// <o> 8MHz Frequency Calibration <0x0-0x3F>
// <id> osc16m_arch_8m_fcal
#ifndef CONF_OSC16M_FCAL
#define CONF_OSC16M_8M_FCAL 0
#endif
// <o> 8MHz Temperature Calibration <0x0-0x3F>
// <id> osc16m_arch_8m_tcal
#ifndef CONF_OSC16M_TCAL
#define CONF_OSC16M_8M_TCAL 0
#endif
// <o> 12MHz Frequency Calibration <0x0-0x3F>
// <id> osc16m_arch_12m_fcal
#ifndef CONF_OSC16M_FCAL
#define CONF_OSC16M_12M_FCAL 0
#endif
// <o> 12MHz Temperature Calibration <0x0-0x3F>
// <id> osc16m_arch_12m_tcal
#ifndef CONF_OSC16M_TCAL
#define CONF_OSC16M_12M_TCAL 0
#endif
// <o> 16MHz Frequency Calibration <0x0-0x3F>
// <id> osc16m_arch_fcal
#ifndef CONF_OSC16M_FCAL
#define CONF_OSC16M_16M_FCAL 0
#endif
// <o> 16MHz Temperature Calibration <0x0-0x3F>
// <id> osc16m_arch_16m_tcal
#ifndef CONF_OSC16M_TCAL
#define CONF_OSC16M_16M_TCAL 0
#endif
//</h>
//</e>
// <e> DFLL Configuration
// <i> Indicates whether configuration for DFLL is enabled or not
// <id> enable_dfll48m
#ifndef CONF_DFLL_CONFIG
#define CONF_DFLL_CONFIG 0
#endif
// <y> Reference Clock Source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source.
// <id> dfll48m_ref_clock
#ifndef CONF_DFLL_GCLK
#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
// <h> Digital Frequency Locked Loop Control
// <q> DFLL Enable
// <i> Indicates whether DFLL is enabled or not
// <id> dfll48m_arch_enable
#ifndef CONF_DFLL_ENABLE
#define CONF_DFLL_ENABLE 0
#endif
// <q> Wait Lock
// <i> Indicates whether Wait Lock is enabled or not
// <id> dfll_arch_waitlock
#ifndef CONF_DFLL_WAITLOCK
#define CONF_DFLL_WAITLOCK 0
#endif
// <q> Bypass Coarse Lock
// <i> Indicates whether Bypass Coarse Lock is enabled or not
// <id> dfll_arch_bplckc
#ifndef CONF_DFLL_BPLCKC
#define CONF_DFLL_BPLCKC 0
#endif
// <q> Quick Lock Disable
// <i> Indicates whether Quick Lock Disable is enabled or not
// <id> dfll_arch_qldis
#ifndef CONF_DFLL_QLDIS
#define CONF_DFLL_QLDIS 0
#endif
// <q> Chill Cycle Disable
// <i> Indicates whether Chill Cycle Disable is enabled or not
// <id> dfll_arch_ccdis
#ifndef CONF_DFLL_CCDIS
#define CONF_DFLL_CCDIS 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> dfll_arch_ondemand
#ifndef CONF_DFLL_ONDEMAND
#define CONF_DFLL_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> dfll_arch_runstdby
#ifndef CONF_DFLL_RUNSTDBY
#define CONF_DFLL_RUNSTDBY 0
#endif
// <q> USB Clock Recovery Mode
// <i> Indicates whether USB Clock Recovery Mode is enabled or not
// <id> dfll_arch_usbcrm
#ifndef CONF_DFLL_USBCRM
#define CONF_DFLL_USBCRM 0
#endif
// <q> Lose Lock After Wake
// <i> Indicates whether Lose Lock After Wake is enabled or not
// <id> dfll_arch_llaw
#ifndef CONF_DFLL_LLAW
#define CONF_DFLL_LLAW 0
#endif
// <q> Stable DFLL Frequency
// <i> Indicates whether Stable DFLL Frequency is enabled or not
// <id> dfll_arch_stable
#ifndef CONF_DFLL_STABLE
#define CONF_DFLL_STABLE 0
#endif
// <o> Operating Mode Selection
// <0=>Open Loop Mode
// <1=>Closed Loop Mode
// <id> dfll48m_mode
#ifndef CONF_DFLL_MODE
#define CONF_DFLL_MODE 0
#endif
// <o> Coarse Maximum Step <0x0-0x1F>
// <id> dfll_arch_cstep
#ifndef CONF_DFLL_CSTEP
#define CONF_DFLL_CSTEP 1
#endif
// <o> Fine Maximum Step <0x0-0x3FF>
// <id> dfll_arch_fstep
#ifndef CONF_DFLL_FSTEP
#define CONF_DFLL_FSTEP 1
#endif
// <o> DFLL Multiply Factor <0x0-0xFFFF>
// <id> dfll48m_mul
#ifndef CONF_DFLL_MUL
#define CONF_DFLL_MUL 0
#endif
// <e> DFLL Calibration Overwrite
// <i> Indicates whether Overwrite Calibration value of DFLL
// <id> dfll_arch_calibration
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
#endif
// <o> Coarse Value <0x0-0x3F>
// <id> dfll_arch_coarse
#ifndef CONF_DFLL_COARSE
#define CONF_DFLL_COARSE (0x1f / 4)
#endif
// <o> Fine Value <0x0-0x3FF>
// <id> dfll_arch_fine
#ifndef CONF_DFLL_FINE
#define CONF_DFLL_FINE (0x200)
#endif
//</e>
//</h>
//</e>
// <e> DPLL Configuration
// <i> Indicates whether configuration for DPLL is enabled or not
// <id> enable_fdpll96m
#ifndef CONF_DPLL_CONFIG
#define CONF_DPLL_CONFIG 0
#endif
// <y> Reference Clock Source
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source.
// <id> fdpll96m_ref_clock
#ifndef CONF_DPLL_GCLK
#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K
#endif
// <h> Digital Phase Locked Loop Control
// <q> Enable
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
// <id> fdpll96m_arch_enable
#ifndef CONF_DPLL_ENABLE
#define CONF_DPLL_ENABLE 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> fdpll96m_arch_ondemand
#ifndef CONF_DPLL_ONDEMAND
#define CONF_DPLL_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> fdpll96m_arch_runstdby
#ifndef CONF_DPLL_RUNSTDBY
#define CONF_DPLL_RUNSTDBY 0
#endif
// <o> Loop Divider Ratio Fractional Part <0x0-0xF>
// <id> fdpll96m_ldrfrac
#ifndef CONF_DPLL_LDRFRAC
#define CONF_DPLL_LDRFRAC 0xd
#endif
// <o> Loop Divider Ratio Integer Part <0x0-0xFFF>
// <id> fdpll96m_ldr
#ifndef CONF_DPLL_LDR
#define CONF_DPLL_LDR 0x5b7
#endif
// <o> Clock Divider <0x0-0x3FF>
// <id> fdpll96m_clock_div
#ifndef CONF_DPLL_DIV
#define CONF_DPLL_DIV 0
#endif
// <q> Lock Bypass
// <i> Indicates whether Lock Bypass is enabled or not
// <id> fdpll96m_arch_lbypass
#ifndef CONF_DPLL_LBYPASS
#define CONF_DPLL_LBYPASS 0
#endif
// <o> Lock Time
// <0=>No time-out, automatic lock
// <4=>The Time-out if no lock within 8 ms
// <5=>The Time-out if no lock within 9 ms
// <6=>The Time-out if no lock within 10 ms
// <7=>The Time-out if no lock within 11 ms
// <id> fdpll96m_arch_ltime
#ifndef CONF_DPLL_LTIME
#define CONF_DPLL_LTIME 0
#endif
// <o> Reference Clock Selection
// <0=>XOSC32K clock reference
// <1=>XOSC clock reference
// <2=>GCLK clock reference
// <id> fdpll96m_arch_refclk
#ifndef CONF_DPLL_REFCLK
#define CONF_DPLL_REFCLK 0
#endif
// <q> Wake Up Fast
// <i> Indicates whether Wake Up Fast is enabled or not
// <id> fdpll96m_arch_wuf
#ifndef CONF_DPLL_WUF
#define CONF_DPLL_WUF 0
#endif
// <q> Low-Power Enable
// <i> Indicates whether Low-Power Enable is enabled or not
// <id> fdpll96m_arch_lpen
#ifndef CONF_DPLL_LPEN
#define CONF_DPLL_LPEN 0
#endif
// <o> Reference Clock Selection
// <0=>Default filter mode
// <1=>Low bandwidth filter
// <2=>High bandwidth filter
// <3=>High damping filter
// <id> fdpll96m_arch_filter
#ifndef CONF_DPLL_FILTER
#define CONF_DPLL_FILTER 0
#endif
// <y> Output Clock Prescaler
// <OSCCTRL_DPLLPRESC_PRESC_DIV1_Val"> 1
// <OSCCTRL_DPLLPRESC_PRESC_DIV2_Val"> 2
// <OSCCTRL_DPLLPRESC_PRESC_DIV4_Val"> 4
// <id> fdpll96m_presc
#ifndef CONF_DPLL_PRESC
#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val
#endif
//</h>
//</e>
// <<< end of configuration section >>>
#endif // HPL_OSCCTRL_CONFIG_H

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/* Auto-generated config file hpl_port_config.h */
#ifndef HPL_PORT_CONFIG_H
#define HPL_PORT_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> PORT Input Event 0 configuration
// <id> enable_port_input_event_0
#ifndef CONF_PORT_EVCTRL_PORT_0
#define CONF_PORT_EVCTRL_PORT_0 0
#endif
// <h> PORT Input Event 0 configuration on PORT A
// <q> PORTA Input Event 0 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
// <id> porta_input_event_enable_0
#ifndef CONF_PORTA_EVCTRL_PORTEI_0
#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
#endif
// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_0
#ifndef CONF_PORTA_EVCTRL_PID_0
#define CONF_PORTA_EVCTRL_PID_0 0x0
#endif
// <o> PORTA Event 0 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 0
// <id> porta_event_action_0
#ifndef CONF_PORTA_EVCTRL_EVACT_0
#define CONF_PORTA_EVCTRL_EVACT_0 0
#endif
// </h>
// <h> PORT Input Event 0 configuration on PORT B
// <q> PORTB Input Event 0 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
// <id> portb_input_event_enable_0
#ifndef CONF_PORTB_EVCTRL_PORTEI_0
#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
#endif
// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_0
#ifndef CONF_PORTB_EVCTRL_PID_0
#define CONF_PORTB_EVCTRL_PID_0 0x0
#endif
// <o> PORTB Event 0 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 0
// <id> portb_event_action_0
#ifndef CONF_PORTB_EVCTRL_EVACT_0
#define CONF_PORTB_EVCTRL_EVACT_0 0
#endif
// </h>
// </e>
// <e> PORT Input Event 1 configuration
// <id> enable_port_input_event_1
#ifndef CONF_PORT_EVCTRL_PORT_1
#define CONF_PORT_EVCTRL_PORT_1 0
#endif
// <h> PORT Input Event 1 configuration on PORT A
// <q> PORTA Input Event 1 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
// <id> porta_input_event_enable_1
#ifndef CONF_PORTA_EVCTRL_PORTEI_1
#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
#endif
// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_1
#ifndef CONF_PORTA_EVCTRL_PID_1
#define CONF_PORTA_EVCTRL_PID_1 0x0
#endif
// <o> PORTA Event 1 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 1
// <id> porta_event_action_1
#ifndef CONF_PORTA_EVCTRL_EVACT_1
#define CONF_PORTA_EVCTRL_EVACT_1 0
#endif
// </h>
// <h> PORT Input Event 1 configuration on PORT B
// <q> PORTB Input Event 1 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
// <id> portb_input_event_enable_1
#ifndef CONF_PORTB_EVCTRL_PORTEI_1
#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
#endif
// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_1
#ifndef CONF_PORTB_EVCTRL_PID_1
#define CONF_PORTB_EVCTRL_PID_1 0x0
#endif
// <o> PORTB Event 1 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 1
// <id> portb_event_action_1
#ifndef CONF_PORTB_EVCTRL_EVACT_1
#define CONF_PORTB_EVCTRL_EVACT_1 0
#endif
// </h>
// </e>
// <e> PORT Input Event 2 configuration
// <id> enable_port_input_event_2
#ifndef CONF_PORT_EVCTRL_PORT_2
#define CONF_PORT_EVCTRL_PORT_2 0
#endif
// <h> PORT Input Event 2 configuration on PORT A
// <q> PORTA Input Event 2 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
// <id> porta_input_event_enable_2
#ifndef CONF_PORTA_EVCTRL_PORTEI_2
#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
#endif
// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_2
#ifndef CONF_PORTA_EVCTRL_PID_2
#define CONF_PORTA_EVCTRL_PID_2 0x0
#endif
// <o> PORTA Event 2 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 2
// <id> porta_event_action_2
#ifndef CONF_PORTA_EVCTRL_EVACT_2
#define CONF_PORTA_EVCTRL_EVACT_2 0
#endif
// </h>
// <h> PORT Input Event 2 configuration on PORT B
// <q> PORTB Input Event 2 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
// <id> portb_input_event_enable_2
#ifndef CONF_PORTB_EVCTRL_PORTEI_2
#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
#endif
// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_2
#ifndef CONF_PORTB_EVCTRL_PID_2
#define CONF_PORTB_EVCTRL_PID_2 0x0
#endif
// <o> PORTB Event 2 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 2
// <id> portb_event_action_2
#ifndef CONF_PORTB_EVCTRL_EVACT_2
#define CONF_PORTB_EVCTRL_EVACT_2 0
#endif
// </h>
// </e>
// <e> PORT Input Event 3 configuration
// <id> enable_port_input_event_3
#ifndef CONF_PORT_EVCTRL_PORT_3
#define CONF_PORT_EVCTRL_PORT_3 0
#endif
// <h> PORT Input Event 3 configuration on PORT A
// <q> PORTA Input Event 3 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
// <id> porta_input_event_enable_3
#ifndef CONF_PORTA_EVCTRL_PORTEI_3
#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
#endif
// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_3
#ifndef CONF_PORTA_EVCTRL_PID_3
#define CONF_PORTA_EVCTRL_PID_3 0x0
#endif
// <o> PORTA Event 3 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 3
// <id> porta_event_action_3
#ifndef CONF_PORTA_EVCTRL_EVACT_3
#define CONF_PORTA_EVCTRL_EVACT_3 0
#endif
// </h>
// <h> PORT Input Event 3 configuration on PORT B
// <q> PORTB Input Event 3 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
// <id> portb_input_event_enable_3
#ifndef CONF_PORTB_EVCTRL_PORTEI_3
#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
#endif
// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_3
#ifndef CONF_PORTB_EVCTRL_PID_3
#define CONF_PORTB_EVCTRL_PID_3 0x0
#endif
// <o> PORTB Event 3 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 3
// <id> portb_event_action_3
#ifndef CONF_PORTB_EVCTRL_EVACT_3
#define CONF_PORTB_EVCTRL_EVACT_3 0
#endif
// </h>
// </e>
#define CONF_PORTA_EVCTRL \
(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
| PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
| CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
| PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
| PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
| CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
#define CONF_PORTB_EVCTRL \
(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
| PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
| CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
| PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
| PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
| CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
// <<< end of configuration section >>>
#endif // HPL_PORT_CONFIG_H

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/* Auto-generated config file hpl_rtc_config.h */
#ifndef HPL_RTC_CONFIG_H
#define HPL_RTC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic settings
#ifndef CONF_RTC_ENABLE
#define CONF_RTC_ENABLE 1
#endif
// <q> Force reset RTC on initialization
// <i> Force RTC to reset on initialization.
// <i> Note that the previous power down data in RTC is lost if it's enabled.
// <id> rtc_arch_init_reset
#ifndef CONF_RTC_INIT_RESET
#define CONF_RTC_INIT_RESET 0
#endif
// <o> Prescaler configuration
// <0x0=>OFF(Peripheral clock divided by 1)
// <0x1=>Peripheral clock divided by 1
// <0x2=>Peripheral clock divided by 2
// <0x3=>Peripheral clock divided by 4
// <0x4=>Peripheral clock divided by 8
// <0x5=>Peripheral clock divided by 16
// <0x6=>Peripheral clock divided by 32
// <0x7=>Peripheral clock divided by 64
// <0x8=>Peripheral clock divided by 128
// <0x9=>Peripheral clock divided by 256
// <0xA=>Peripheral clock divided by 512
// <0xB=>Peripheral clock divided by 1024
// <i> These bits define the RTC clock relative to the peripheral clock
// <id> rtc_arch_prescaler
#ifndef CONF_RTC_PRESCALER
#define CONF_RTC_PRESCALER 0xb
#endif
#ifndef CONF_RTC_COMP_VAL
#define CONF_RTC_COMP_VAL 0
#endif
// <e> RTC Tamper Input 0 settings
// <id> tamper_input_0_settings
#ifndef CONF_TAMPER_INPUT_0_SETTINGS
#define CONF_TAMPER_INPUT_0_SETTINGS 0
#endif
// <q> Tamper Level Settings
// <i> Indicates Tamper input 0 level
// <id> tamper_level_0
#ifndef CONF_RTC_TAMP_LVL_0
#define CONF_RTC_TAMP_LVL_0 0
#endif
// <o> RTC Tamper Input Action
// <0x0=>OFF(Disabled)
// <0x1=>Wake and Set Tamper Flag
// <0x2=>Capture Timestamp and Set Tamper Flag
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
// <i> These bits define the RTC Tamper Input Action to be performed
// <id> rtc_tamper_input_action_0
#ifndef CONF_RTC_TAMPER_INACT_0
#define CONF_RTC_TAMPER_INACT_0 0
#endif
// <q> Debounce Enable for Tamper Input
// <i> Indicates Debounce should be enabled for Tamper input 0
// <id> tamper_debounce_enable_0
#ifndef CONF_RTC_TAMP_DEBNC_0
#define CONF_RTC_TAMP_DEBNC_0 0
#endif
// </e>
// <e> RTC Tamper Input 1 settings
// <id> tamper_input_1_settings
#ifndef CONF_TAMPER_INPUT_1_SETTINGS
#define CONF_TAMPER_INPUT_1_SETTINGS 0
#endif
// <q> Tamper Level Settings
// <i> Indicates Tamper input 1 level
// <id> tamper_level_1
#ifndef CONF_RTC_TAMP_LVL_1
#define CONF_RTC_TAMP_LVL_1 0
#endif
// <o> RTC Tamper Input Action
// <0x0=>OFF(Disabled)
// <0x1=>Wake and Set Tamper Flag
// <0x2=>Capture Timestamp and Set Tamper Flag
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
// <i> These bits define the RTC Tamper Input Action to be performed
// <id> rtc_tamper_input_action_1
#ifndef CONF_RTC_TAMPER_INACT_1
#define CONF_RTC_TAMPER_INACT_1 0
#endif
// <q> Debounce Enable for Tamper Input
// <i> Indicates Debounce should be enabled for Tamper input 1
// <id> tamper_debounce_enable_1
#ifndef CONF_RTC_TAMP_DEBNC_1
#define CONF_RTC_TAMP_DEBNC_1 0
#endif
// </e>
// <e> RTC Tamper Input 2 settings
// <id> tamper_input_2_settings
#ifndef CONF_TAMPER_INPUT_2_SETTINGS
#define CONF_TAMPER_INPUT_2_SETTINGS 0
#endif
// <q> Tamper Level Settings
// <i> Indicates Tamper input 2 level
// <id> tamper_level_2
#ifndef CONF_RTC_TAMP_LVL_2
#define CONF_RTC_TAMP_LVL_2 0
#endif
// <o> RTC Tamper Input Action
// <0x0=>OFF(Disabled)
// <0x1=>Wake and Set Tamper Flag
// <0x2=>Capture Timestamp and Set Tamper Flag
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
// <i> These bits define the RTC Tamper Input Action to be performed
// <id> rtc_tamper_input_action_2
#ifndef CONF_RTC_TAMPER_INACT_2
#define CONF_RTC_TAMPER_INACT_2 0
#endif
// <q> Debounce Enable for Tamper Input
// <i> Indicates Debounce should be enabled for Tamper input 2
// <id> tamper_debounce_enable_2
#ifndef CONF_RTC_TAMP_DEBNC_2
#define CONF_RTC_TAMP_DEBNC_2 0
#endif
// </e>
// <e> RTC Tamper Input 3 settings
// <id> tamper_input_3_settings
#ifndef CONF_TAMPER_INPUT_3_SETTINGS
#define CONF_TAMPER_INPUT_3_SETTINGS 0
#endif
// <q> Tamper Level Settings
// <i> Indicates Tamper input 3 level
// <id> tamper_level_3
#ifndef CONF_RTC_TAMP_LVL_3
#define CONF_RTC_TAMP_LVL_3 0
#endif
// <o> RTC Tamper Input Action
// <0x0=>OFF(Disabled)
// <0x1=>Wake and Set Tamper Flag
// <0x2=>Capture Timestamp and Set Tamper Flag
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
// <i> These bits define the RTC Tamper Input Action to be performed
// <id> rtc_tamper_input_action_3
#ifndef CONF_RTC_TAMPER_INACT_3
#define CONF_RTC_TAMPER_INACT_3 0
#endif
// <q> Debounce Enable for Tamper Input
// <i> Indicates Debounce should be enabled for Tamper input 3
// <id> tamper_debounce_enable_3
#ifndef CONF_RTC_TAMP_DEBNC_3
#define CONF_RTC_TAMP_DEBNC_3 0
#endif
// </e>
// <e> RTC Tamper Input 4 settings
// <id> tamper_input_4_settings
#ifndef CONF_TAMPER_INPUT_4_SETTINGS
#define CONF_TAMPER_INPUT_4_SETTINGS 0
#endif
// <q> Tamper Level Settings
// <i> Indicates Tamper input 4 level
// <id> tamper_level_4
#ifndef CONF_RTC_TAMP_LVL_4
#define CONF_RTC_TAMP_LVL_4 0
#endif
// <o> RTC Tamper Input Action
// <0x0=>OFF(Disabled)
// <0x1=>Wake and Set Tamper Flag
// <0x2=>Capture Timestamp and Set Tamper Flag
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
// <i> These bits define the RTC Tamper Input Action to be performed
// <id> rtc_tamper_input_action_4
#ifndef CONF_RTC_TAMPER_INACT_4
#define CONF_RTC_TAMPER_INACT_4 0
#endif
// <q> Debounce Enable for Tamper Input
// <i> Indicates Debounce should be enabled for Tamper input 4
// <id> tamper_debounce_enable_4
#ifndef CONF_RTC_TAMP_DEBNC_4
#define CONF_RTC_TAMP_DEBNC_4 0
#endif
// </e>
// <o> RTC Tamper Active Layer Frequency Prescalar
// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2
// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4
// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8
// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16
// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32
// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64
// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128
// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256
// <i> These bits define the RTC Tamper Active Layer Frequecny Prescalar
// <id> rtc_tamper_active_layer_frequency_prescalar
#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES
#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0
#endif
// <o> RTC Tamper Debounce Frequency Prescalar
// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2
// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4
// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8
// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16
// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32
// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64
// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128
// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256
// <i> These bits define the RTC Debounce Frequency Prescalar
// <id> rtc_tamper_debounce_frequency_prescalar
#ifndef CONF_RTC_TAMP_DEBF_PRES
#define CONF_RTC_TAMP_DEBF_PRES 0
#endif
// <e> Event control
// <id> rtc_event_control
#ifndef CONF_RTC_EVENT_CONTROL_ENABLE
#define CONF_RTC_EVENT_CONTROL_ENABLE 0
#endif
// <q> Periodic Interval 0 Event Output
// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated
// <id> rtc_pereo0
#ifndef CONF_RTC_PEREO0
#define CONF_RTC_PEREO0 0
#endif
// <q> Periodic Interval 1 Event Output
// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated
// <id> rtc_pereo1
#ifndef CONF_RTC_PEREO1
#define CONF_RTC_PEREO1 0
#endif
// <q> Periodic Interval 2 Event Output
// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated
// <id> rtc_pereo2
#ifndef CONF_RTC_PEREO2
#define CONF_RTC_PEREO2 0
#endif
// <q> Periodic Interval 3 Event Output
// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated
// <id> rtc_pereo3
#ifndef CONF_RTC_PEREO3
#define CONF_RTC_PEREO3 0
#endif
// <q> Periodic Interval 4 Event Output
// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated
// <id> rtc_pereo4
#ifndef CONF_RTC_PEREO4
#define CONF_RTC_PEREO4 0
#endif
// <q> Periodic Interval 5 Event Output
// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated
// <id> rtc_pereo5
#ifndef CONF_RTC_PEREO5
#define CONF_RTC_PEREO5 0
#endif
// <q> Periodic Interval 6 Event Output
// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated
// <id> rtc_pereo6
#ifndef CONF_RTC_PEREO6
#define CONF_RTC_PEREO6 0
#endif
// <q> Periodic Interval 7 Event Output
// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated
// <id> rtc_pereo7
#ifndef CONF_RTC_PEREO7
#define CONF_RTC_PEREO7 0
#endif
// <q> Compare 0 Event Output
// <i> This bit indicates whether Compare O event is enabled and will be generated
// <id> rtc_cmpeo0
#ifndef CONF_RTC_COMPE0
#define CONF_RTC_COMPE0 0
#endif
// <q> Overflow Event Output
// <i> This bit indicates whether Overflow event is enabled and will be generated
// <id> rtc_ovfeo
#ifndef CONF_RTC_OVFEO
#define CONF_RTC_OVFEO 0
#endif
// </e>
// </h>
// <<< end of configuration section >>>
#endif // HPL_RTC_CONFIG_H

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/* Auto-generated config file hpl_sercom_config.h */
#ifndef HPL_SERCOM_CONFIG_H
#define HPL_SERCOM_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
#endif
#ifndef CONF_SERCOM_1_I2CM_ENABLE
#define CONF_SERCOM_1_I2CM_ENABLE 1
#endif
// <h> Basic
// <o> I2C Bus clock speed (Hz) <1-400000>
// <i> I2C Bus clock (SCL) speed measured in Hz
// <id> i2c_master_baud_rate
#ifndef CONF_SERCOM_1_I2CM_BAUD
#define CONF_SERCOM_1_I2CM_BAUD 100000
#endif
// </h>
// <e> Advanced
// <id> i2c_master_advanced
#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG
#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0
#endif
// <o> TRise (ns) <0-300>
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
// <i> Standard Fast Mode: typical 215ns, max 300ns
// <i> Fast Mode +: typical 60ns, max 100ns
// <i> High Speed Mode: typical 20ns, max 40ns
// <id> i2c_master_arch_trise
#ifndef CONF_SERCOM_1_I2CM_TRISE
#define CONF_SERCOM_1_I2CM_TRISE 215
#endif
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
// <i> This enables the master SCL low extend time-out
// <id> i2c_master_arch_mexttoen
#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN
#define CONF_SERCOM_1_I2CM_MEXTTOEN 0
#endif
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
// <id> i2c_master_arch_sexttoen
#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN
#define CONF_SERCOM_1_I2CM_SEXTTOEN 0
#endif
// <q> SCL Low Time-Out (LOWTOUT)
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
// <id> i2c_master_arch_lowtout
#ifndef CONF_SERCOM_1_I2CM_LOWTOUT
#define CONF_SERCOM_1_I2CM_LOWTOUT 0
#endif
// <o> Inactive Time-Out (INACTOUT)
// <0x0=>Disabled
// <0x1=>5-6 SCL cycle time-out(50-60us)
// <0x2=>10-11 SCL cycle time-out(100-110us)
// <0x3=>20-21 SCL cycle time-out(200-210us)
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
// <id> i2c_master_arch_inactout
#ifndef CONF_SERCOM_1_I2CM_INACTOUT
#define CONF_SERCOM_1_I2CM_INACTOUT 0x0
#endif
// <o> SDA Hold Time (SDAHOLD)
// <0=>Disabled
// <1=>50-100ns hold time
// <2=>300-600ns hold time
// <3=>400-800ns hold time
// <i> Defines the SDA hold time with respect to the negative edge of SCL
// <id> i2c_master_arch_sdahold
#ifndef CONF_SERCOM_1_I2CM_SDAHOLD
#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2
#endif
// <q> Run in stand-by
// <i> Determine if the module shall run in standby sleep mode
// <id> i2c_master_arch_runstdby
#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY
#define CONF_SERCOM_1_I2CM_RUNSTDBY 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> i2c_master_arch_dbgstop
#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE
#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_1_I2CM_SPEED
#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
#endif
#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
#undef CONF_SERCOM_1_I2CM_TRISE
#define CONF_SERCOM_1_I2CM_TRISE 215U
#endif
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
// BAUD + BAUDLOW = --------------------------------------------------------------------
// i2c_scl_freq
// BAUD: register value low [7:0]
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \
(((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \
- (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \
/ 1000U)) \
* 10U \
+ 5U) \
/ (CONF_SERCOM_1_I2CM_BAUD * 10U))
#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE
#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2)
#warning Requested I2C baudrate too low, please check
#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF
#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1
#warning Requested I2C baudrate too high, please check
#define CONF_SERCOM_1_I2CM_BAUD_RATE 1
#else
#define CONF_SERCOM_1_I2CM_BAUD_RATE \
((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \
? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
: (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2))
#endif
#endif
#include <peripheral_clk_config.h>
// Enable configuration of module
#ifndef CONF_SERCOM_3_SPI_ENABLE
#define CONF_SERCOM_3_SPI_ENABLE 1
#endif
// Set module in SPI Master mode
#ifndef CONF_SERCOM_3_SPI_MODE
#define CONF_SERCOM_3_SPI_MODE 0x03
#endif
// <h> Basic Configuration
// <q> Receive buffer enable
// <i> Enable receive buffer to receive data from slave (RXEN)
// <id> spi_master_rx_enable
#ifndef CONF_SERCOM_3_SPI_RXEN
#define CONF_SERCOM_3_SPI_RXEN 0x1
#endif
// <o> Character Size
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
// <0x0=>8 bits
// <0x1=>9 bits
// <id> spi_master_character_size
#ifndef CONF_SERCOM_3_SPI_CHSIZE
#define CONF_SERCOM_3_SPI_CHSIZE 0x0
#endif
// <o> Baud rate <1-12000000>
// <i> The SPI data transfer rate
// <id> spi_master_baud_rate
#ifndef CONF_SERCOM_3_SPI_BAUD
#define CONF_SERCOM_3_SPI_BAUD 50000
#endif
// </h>
// <e> Advanced Configuration
// <id> spi_master_advanced
#ifndef CONF_SERCOM_3_SPI_ADVANCED
#define CONF_SERCOM_3_SPI_ADVANCED 1
#endif
// <o> Dummy byte <0x00-0x1ff>
// <id> spi_master_dummybyte
// <i> Dummy byte used when reading data from the slave without sending any data
#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE
#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff
#endif
// <o> Data Order
// <0=>MSB first
// <1=>LSB first
// <i> I least significant or most significant bit is shifted out first (DORD)
// <id> spi_master_arch_dord
#ifndef CONF_SERCOM_3_SPI_DORD
#define CONF_SERCOM_3_SPI_DORD 0x0
#endif
// <o> Clock Polarity
// <0=>SCK is low when idle
// <1=>SCK is high when idle
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
// <id> spi_master_arch_cpol
#ifndef CONF_SERCOM_3_SPI_CPOL
#define CONF_SERCOM_3_SPI_CPOL 0x0
#endif
// <o> Clock Phase
// <0x0=>Sample input on leading edge
// <0x1=>Sample input on trailing edge
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
// <id> spi_master_arch_cpha
#ifndef CONF_SERCOM_3_SPI_CPHA
#define CONF_SERCOM_3_SPI_CPHA 0x0
#endif
// <o> Immediate Buffer Overflow Notification
// <i> Controls when OVF is asserted (IBON)
// <0x0=>In data stream
// <0x1=>On buffer overflow
// <id> spi_master_arch_ibon
#ifndef CONF_SERCOM_3_SPI_IBON
#define CONF_SERCOM_3_SPI_IBON 0x0
#endif
// <q> Run in stand-by
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
// <id> spi_master_arch_runstdby
#ifndef CONF_SERCOM_3_SPI_RUNSTDBY
#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
// <0=>Keep running
// <1=>Halt
// <id> spi_master_arch_dbgstop
#ifndef CONF_SERCOM_3_SPI_DBGSTOP
#define CONF_SERCOM_3_SPI_DBGSTOP 0
#endif
// </e>
// Address mode disabled in master mode
#ifndef CONF_SERCOM_3_SPI_AMODE_EN
#define CONF_SERCOM_3_SPI_AMODE_EN 0
#endif
#ifndef CONF_SERCOM_3_SPI_AMODE
#define CONF_SERCOM_3_SPI_AMODE 0
#endif
#ifndef CONF_SERCOM_3_SPI_ADDR
#define CONF_SERCOM_3_SPI_ADDR 0
#endif
#ifndef CONF_SERCOM_3_SPI_ADDRMASK
#define CONF_SERCOM_3_SPI_ADDRMASK 0
#endif
#ifndef CONF_SERCOM_3_SPI_SSDE
#define CONF_SERCOM_3_SPI_SSDE 0
#endif
#ifndef CONF_SERCOM_3_SPI_MSSEN
#define CONF_SERCOM_3_SPI_MSSEN 0x0
#endif
#ifndef CONF_SERCOM_3_SPI_PLOADEN
#define CONF_SERCOM_3_SPI_PLOADEN 0
#endif
// <o> Receive Data Pinout
// <0x0=>PAD[0]
// <0x1=>PAD[1]
// <0x2=>PAD[2]
// <0x3=>PAD[3]
// <id> spi_master_rxpo
#ifndef CONF_SERCOM_3_SPI_RXPO
#define CONF_SERCOM_3_SPI_RXPO 2
#endif
// <o> Transmit Data Pinout
// <0x0=>PAD[0,1]_DO_SCK
// <0x1=>PAD[2,3]_DO_SCK
// <0x2=>PAD[3,1]_DO_SCK
// <0x3=>PAD[0,3]_DO_SCK
// <id> spi_master_txpo
#ifndef CONF_SERCOM_3_SPI_TXPO
#define CONF_SERCOM_3_SPI_TXPO 3
#endif
// Calculate baud register value from requested baudrate value
#ifndef CONF_SERCOM_3_SPI_BAUD_RATE
#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1
#endif
// <<< end of configuration section >>>
#endif // HPL_SERCOM_CONFIG_H

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/* Auto-generated config file hpl_slcd_config.h */
#ifndef HPL_SLCD_CONFIG_H
#define HPL_SLCD_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <hpl_slcd_cm.h>
#include <peripheral_clk_config.h>
#include "pins.h"
// <h> Standard configuration
// <o> Number of COM Lines
// <i> Number of COM Lines
// <0=>1
// <1=>2
// <2=>3
// <3=>4
// <4=>6
// <5=>8
// <id> slcd_arch_com_num
#ifndef CONF_SLCD_COM_NUM
#define CONF_SLCD_COM_NUM 2
#endif
// <o> Number of Segment Lines <1-44>
// <i> Number of Segment Lines
// <id> slcd_arch_seg_num
#ifndef CONF_SLCD_SEG_NUM
#define CONF_SLCD_SEG_NUM 24
#endif
#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_SIXTH_Val && CONF_SLCD_SEG_NUM > 42
#warning Segment number should less than or equals to 42
#endif
#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_EIGHT_Val && CONF_SLCD_SEG_NUM > 40
#warning Segment number should less than or equals to 40
#endif
// <o> Bias
// <i> Bias Settting
// <0=>STATIC
// <1=>HALF
// <2=>THIRD
// <3=>FOURTH
// <id> slcd_arch_bias
#ifndef CONF_SLCD_BIAS
#define CONF_SLCD_BIAS 2
#endif
#if CONF_SLCD_COM_NUM == 0 && CONF_SLCD_BIAS != 0
#warning Recommended Bias for 1 common terminal is STATIC
#elif CONF_SLCD_COM_NUM == 1 && CONF_SLCD_BIAS != 1
#warning Recommended Bias for 2 Common Terminals is HALF
#elif CONF_SLCD_COM_NUM <= 4 && CONF_SLCD_BIAS != 2
#warning Recommended Bias for 3/4/6 Common Terminals is THIRD
#elif CONF_SLCD_COM_NUM == 5 && CONF_SLCD_BIAS != 3
#warning Recommended Bias for 8 Common Terminals is FOURTH
#endif
// <q> Bias Buffer Enable
// <i> Enable Bias Buffer
// <id> slcd_arch_bben
#ifndef CONF_SLCD_BBEN
#define CONF_SLCD_BBEN 1
#endif
// <o> Bias Buffer Enable Duration <1-16>
// <i> Configure the enable duration of the bias buffer, unit is cycle of SLCD OSC clock source
// <id> slcd_arch_bbd
#ifndef CONF_SLCD_BBD
#define CONF_SLCD_BBD 2
#endif
// <o> Clock Prescaler
// <i> Setting for LCD frame frequency
// <0=>16
// <1=>32
// <2=>64
// <3=>128
// <id> slcd_arch_presc
#ifndef CONF_SLCD_PRESC
#define CONF_SLCD_PRESC 1
#endif
// <o> Clock Divider
// <i> Setting for LCD frame frequency
// <0=>1
// <1=>2
// <2=>3
// <3=>4
// <4=>5
// <5=>6
// <6=>7
// <7=>8
// <id> slcd_arch_ckdiv
#ifndef CONF_SLCD_CKDIV
#define CONF_SLCD_CKDIV 5
#endif
/* TODO add frame frequency check */
// <o> Reference Refresh Frequency
// <i> Setting for Reference Refresh Frequency
// <0=>2kHz
// <1=>1kHz
// <2=>500Hz
// <3=>250Hz
// <4=>125Hz
// <5=>62.5Hz
// <id> slcd_arch_rrf
#ifndef CONF_SLCD_RRF
#define CONF_SLCD_RRF 0
#endif
// <o> Power Refresh Frequency
// <i> Setting for Charge pump Refresh Frequency
// <0=>2kHz
// <1=>1kHz
// <2=>500Hz
// <3=>250Hz
// <id> slcd_arch_prf
#ifndef CONF_SLCD_PRF
#define CONF_SLCD_PRF 3
#endif
// <q> External VLCD
// <i> Setting for how VLCD is generated
// <id> slcd_arch_xvlcd
#ifndef CONF_SLCD_XVLCD
#define CONF_SLCD_XVLCD 0
#endif
// <o> Waveform Mode
// <i> Setting for Waveform Mode
// <0=>Low Power Waveform(frame-inversion)
// <1=>Standard Waveform Mode(bit-inversion)
// <id> slcd_arch_wmod
#ifndef CONF_SLCD_WMOD
#define CONF_SLCD_WMOD 0
#endif
// <o> Contrast Adjustment
// <i> The contrast of the LCD is determined by the value of VLCD voltage.
// <i> The higher the VLCD voltage, the higher is the contrast.
// <i> The software contrast adjustment is only possible in internal supply mode.
// <0=>2.5056V
// <1=>2.5731V
// <2=>2.6379V
// <3=>2.7054V
// <4=>2.7729V
// <5=>2.8404V
// <6=>2.9052V
// <7=>2.9727V
// <8=>3.0402V
// <9=>3.1077V
// <10=>3.1725V
// <11=>3.24V
// <12=>3.3075V
// <13=>3.375V
// <14=>3.4398V
// <15=>3.5073V
// <id> slcd_arch_contrast_adjust
#ifndef CONF_SLCD_CONTRAST_ADJUST
#define CONF_SLCD_CONTRAST_ADJUST 14
#endif
// </h>
// <e> Advanced configuration
// <id> slcd_arch_advanced_settings
#ifndef CONF_SLCD_ADVANCED_SETTINGS
#define CONF_SLCD_ADVANCED_SETTINGS 1
#endif
// <q> Run in standby
// <i> Indicates whether the SLCD will continue running in standby sleep mode or not
// <id> slcd_arch_runstdby
#ifndef CONF_SLCD_RUNSTDBY
#define CONF_SLCD_RUNSTDBY 1
#endif
// </e>
#if SLCD_FRAME_FREQUENCY < 30 || SLCD_FRAME_FREQUENCY > 100
#warning The optimal frame frequency should be in range from 30Hz up to 100Hz to avoid flickering and ghosting effect.
#endif
#define SLCD_FC_MAX_MS (((0x1F + 1) * 8) * (1000 / SLCD_FRAME_FREQUENCY))
#define SLCD_FC_MIN_MS (1000 / SLCD_FRAME_FREQUENCY)
#define SLCD_FC_BYPASS_MAX_MS ((0x1F + 1) * (1000 / SLCD_FRAME_FREQUENCY))
// <e> Character Mapping Setting
// <id> slcd_arch_cm_setting
#ifndef CONF_SLCD_CM_ENABLE
#define CONF_SLCD_CM_ENABLE 0
#endif
/**
* character lookup table
*/
#ifndef CONF_SLCD_LPENL
#define CONF_SLCD_LPENL (\
(uint32_t)1 << 0 | \
(uint32_t)1 << 1 | \
(uint32_t)1 << 2 | \
(uint32_t)1 << 3 | \
(uint32_t)1 << 4 | \
(uint32_t)1 << 5 | \
(uint32_t)1 << 6 | \
(uint32_t)1 << 7 | \
(uint32_t)1 << 11 | \
(uint32_t)1 << 12 | \
(uint32_t)1 << 13 | \
(uint32_t)1 << 14 | \
(uint32_t)1 << 21 | \
(uint32_t)1 << 22 | \
(uint32_t)1 << 23 | \
(uint32_t)1 << 24 | \
(uint32_t)1 << 25 | \
(uint32_t)1 << 28 | \
(uint32_t)1 << 29 | \
(uint32_t)1 << 30 | \
(uint32_t)1 << 31 | 0)
#endif // CONF_SLCD_LPENL
#ifndef CONF_SLCD_LPENH
#define CONF_SLCD_LPENH (\
(uint32_t)1 << (32 - 32) | \
(uint32_t)1 << (33 - 32) | \
(uint32_t)1 << (34 - 32) | \
(uint32_t)1 << (35 - 32) | \
(uint32_t)1 << (42 - 32) | \
(uint32_t)1 << (43 - 32) | 0)
#endif // CONF_SLCD_LPENH
// <<< end of configuration section >>>
#endif // HPL_SLCD_CONFIG_H

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/* Auto-generated config file hpl_systick_config.h */
#ifndef HPL_SYSTICK_CONFIG_H
#define HPL_SYSTICK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Advanced settings
// <q> SysTick exception request
// <i> Indicates whether the generation of SysTick exception is enabled or not
// <id> systick_arch_tickint
#ifndef CONF_SYSTICK_TICKINT
#define CONF_SYSTICK_TICKINT 0
#endif
// </h>
// <<< end of configuration section >>>
#endif // HPL_SYSTICK_CONFIG_H

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watch-library/shared/config/hpl_trng_config.h Executable file
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/* Auto-generated config file hpl_trng_config.h */
#ifndef HPL_TRNG_CONFIG_H
#define HPL_TRNG_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Advanced configurations
// <q> Run In Standby
// <i> Indicates whether the TRNG works in standby mode
// <id> trng_runstdby
#ifndef CONF_TRNG_RUNSTDBY
#define CONF_TRNG_RUNSTDBY 0
#endif
// <q> Data Ready Event Output Enable
// <i> Indicates whether the TRNG generates event on Data Ready
// <id> trng_datardyeo
#ifndef CONF_TRNG_DATARDYEO
#define CONF_TRNG_DATARDYEO 0
#endif
// </h>
// <<< end of configuration section >>>
#endif // HPL_TRNG_CONFIG_H

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watch-library/shared/config/nv_storage_config.h Executable file
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/* Auto-generated config file nv_storage_config.h */
#ifndef NV_STORAGE_CONFIG_H
#define NV_STORAGE_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
//<o> Storage start address <0x00000000-0xFFFFFFFF>
//<i> This defines the start address of device flash for storage.
//<i> The start address should be in device flash area.
//<i> The start address and (start address + Item Number * Sector size) cannot beyond device flash area.
//<id> conf_storage_memory_start
#ifndef CONF_STORAGE_MEMORY_START
#define CONF_STORAGE_MEMORY_START 0x10000
#endif
//<o> Item number <0-65535>
//<i> This defines the maximum number of elements stored in persistent storage
//<id> conf_max_item_number
#ifndef CONF_MAX_ITEM_NUMBER
#define CONF_MAX_ITEM_NUMBER 10
#endif
//<o> Sector size <0-65535>
//<i> This defines the size of one storage sector in bytes
//<id> conf_sector_size
#ifndef CONF_SECTOR_SIZE
#define CONF_SECTOR_SIZE 4096
#endif
/**
* Check If the Storage configuration out of the flash area.
*/
#ifdef FLASH_SIZE
#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > FLASH_SIZE
#error Invalidate storage configuration, make sure the configuration with \
the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \
are located within the device flash size.
#endif
#endif
#ifdef IFLASH_SIZE
#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > IFLASH_SIZE
#error Invalidate storage configuration, make sure the configuration with \
the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \
are located within the device flash size.
#endif
#endif
// <<< end of configuration section >>>
#endif // NV_STORAGE_CONFIG_H

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/* Auto-generated config file peripheral_clk_config.h */
#ifndef PERIPHERAL_CLK_CONFIG_H
#define PERIPHERAL_CLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <y> ADC Clock Source
// <id> adc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the clock source for ADC.
#ifndef CONF_GCLK_ADC_SRC
#define CONF_GCLK_ADC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_ADC_FREQUENCY
* \brief ADC's Clock frequency
*/
#ifndef CONF_GCLK_ADC_FREQUENCY
#define CONF_GCLK_ADC_FREQUENCY 4000000
#endif
// <y> EIC Clock Source
// <id> eic_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the clock source for EIC.
#ifndef CONF_GCLK_EIC_SRC
#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_EIC_FREQUENCY
* \brief EIC's Clock frequency
*/
#ifndef CONF_GCLK_EIC_FREQUENCY
#define CONF_GCLK_EIC_FREQUENCY 32768
#endif
/**
* \def CONF_CPU_FREQUENCY
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 4000000
#endif
// <y> RTC Clock Source
// <id> rtc_clk_selection
// <RTC_CLOCK_SOURCE"> RTC source
// <i> Select the clock source for RTC.
#ifndef CONF_GCLK_RTC_SRC
#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
#endif
/**
* \def CONF_GCLK_RTC_FREQUENCY
* \brief RTC's Clock frequency
*/
#ifndef CONF_GCLK_RTC_FREQUENCY
#define CONF_GCLK_RTC_FREQUENCY 1024
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM1_CORE_SRC
#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
* \brief SERCOM1's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 4000000
#endif
/**
* \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
* \brief SERCOM1's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM3_CORE_SRC
#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
* \brief SERCOM3's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 4000000
#endif
/**
* \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
* \brief SERCOM3's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
#endif
// <y> TC Clock Source
// <id> tc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC3_SRC
#define CONF_GCLK_TC3_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_TC3_FREQUENCY
* \brief TC3's Clock frequency
*/
#ifndef CONF_GCLK_TC3_FREQUENCY
#define CONF_GCLK_TC3_FREQUENCY 32768
#endif
// <y> TCC Clock Source
// <id> tcc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the clock source for TCC.
#ifndef CONF_GCLK_TCC0_SRC
#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_TCC0_FREQUENCY
* \brief TCC0's Clock frequency
*/
#ifndef CONF_GCLK_TCC0_FREQUENCY
#define CONF_GCLK_TCC0_FREQUENCY 16000000
#endif
#include <hpl_osc32kctrl_config.h>
// <y> SLCD Clock Source
// <id> slcd_clk_selection
// <SLCD_CLOCK_SOURCE"> SLCD source
// <i> Select the clock source for SLCD.
#ifndef CONF_GCLK_SLCD_SRC
#define CONF_GCLK_SLCD_SRC SLCD_CLOCK_SOURCE
#endif
/**
* \def CONF_GCLK_SLCD_FREQUENCY
* \brief SLCD's Clock frequency
*/
#ifndef CONF_GCLK_SLCD_FREQUENCY
#define CONF_GCLK_SLCD_FREQUENCY 32768
#endif
#ifndef SLCD_FRAME_FREQUENCY
#define SLCD_FRAME_FREQUENCY \
(CONF_GCLK_SLCD_FREQUENCY \
/ (((CONF_SLCD_PRESC + 1) * 16) * (CONF_SLCD_CKDIV + 1) \
* ((CONF_SLCD_COM_NUM == 4) ? 6 : ((CONF_SLCD_COM_NUM == 5) ? 8 : (CONF_SLCD_COM_NUM + 1)))))
#endif
// <<< end of configuration section >>>
#endif // PERIPHERAL_CLK_CONFIG_H

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/*
* MIT License
*
* Copyright (c) 2021 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "lis2dh.h"
#include "watch.h"
bool lis2dh_begin(void) {
if (lis2dh_get_device_id() != LIS2DH_WHO_AM_I_VAL) {
return false;
}
// Enable all axes, start at lowest possible data rate
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1, LIS2DH_CTRL1_VAL_XEN |
LIS2DH_CTRL1_VAL_YEN |
LIS2DH_CTRL1_VAL_ZEN |
LIS2DH_CTRL1_VAL_ODR_1HZ);
// Set range to ±2G and enable block data update (output registers not updated until MSB and LSB have been read)
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4, LIS2DH_CTRL4_VAL_BDU | LIS2DH_RANGE_2_G);
return true;
}
uint8_t lis2dh_get_device_id(void) {
return watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_WHO_AM_I);
}
bool lis2dh_have_new_data(void) {
uint8_t retval = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_STATUS);
return !!retval; // return true if any bit is set
}
lis2dh_reading lis2dh_get_raw_reading(void) {
uint8_t buffer[6];
uint8_t reg = LIS2DH_REG_OUT_X_L | 0x80; // set high bit for consecutive reads
lis2dh_reading retval;
watch_i2c_send(LIS2DH_ADDRESS, &reg, 1);
watch_i2c_receive(LIS2DH_ADDRESS, (uint8_t *)&buffer, 6);
retval.x = buffer[0];
retval.x |= ((uint16_t)buffer[1]) << 8;
retval.y = buffer[2];
retval.y |= ((uint16_t)buffer[3]) << 8;
retval.z = buffer[4];
retval.z |= ((uint16_t)buffer[5]) << 8;
return retval;
}
lis2dh_acceleration_measurement lis2dh_get_acceleration_measurement(lis2dh_reading *out_reading) {
lis2dh_reading reading = lis2dh_get_raw_reading();
uint8_t range = lis2dh_get_range();
if (out_reading != NULL) *out_reading = reading;
// this bit is cribbed from Adafruit's LIS3DH driver; from their notes, the magic number below
// converts from 16-bit lsb to 10-bit and divides by 1k to convert from milli-gs.
// final value is raw_lsb => 10-bit lsb -> milli-gs -> gs
uint8_t lsb_value = 1;
if (range == LIS2DH_RANGE_2_G) lsb_value = 4;
if (range == LIS2DH_RANGE_4_G) lsb_value = 8;
if (range == LIS2DH_RANGE_8_G) lsb_value = 16;
if (range == LIS2DH_RANGE_16_G) lsb_value = 48;
lis2dh_acceleration_measurement retval;
retval.x = lsb_value * ((float)reading.x / 64000.0);
retval.y = lsb_value * ((float)reading.y / 64000.0);
retval.z = lsb_value * ((float)reading.z / 64000.0);
return retval;
}
void lis2dh_set_range(lis2dh_range_t range) {
uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4) & 0xCF;
uint8_t bits = range << 4;
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4, val | bits);
}
lis2dh_range_t lis2dh_get_range(void) {
uint8_t retval = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4) & 0x30;
retval >>= 4;
return (lis2dh_range_t)retval;
}
void lis2dh_set_data_rate(lis2dh_data_rate_t dataRate) {
uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1) & 0x0F;
uint8_t bits = dataRate << 4;
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1, val | bits);
}
lis2dh_data_rate_t lis2dh_get_data_rate(void) {
return watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1) >> 4;
}
void lis2dh_configure_aoi_int1(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch) {
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL3, LIS2DH_CTRL3_VAL_I1_AOI1);
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_CFG, configuration);
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_THS, threshold);
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_DUR, duration);
uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5) & 0xF7;
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5, val | latch ? LIS2DH_CTRL5_VAL_LIR_INT1 : 0);
}
lis2dh_interrupt_state lis2dh_get_int1_state(void) {
return (lis2dh_interrupt_state) watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_SRC);
}
void lis2dh_configure_aoi_int2(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch) {
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL6, LIS2DH_CTRL6_VAL_I2_INT2);
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_CFG, configuration);
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_THS, threshold);
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_DUR, duration);
uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5) & 0xFD;
watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5, val | latch ? LIS2DH_CTRL5_VAL_LIR_INT2 : 0);
}
lis2dh_interrupt_state lis2dh_get_int2_state(void) {
return (lis2dh_interrupt_state) watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_SRC);
}

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/*
* MIT License
*
* Copyright (c) 2021 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef LIS2DH_H
#define LIS2DH_H
#include <stdbool.h>
#include <stdint.h>
typedef struct {
int16_t x;
int16_t y;
int16_t z;
} lis2dh_reading;
typedef struct {
float x;
float y;
float z;
} lis2dh_acceleration_measurement;
typedef enum {
LIS2DH_RANGE_16_G = 0b11, // +/- 16g
LIS2DH_RANGE_8_G = 0b10, // +/- 8g
LIS2DH_RANGE_4_G = 0b01, // +/- 4g
LIS2DH_RANGE_2_G = 0b00 // +/- 2g (default value)
} lis2dh_range_t;
typedef enum {
LIS2DH_DATA_RATE_POWERDOWN = 0,
LIS2DH_DATA_RATE_1_HZ = 0b0001,
LIS2DH_DATA_RATE_10_HZ = 0b0010,
LIS2DH_DATA_RATE_25_HZ = 0b0011,
LIS2DH_DATA_RATE_50_HZ = 0b0100,
LIS2DH_DATA_RATE_100_HZ = 0b0101,
LIS2DH_DATA_RATE_200_HZ = 0b0110,
LIS2DH_DATA_RATE_400_HZ = 0b0111,
LIS2DH_DATA_RATE_LP1620HZ = 0b1000,
LIS2DH_DATA_RATE_LP5376HZ = 0b1001,
} lis2dh_data_rate_t;
typedef enum {
LIS2DH_INTERRUPT_CONFIGURATION_OR = 0b00000000,
LIS2DH_INTERRUPT_CONFIGURATION_AND = 0b10000000,
LIS2DH_INTERRUPT_CONFIGURATION_6D_MOVEMENT = 0b01000000,
LIS2DH_INTERRUPT_CONFIGURATION_6D_POSITION = 0b11000000, // in 6D mode, these have an alternate meaning:
LIS2DH_INTERRUPT_CONFIGURATION_Z_HIGH_ENABLE = 0b00100000, // Z up enable
LIS2DH_INTERRUPT_CONFIGURATION_Z_LOW_ENABLE = 0b00010000, // Z down enable
LIS2DH_INTERRUPT_CONFIGURATION_Y_HIGH_ENABLE = 0b00001000, // Y up enable
LIS2DH_INTERRUPT_CONFIGURATION_Y_LOW_ENABLE = 0b00000100, // Y down enable
LIS2DH_INTERRUPT_CONFIGURATION_X_HIGH_ENABLE = 0b00000010, // X up enable
LIS2DH_INTERRUPT_CONFIGURATION_X_LOW_ENABLE = 0b00000001, // X down enable
} lis2dh_interrupt_configuration;
typedef enum {
LIS2DH_INTERRUPT_STATE_ACTIVE = 0b01000000,
LIS2DH_INTERRUPT_STATE_Z_HIGH = 0b00100000, // Z up
LIS2DH_INTERRUPT_STATE_Z_LOW = 0b00010000, // Z down
LIS2DH_INTERRUPT_STATE_Y_HIGH = 0b00001000, // Y up
LIS2DH_INTERRUPT_STATE_Y_LOW = 0b00000100, // Y down
LIS2DH_INTERRUPT_STATE_X_HIGH = 0b00000010, // X up
LIS2DH_INTERRUPT_STATE_X_LOW = 0b00000001, // X down
} lis2dh_interrupt_state;
bool lis2dh_begin(void);
uint8_t lis2dh_get_device_id(void);
bool lis2dh_have_new_data(void);
lis2dh_reading lis2dh_get_raw_reading(void);
lis2dh_acceleration_measurement lis2dh_get_acceleration_measurement(lis2dh_reading *out_reading);
void lis2dh_set_range(lis2dh_range_t range);
lis2dh_range_t lis2dh_get_range(void);
void lis2dh_set_data_rate(lis2dh_data_rate_t dataRate);
lis2dh_data_rate_t lis2dh_get_data_rate(void);
void lis2dh_configure_aoi_int1(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch);
lis2dh_interrupt_state lis2dh_get_int1_state(void);
void lis2dh_configure_aoi_int2(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch);
lis2dh_interrupt_state lis2dh_get_int2_state(void);
// Assumes SA0 is high; if low, its 0x18
#define LIS2DH_ADDRESS (0x19)
#define LIS2DH_REG_STATUS_AUX 0x07 ///< Auxiliary status register
#define LIS2DH_REG_STATUS_AUX_TDA (1 << 2) ///< Temperature data available
#define LIS2DH_REG_STATUS_AUX_TOR (1 << 6) ///< Temperature data overrun
#define LIS2DH_REG_OUT_TEMP_L 0x0C ///< Temperature data low bit
#define LIS2DH_REG_OUT_TEMP_H 0x0D ///< Temperature data high bit
#define LIS2DH_REG_INT_COUNTER 0x0E
#define LIS2DH_REG_WHO_AM_I 0x0F ///< Device identification, will read 0x33
#define LIS2DH_WHO_AM_I_VAL 0x33 ///< Expected value of the WHO_AM_I register
#define LIS2DH_REG_TEMP_CFG 0x1F ///< Temperature configuration; 0 to disable, 0xC0 to enable.
#define LIS2DH_TEMP_CFG_VAL_ENABLE 0xC0 ///< Value for LIS2DH_REG_TEMP_CFG that enables temperature sensing.
#define LIS2DH_TEMP_CFG_VAL_DISABLE 0x00 ///< Value for LIS2DH_REG_TEMP_CFG that disables temperature sensing.
#define LIS2DH_REG_CTRL1 0x20 ///< CTRL_REG1 in the data sheet.
#define LIS2DH_CTRL1_VAL_XEN 0b00000001 ///< Enable X-axis
#define LIS2DH_CTRL1_VAL_YEN 0b00000010 ///< Enable Y-axis
#define LIS2DH_CTRL1_VAL_ZEN 0b00000100 ///< Enable Z-axis
#define LIS2DH_CTRL1_VAL_LPEN 0b00001000 ///< Enable low power mode
#define LIS2DH_CTRL1_VAL_ODR_POWERDOWN 0 ///< Power down
#define LIS2DH_CTRL1_VAL_ODR_1HZ (LIS2DH_DATA_RATE_1_HZ << 4)
#define LIS2DH_CTRL1_VAL_ODR_10HZ (LIS2DH_DATA_RATE_10_HZ << 4)
#define LIS2DH_CTRL1_VAL_ODR_25HZ (LIS2DH_DATA_RATE_25_HZ << 4)
#define LIS2DH_CTRL1_VAL_ODR_50HZ (LIS2DH_DATA_RATE_50_HZ << 4)
#define LIS2DH_CTRL1_VAL_ODR_100HZ (LIS2DH_DATA_RATE_100_HZ << 4)
#define LIS2DH_CTRL1_VAL_ODR_200HZ (LIS2DH_DATA_RATE_200_HZ << 4)
#define LIS2DH_CTRL1_VAL_ODR_400HZ (LIS2DH_DATA_RATE_400_HZ << 4)
#define LIS2DH_CTRL1_VAL_ODR_LP1620HZ (LIS2DH_DATA_RATE_LP1620HZ << 4)
#define LIS2DH_CTRL1_VAL_ODR_LP5376HZ (LIS2DH_DATA_RATE_LP5376HZ << 4)
#define LIS2DH_REG_CTRL2 0x21
#define LIS2DH_REG_CTRL3 0x22
#define LIS2DH_CTRL3_VAL_I1_CLICK 0b10000000
#define LIS2DH_CTRL3_VAL_I1_AOI1 0b01000000
#define LIS2DH_CTRL3_VAL_I1_AOI2 0b00100000
#define LIS2DH_CTRL3_VAL_I1_DRDY1 0b00010000
#define LIS2DH_CTRL3_VAL_I1_DRDY2 0b00001000
#define LIS2DH_CTRL3_VAL_I1_WTM 0b00000100
#define LIS2DH_CTRL3_VAL_I1_OVERRUN 0b00000010
#define LIS2DH_REG_CTRL4 0x23
#define LIS2DH_CTRL4_VAL_BDU 0b10000000
#define LIS2DH_CTRL4_VAL_BLE 0b01000000
#define LIS2DH_CTRL4_VAL_RANGE_2G (LIS2DH_RANGE_2_G << 4)
#define LIS2DH_CTRL4_VAL_RANGE_4G (LIS2DH_RANGE_4_G << 4)
#define LIS2DH_CTRL4_VAL_RANGE_8G (LIS2DH_RANGE_8_G << 4)
#define LIS2DH_CTRL4_VAL_RANGE_16G (LIS2DH_RANGE_16_G << 4)
#define LIS2DH_CTRL4_VAL_HR 0b00001000
#define LIS2DH_CTRL4_VAL_ST0 0b00000000
#define LIS2DH_CTRL4_VAL_ST1 0b00000000
#define LIS2DH_REG_CTRL5 0x24
#define LIS2DH_CTRL5_VAL_BOOT 0b10000000
#define LIS2DH_CTRL5_VAL_FIFO_EN 0b01000000
#define LIS2DH_CTRL5_VAL_LIR_INT1 0b00001000
#define LIS2DH_CTRL5_VAL_D4D_INT1 0b00000100
#define LIS2DH_CTRL5_VAL_LIR_INT2 0b00000010
#define LIS2DH_CTRL5_VAL_D4D_INT2 0b00000001
#define LIS2DH_REG_CTRL6 0x25
#define LIS2DH_CTRL6_VAL_I2_CLICK 0b10000000
#define LIS2DH_CTRL6_VAL_I2_INT1 0b01000000
#define LIS2DH_CTRL6_VAL_I2_INT2 0b00100000
#define LIS2DH_CTRL6_VAL_BOOT_I2 0b00010000
#define LIS2DH_CTRL6_VAL_P2_ACT 0b00001000
#define LIS2DH_CTRL6_VAL_H_L_ACTIVE 0b00000000
#define LIS2DH_REG_REFERENCE 0x26
#define LIS2DH_REG_STATUS 0x27
#define LIS2DH_STATUS_VAL_ZYXOR 0b10000000
#define LIS2DH_STATUS_VAL_ZOR 0b01000000
#define LIS2DH_STATUS_VAL_YOR 0b00100000
#define LIS2DH_STATUS_VAL_XOR 0b00010000
#define LIS2DH_STATUS_VAL_ZYXDA 0b00001000
#define LIS2DH_STATUS_VAL_ZDA 0b00000100
#define LIS2DH_STATUS_VAL_YDA 0b00000010
#define LIS2DH_STATUS_VAL_XDA 0b00000001
#define LIS2DH_REG_OUT_X_L 0x28
#define LIS2DH_REG_OUT_X_H 0x29
#define LIS2DH_REG_OUT_Y_L 0x2A
#define LIS2DH_REG_OUT_Y_H 0x2B
#define LIS2DH_REG_OUT_Z_L 0x2C
#define LIS2DH_REG_OUT_Z_H 0x2D
#define LIS2DH_REG_FIFO_CTRL 0x2E
#define LIS2DH_REG_FIFO_SRC 0x2F
#define LIS2DH_REG_INT1_CFG 0x30
#define LIS2DH_REG_INT1_SRC 0x31
#define LIS2DH_REG_INT1_THS 0x32
#define LIS2DH_REG_INT1_DUR 0x33
#define LIS2DH_REG_INT2_CFG 0x34
#define LIS2DH_REG_INT2_SRC 0x35
#define LIS2DH_REG_INT2_THS 0x36
#define LIS2DH_REG_INT2_DUR 0x37
#define LIS2DH_REG_CLICK_CFG 0x38
#define LIS2DH_REG_CLICK_SRC 0x39
#define LIS2DH_REG_CLICK_THS 0x3A
#define LIS2DH_REG_TIME_LIMIT 0x3B
#define LIS2DH_REG_TIME_LATENCY 0x3C
#define LIS2DH_REG_TIME_WINDOW 0x3D
#endif // LIS2DH_H

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/*
* MIT License
*
* Copyright (c) 2021 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "lis2dw.h"
#include "watch.h"
bool lis2dw_begin(void) {
if (lis2dw_get_device_id() != LIS2DW_WHO_AM_I_VAL) {
return false;
}
watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL2, LIS2DW_CTRL2_VAL_BOOT);
watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL2, LIS2DW_CTRL2_VAL_SOFT_RESET);
// Start at lowest possible data rate and lowest possible power mode
watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, LIS2DW_CTRL1_VAL_ODR_LOWEST | LIS2DW_CTRL1_VAL_MODE_LOW_POWER | LIS2DW_CTRL1_VAL_LPMODE_1);
// Enable block data update (output registers not updated until MSB and LSB have been read) and address autoincrement
watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL2, LIS2DW_CTRL2_VAL_BDU | LIS2DW_CTRL2_VAL_IF_ADD_INC);
// Set range to ±2G
watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6, LIS2DW_CTRL6_VAL_RANGE_2G);
return true;
}
uint8_t lis2dw_get_device_id(void) {
return watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_WHO_AM_I);
}
bool lis2dw_have_new_data(void) {
uint8_t retval = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_STATUS);
return retval & LIS2DW_STATUS_VAL_DRDY;
}
lis2dw_reading lis2dw_get_raw_reading(void) {
uint8_t buffer[6];
uint8_t reg = LIS2DW_REG_OUT_X_L | 0x80; // set high bit for consecutive reads
lis2dw_reading retval;
watch_i2c_send(LIS2DW_ADDRESS, &reg, 1);
watch_i2c_receive(LIS2DW_ADDRESS, (uint8_t *)&buffer, 6);
retval.x = buffer[0];
retval.x |= ((uint16_t)buffer[1]) << 8;
retval.y = buffer[2];
retval.y |= ((uint16_t)buffer[3]) << 8;
retval.z = buffer[4];
retval.z |= ((uint16_t)buffer[5]) << 8;
return retval;
}
lis2dw_acceleration_measurement lis2dw_get_acceleration_measurement(lis2dw_reading *out_reading) {
lis2dw_reading reading = lis2dw_get_raw_reading();
uint8_t range = lis2dw_get_range();
if (out_reading != NULL) *out_reading = reading;
// this bit is cribbed from Adafruit's LIS3DH driver; from their notes, the magic number below
// converts from 16-bit lsb to 10-bit and divides by 1k to convert from milli-gs.
// final value is raw_lsb => 10-bit lsb -> milli-gs -> gs
uint8_t lsb_value = 1;
if (range == LIS2DW_RANGE_2_G) lsb_value = 4;
if (range == LIS2DW_RANGE_4_G) lsb_value = 8;
if (range == LIS2DW_RANGE_8_G) lsb_value = 16;
if (range == LIS2DW_RANGE_16_G) lsb_value = 48;
lis2dw_acceleration_measurement retval;
retval.x = lsb_value * ((float)reading.x / 64000.0);
retval.y = lsb_value * ((float)reading.y / 64000.0);
retval.z = lsb_value * ((float)reading.z / 64000.0);
return retval;
}
void lis2dw_set_range(lis2dw_range_t range) {
uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6) & ~(LIS2DW_RANGE_16_G << 4);
uint8_t bits = range << 4;
watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6, val | bits);
}
lis2dw_range_t lis2dw_get_range(void) {
uint8_t retval = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6) & (LIS2DW_RANGE_16_G << 4);
retval >>= 4;
return (lis2dw_range_t)retval;
}
void lis2dw_set_data_rate(lis2dw_data_rate_t dataRate) {
uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & ~(0b1111 << 4);
uint8_t bits = dataRate << 4;
watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, val | bits);
}
lis2dw_data_rate_t lis2dw_get_data_rate(void) {
return watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) >> 4;
}
void lis2dw_set_low_power_mode(lis2dw_low_power_mode_t mode) {
uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & ~(0b11);
uint8_t bits = mode & 0b11;
watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, val | bits);
}
lis2dw_low_power_mode_t lis2dw_get_low_power_mode(void) {
return watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & 0b11;
}
void lis2dw_set_low_noise_mode(bool on) {
uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & ~(LIS2DW_CTRL6_VAL_LOW_NOISE);
uint8_t bits = on ? LIS2DW_CTRL6_VAL_LOW_NOISE : 0;
watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, val | bits);
}
bool lis2dw_get_low_noise_mode(void) {
return (watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & LIS2DW_CTRL6_VAL_LOW_NOISE) != 0;
}

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/*
* MIT License
*
* Copyright (c) 2021 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef LIS2DW_H
#define LIS2DW_H
#include <stdbool.h>
#include <stdint.h>
typedef struct {
int16_t x;
int16_t y;
int16_t z;
} lis2dw_reading;
typedef struct {
float x;
float y;
float z;
} lis2dw_acceleration_measurement;
typedef enum {
LIS2DW_DATA_RATE_POWERDOWN = 0,
LIS2DW_DATA_RATE_LOWEST = 0b0001, // 12.5 Hz in high performance mode, 1.6 Hz in low power
LIS2DW_DATA_RATE_12_5_HZ = 0b0010,
LIS2DW_DATA_RATE_25_HZ = 0b0011,
LIS2DW_DATA_RATE_50_HZ = 0b0100,
LIS2DW_DATA_RATE_100_HZ = 0b0101,
LIS2DW_DATA_RATE_200_HZ = 0b0110,
LIS2DW_DATA_RATE_HP_400_HZ = 0b0111,
LIS2DW_DATA_RATE_HP_800_HZ = 0b1000,
LIS2DW_DATA_RATE_HP_1600_HZ = 0b1001,
} lis2dw_data_rate_t;
typedef enum {
LIS2DW_MODE_LOW_POWER = 0b00,
LIS2DW_MODE_HIGH_PERFORMANCE = 0b01,
LIS2DW_MODE_ON_DEMAND = 0b10,
} lis2dw_mode_t;
typedef enum {
LIS2DW_LP_MODE_1 = 0b00, // 12-bit
LIS2DW_LP_MODE_2 = 0b01, // 14-bit
LIS2DW_LP_MODE_3 = 0b10, // 14-bit
LIS2DW_LP_MODE_4 = 0b11, // 14-bit
} lis2dw_low_power_mode_t;
typedef enum {
LIS2DW_BANDWIDTH_FILTER_DIV2 = 0b00,
LIS2DW_BANDWIDTH_FILTER_DIV4 = 0b01,
LIS2DW_BANDWIDTH_FILTER_DIV10 = 0b10,
LIS2DW_BANDWIDTH_FILTER_DIV20 = 0b11,
} lis2dw_bandwidth_filtering_mode_t;
typedef enum {
LIS2DW_RANGE_16_G = 0b11, // +/- 16g
LIS2DW_RANGE_8_G = 0b10, // +/- 8g
LIS2DW_RANGE_4_G = 0b01, // +/- 4g
LIS2DW_RANGE_2_G = 0b00 // +/- 2g (default value)
} lis2dw_range_t;
// Assumes SA0 is high; if low, its 0x18
#define LIS2DW_ADDRESS (0x19)
#define LIS2DW_REG_OUT_TEMP_L 0x0D ///< Temperature data low bit
#define LIS2DW_REG_OUT_TEMP_H 0x0E ///< Temperature data high bit
#define LIS2DW_REG_WHO_AM_I 0x0F ///< Device identification, will read 0x44
#define LIS2DW_WHO_AM_I_VAL 0x44 ///< Expected value of the WHO_AM_I register
#define LIS2DW_REG_CTRL1 0x20 ///< CTRL_REG1 in the data sheet.
#define LIS2DW_CTRL1_VAL_ODR_POWERDOWN 0
#define LIS2DW_CTRL1_VAL_ODR_LOWEST (LIS2DW_DATA_RATE_LOWEST << 4)
#define LIS2DW_CTRL1_VAL_ODR_12_5HZ (LIS2DW_DATA_RATE_12_5_HZ << 4)
#define LIS2DW_CTRL1_VAL_ODR_25HZ (LIS2DW_DATA_RATE_25_HZ << 4)
#define LIS2DW_CTRL1_VAL_ODR_50HZ (LIS2DW_DATA_RATE_50_HZ << 4)
#define LIS2DW_CTRL1_VAL_ODR_100HZ (LIS2DW_DATA_RATE_100_HZ << 4)
#define LIS2DW_CTRL1_VAL_ODR_200HZ (LIS2DW_DATA_RATE_200_HZ << 4)
#define LIS2DW_CTRL1_VAL_ODR_HP_400_HZ (LIS2DW_DATA_RATE_HP_400_HZ << 4)
#define LIS2DW_CTRL1_VAL_ODR_HP_800_HZ (LIS2DW_DATA_RATE_HP_800_HZ << 4)
#define LIS2DW_CTRL1_VAL_ODR_HP_1600_HZ (LIS2DW_DATA_RATE_HP_1600_HZ << 4)
#define LIS2DW_CTRL1_VAL_MODE_LOW_POWER (LIS2DW_MODE_LOW_POWER << 2)
#define LIS2DW_CTRL1_VAL_MODE_HIGH_PERFORMANCE (LIS2DW_MODE_HIGH_PERFORMANCE << 2)
#define LIS2DW_CTRL1_VAL_MODE_ON_DEMAND (LIS2DW_MODE_ON_DEMAND << 2)
#define LIS2DW_CTRL1_VAL_LPMODE_1 (LIS2DW_LP_MODE_1 << 0)
#define LIS2DW_CTRL1_VAL_LPMODE_2 (LIS2DW_LP_MODE_2 << 0)
#define LIS2DW_CTRL1_VAL_LPMODE_3 (LIS2DW_LP_MODE_3 << 0)
#define LIS2DW_CTRL1_VAL_LPMODE_4 (LIS2DW_LP_MODE_4 << 0)
#define LIS2DW_REG_CTRL2 0x21
#define LIS2DW_CTRL2_VAL_BOOT 0b10000000
#define LIS2DW_CTRL2_VAL_SOFT_RESET 0b01000000
#define LIS2DW_CTRL2_VAL_CS_PU_DISC 0b00010000
#define LIS2DW_CTRL2_VAL_BDU 0b00001000
#define LIS2DW_CTRL2_VAL_IF_ADD_INC 0b00000100
#define LIS2DW_REG_CTRL3 0x22
#define LIS2DW_CTRL4_VAL_SELF_TEST_POS 0b10000000
#define LIS2DW_CTRL4_VAL_SELF_TEST_NEG 0b01000000
#define LIS2DW_CTRL3_VAL_PP_OD 0b00100000
#define LIS2DW_CTRL3_VAL_LIR 0b00010000
#define LIS2DW_CTRL3_VAL_H_L_ACTIVE 0b00001000
#define LIS2DW_CTRL3_VAL_SLP_MODE_SEL 0b00000010
#define LIS2DW_CTRL3_VAL_SLP_MODE_1 0b00000001
#define LIS2DW_REG_CTRL4 0x23
#define LIS2DW_CTRL4_INT1_6D 0b10000000
#define LIS2DW_CTRL4_INT1_SINGLE_TAP 0b01000000
#define LIS2DW_CTRL4_INT1_WU 0b00100000
#define LIS2DW_CTRL4_INT1_FF 0b00010000
#define LIS2DW_CTRL4_INT1_TAP 0b00001000
#define LIS2DW_CTRL4_INT1_DIFF5 0b00000100
#define LIS2DW_CTRL4_INT1_FTH 0b00000010
#define LIS2DW_CTRL4_INT1_DRDY 0b00000001
#define LIS2DW_REG_CTRL5 0x24
#define LIS2DW_CTRL5_INT2_SLEEP_STATE 0b10000000
#define LIS2DW_CTRL5_INT2_SLEEP_CHG 0b01000000
#define LIS2DW_CTRL5_INT2_BOOT 0b00100000
#define LIS2DW_CTRL5_INT2_DRDY_T 0b00010000
#define LIS2DW_CTRL5_INT2_OVR 0b00001000
#define LIS2DW_CTRL5_INT2_DIFF5 0b00000100
#define LIS2DW_CTRL5_INT2_FTH 0b00000010
#define LIS2DW_CTRL5_INT2_DRDY 0b00000001
#define LIS2DW_REG_CTRL6 0x25
#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV2 (LIS2DW_BANDWIDTH_FILTER_DIV2 << 6)
#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV4 (LIS2DW_BANDWIDTH_FILTER_DIV4 << 6)
#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV10 (LIS2DW_BANDWIDTH_FILTER_DIV10 << 6)
#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV20 (LIS2DW_BANDWIDTH_FILTER_DIV20 << 6)
#define LIS2DW_CTRL6_VAL_RANGE_2G (LIS2DW_RANGE_2_G << 4)
#define LIS2DW_CTRL6_VAL_RANGE_4G (LIS2DW_RANGE_4_G << 4)
#define LIS2DW_CTRL6_VAL_RANGE_8G (LIS2DW_RANGE_8_G << 4)
#define LIS2DW_CTRL6_VAL_RANGE_16G (LIS2DW_RANGE_16_G << 4)
#define LIS2DW_CTRL6_VAL_FDS 0b00001000
#define LIS2DW_CTRL6_VAL_LOW_NOISE 0b00000100
#define LIS2DW_REG_OUT_TEMP 0x26
#define LIS2DW_REG_STATUS 0x27
#define LIS2DW_STATUS_VAL_FIFO_THS 0b10000000
#define LIS2DW_STATUS_VAL_WU_IA 0b01000000
#define LIS2DW_STATUS_VAL_SLEEP_STATE 0b00100000
#define LIS2DW_STATUS_VAL_DOUBLE_TAP 0b00010000
#define LIS2DW_STATUS_VAL_SINGLE_TAP 0b00001000
#define LIS2DW_STATUS_VAL_6D_IA 0b00000100
#define LIS2DW_STATUS_VAL_FF_IA 0b00000010
#define LIS2DW_STATUS_VAL_DRDY 0b00000001
#define LIS2DW_REG_OUT_X_L 0x28
#define LIS2DW_REG_OUT_X_H 0x29
#define LIS2DW_REG_OUT_Y_L 0x2A
#define LIS2DW_REG_OUT_Y_H 0x2B
#define LIS2DW_REG_OUT_Z_L 0x2C
#define LIS2DW_REG_OUT_Z_H 0x2D
#define LIS2DW_REG_FIFO_CTRL 0x2E
#define LIS2DW_REG_FIFO_SRC 0x2F
#define LIS2DW_REG_TAP_THS_X 0x30
#define LIS2DW_REG_TAP_THS_Y 0x31
#define LIS2DW_REG_TAP_THS_Z 0x32
#define LIS2DW_REG_INT1_DUR 0x33
#define LIS2DW_REG_WAKE_UP_THS 0x34
#define LIS2DW_REG_WAKE_UP_DUR 0x35
#define LIS2DW_REG_FREE_FALL 0x36
#define LIS2DW_REG_STATUS_DUP 0x37
#define LIS2DW_REG_WAKE_UP_SRC 0x38
#define LIS2DW_WAKE_UP_SRC_VAL_FF_IA 0b00100000
#define LIS2DW_WAKE_UP_SRC_VAL_SLEEP_STATE_IA 0b00010000
#define LIS2DW_WAKE_UP_SRC_VAL_WU_IA 0b00001000
#define LIS2DW_WAKE_UP_SRC_VAL_X_WU 0b00000100
#define LIS2DW_WAKE_UP_SRC_VAL_Y_WU 0b00000010
#define LIS2DW_WAKE_UP_SRC_VAL_Z_WU 0b00000001
#define LIS2DW_REG_TAP_SRC 0x39
#define LIS2DW_TAP_SRC_VAL_TAP_IA 0b01000000
#define LIS2DW_TAP_SRC_VAL_SINGLE_TAP 0b00100000
#define LIS2DW_TAP_SRC_VAL_DOUBLE_TAP 0b00010000
#define LIS2DW_TAP_SRC_VAL_TAP_SIGN 0b00001000
#define LIS2DW_TAP_SRC_VAL_X_TAP 0b00000100
#define LIS2DW_TAP_SRC_VAL_Y_TAP 0b00000010
#define LIS2DW_TAP_SRC_VAL_Z_TAP 0b00000001
#define LIS2DW_REG_SIXD_SRC 0x3A
#define LIS2DW_WAKE_UP_SRC_VAL_6D_IA 0b01000000
#define LIS2DW_WAKE_UP_SRC_VAL_ZH 0b00100000
#define LIS2DW_WAKE_UP_SRC_VAL_ZL 0b00010000
#define LIS2DW_WAKE_UP_SRC_VAL_YH 0b00001000
#define LIS2DW_WAKE_UP_SRC_VAL_YL 0b00000100
#define LIS2DW_WAKE_UP_SRC_VAL_XH 0b00000010
#define LIS2DW_WAKE_UP_SRC_VAL_XL 0b00000001
#define LIS2DW_REG_ALL_INT_SRC 0x3B
#define LIS2DW_REG_ALL_INT_SRC_SLEEP_CHANGE_IA 0b00100000
#define LIS2DW_REG_ALL_INT_SRC_6D_IA 0b00010000
#define LIS2DW_REG_ALL_INT_SRC_DOUBLE_TAP 0b00001000
#define LIS2DW_REG_ALL_INT_SRC_SINGLE_TAP 0b00000100
#define LIS2DW_REG_ALL_INT_SRC_WU_IA 0b00000010
#define LIS2DW_REG_ALL_INT_SRC_FF_IA 0b00000001
#define LIS2DW_REG_X_OFS_USR 0x3C
#define LIS2DW_REG_Y_OFS_USR 0x3D
#define LIS2DW_REG_Z_OFS_USR 0x3E
#define LIS2DW_REG_CTRL7 0x3F
#define LIS2DW_CTRL7_VAL_DRDY_PULSED 0b10000000
#define LIS2DW_CTRL7_VAL_INT2_ON_INT1 0b01000000
#define LIS2DW_CTRL7_VAL_INTERRUPTS_ENABLE 0b00100000
#define LIS2DW_CTRL7_VAL_USR_OFF_ON_OUT 0b00010000
#define LIS2DW_CTRL7_VAL_USR_OFF_ON_WU 0b00001000
#define LIS2DW_CTRL7_VAL_USR_OFF_W 0b00000100
#define LIS2DW_CTRL7_VAL_HP_REF_MODE 0b00000010
#define LIS2DW_CTRL7_VAL_LPASS_ON6D 0b00000001
bool lis2dw_begin(void);
uint8_t lis2dw_get_device_id(void);
bool lis2dw_have_new_data(void);
lis2dw_reading lis2dw_get_raw_reading(void);
lis2dw_acceleration_measurement lis2dw_get_acceleration_measurement(lis2dw_reading *out_reading);
void lis2dw_set_range(lis2dw_range_t range);
lis2dw_range_t lis2dw_get_range(void);
void lis2dw_set_data_rate(lis2dw_data_rate_t dataRate);
lis2dw_data_rate_t lis2dw_get_data_rate(void);
void lis2dw_set_low_power_mode(lis2dw_low_power_mode_t mode);
lis2dw_low_power_mode_t lis2dw_get_low_power_mode(void);
void lis2dw_set_low_noise_mode(bool on);
bool lis2dw_get_low_noise_mode(void);
#endif // LIS2DW_H

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/// @file watch.h
#ifndef WATCH_H_
#define WATCH_H_
#include <stdint.h>
#include <stdbool.h>
#include "driver_init.h"
/** @mainpage Sensor Watch Documentation
* @brief This documentation covers most of the functions you will use to interact with the Sensor Watch
hardware. It is divided into the following sections:
- @ref app - This section covers the functions that you will implement in your app.c file when designing a
Sensor Watch app.
- @ref rtc - This section covers functions related to the SAM L22's real-time clock peripheral, including
date, time and alarm functions.
- @ref slcd - This section covers functions related to the Segment LCD display driver, which is responsible
for displaying strings of characters and indicators on the main watch display.
- @ref buttons - This section covers functions related to the three buttons: Light, Mode and Alarm.
- @ref led - This section covers functions related to the bi-color red/green LED mounted behind the LCD.
- @ref buzzer - This section covers functions related to the piezo buzzer.
- @ref adc - This section covers functions related to the SAM L22's analog-to-digital converter, as well as
configuring and reading values from the five analog-capable pins on the 9-pin connector.
- @ref gpio - This section covers functions related to general-purpose input and output signals.
- @ref i2c - This section covers functions related to the SAM L22's built-I2C driver, including configuring
the I2C bus, putting values directly on the bus and reading data from registers on I2C devices.
- @ref debug - This section covers functions related to the debug UART, available on pin D1 of the 9-pin connector.
- @ref deepsleep - This section covers functions related to preparing for and entering BACKUP mode, the
deepest sleep mode available on the SAM L22.
*/
#include "watch_app.h"
#include "watch_rtc.h"
#include "watch_slcd.h"
#include "watch_extint.h"
#include "watch_led.h"
#include "watch_buzzer.h"
#include "watch_adc.h"
#include "watch_gpio.h"
#include "watch_i2c.h"
#include "watch_uart.h"
#include "watch_deepsleep.h"
#include "watch_private.h"
/** @brief Returns true when the battery voltage dips below 2.5V.
* @details A CR2016 battery will have a nominal voltage between 2.9 and 3 volts for most of its lifespan. Once the battery
* discharges to about 60%, the voltage will drift slightly lower; this may manifest as a dimmer LED. By the time
* the battery voltage has fallen to 2.5 volts, it will have probably less than 10% of its capacity remaining, and
* you can expect the voltage to drop relatively quickly as the battery dies.
*/
bool watch_is_battery_low(void);
/** @brief Returns true if either the buzzer or the LED driver is enabled.
* @details Both the buzzer and the LED use the TCC peripheral to drive their behavior. This function returns true if that
* peripheral is enabled. You can use this function to determine whether you need to call the watch_disable_leds or
* or watch_enable_buzzer functions before using these peripherals.
*/
bool watch_is_buzzer_or_led_enabled(void);
#endif /* WATCH_H_ */

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_ADC_H_INCLUDED
#define _WATCH_ADC_H_INCLUDED
////< @file watch_adc.h
#include "watch.h"
// matches adc.h
#ifndef ADC_REFCTRL_REFSEL_INTREF_Val
#define ADC_REFCTRL_REFSEL_INTREF_Val 0x0
#endif
#ifndef ADC_REFCTRL_REFSEL_INTVCC0_Val
#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1
#endif
#ifndef ADC_REFCTRL_REFSEL_INTVCC1_Val
#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2
#endif
#ifndef ADC_REFCTRL_REFSEL_INTVCC2_Val
#define ADC_REFCTRL_REFSEL_INTVCC2_Val 0x5
#endif
/** @addtogroup adc Analog Input
* @brief This section covers functions related to the SAM L22's analog-to-digital converter,
* as well as configuring and reading values from the five analog-capable pins on the
* 9-pin connector.
*/
/// @{
/** @brief Enables the ADC peripheral. You must call this before attempting to read a value
* from an analog pin.
*/
void watch_enable_adc(void);
/** @brief Configures the selected pin for analog input.
* @param pin One of pins A0-A4.
*/
void watch_enable_analog_input(const uint8_t pin);
/** @brief Reads an analog value from one of the pins.
* @param pin One of pins A0-A4.
* @return a 16-bit unsigned integer from 0-65535 representing the sampled value, unless you
* have changed the number of samples. @see watch_set_num_analog_samples for details
* on how that function changes the values returned from this one.
**/
uint16_t watch_get_analog_pin_level(const uint8_t pin);
/** @brief Sets the number of samples to accumulate when measuring a pin level. Default is 16.
* @param samples A power of 2 <= 1024. Specifically: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512
or 1024. Any other value will be ignored.
* @details The SAM L22's ADC has a resolution of 12 bits. By default, the watch configures
* the ADC to take 16 samples of the analog input and accumulate them in the result
* register; this effectively gives us a 16-bit resolution, at the cost of taking 16
* ADC cycles to complete a measurement. If you are measuring a slowly changing signal
* like a thermistor output or an ambient light sensor this is probably fine, even
* desirable. If you are measuring something a bit more fast-paced, like an analog
* accelerometer, you may wish to exchange precision for speed. In this case you may
* call this function to configure the ADC to accumulate fewer samples. HOWEVER! Note
* that this may change the range of values returned from watch_get_analog_pin_level:
* - For watch_set_num_analog_samples(1), the returned value will be 12 bits (0-4095).
* - For watch_set_num_analog_samples(2), the returned value will be 13 bits (0-8191).
* - For watch_set_num_analog_samples(4), the returned value will be 14 bits (0-16383).
* - For watch_set_num_analog_samples(8), the returned value will be 15 bits (0-32767).
* For sampling values over 16, the returned value will still be 16 bits (0-65535); the
* ADC will automatically divide the measured value by whatever factor is necessary to fit
* the result in 16 bits.
* @see watch_get_analog_pin_level
**/
void watch_set_analog_num_samples(uint16_t samples);
/** @brief Sets the length of time spent sampling, which allows measurement of higher impedance inputs.
* Default is 1.
* @param cycles The number of ADC cycles to sample, between 1 and 64.
* @see this article by Thea Flowers: https://blog.thea.codes/getting-the-most-out-of-the-samd21-adc/
* which is where I learned all of this.
* @details To measure an analog value, the SAM L22 must charge a capacitor to the analog voltage
* presented at the input. This takes time. Importantly, the higher the input impedance,
* the more time this takes. As a basic example: if you are using a thermistor tied to
* VCC to measure temperature, the capacitor has to charge through the thermistor. The
* higher the resistor value, the higher the input impedance, and the more time we need
* to allow for the measurement. By default, the ADC is configured to run on a 500 kHz
* clock with a sample time of one cycle. This is appropriate for an input impedance up
* to about 28kΩ. Setting the sampling time to 4 cycles allows for an input impedance up
* to 123kΩ. Setting the sampling time to the maximum of 64 cycles theoretically allows
* for input impedance up to 2 MΩ. (I based these numbers on the calculator in the linked
* blog post; it also has a ton of great info on the SAM D21 ADC, which is similar to the
* SAM L22's).
**/
void watch_set_analog_sampling_length(uint8_t cycles);
typedef enum {
ADC_REFERENCE_INTREF = ADC_REFCTRL_REFSEL_INTREF_Val,
ADC_REFERENCE_VCC_DIV1POINT6 = ADC_REFCTRL_REFSEL_INTVCC0_Val,
ADC_REFERENCE_VCC_DIV2 = ADC_REFCTRL_REFSEL_INTVCC1_Val,
ADC_REFERENCE_VCC = ADC_REFCTRL_REFSEL_INTVCC2_Val,
} watch_adc_reference_voltage;
/** @brief Selects the reference voltage to use for analog readings. Default is ADC_REFERENCE_VCC.
* @param reference One of ADC_REFERENCE_VCC, ADC_REFERENCE_VCC_DIV1POINT6, ADC_REFERENCE_VCC_DIV2
* or ADC_REFERENCE_INTREF.
* @details In order to turn an analog voltage into a 16-bit integer, the ADC needs to compare the
* measured voltage to a reference point. For example, if you were powering the watch with
* VCC == 3.0V and you had two 10K resistors connected in series from 3V to GND, you could
* expect to get 3 volts when you measure the top of the voltage divider, 0 volts at the
* bottom, and 1.5 volts in the middle. If you read these values uising a reference voltage
* of ADC_REFERENCE_VCC, the top value would be about 65535, the bottom about 0, and the
* middle about 32768. However! If we used ADC_REFERENCE_VCC_DIV2 as our reference, we would
* expect to get 65535 both at the top and the middle, because the largest value the ADC can
* measure in this configutation is 1.5V (VCC / 2).
*
* By changing the reference voltage from ADC_REFERENCE_VCC to ADC_REFERENCE_VCC_DIV1POINT6
* or ADC_REFERENCE_VCC_DIV2, you can get more resolution when measuring small voltages (i.e.
* a phototransistor circuit in low light).
*
* There is also a special reference voltage called ADC_REFERENCE_INTREF. The SAM L22's
* Supply Controller provides a selectable voltage reference (by default, 1.024 V) that you
* can select as a reference voltage for ADC conversions. Unlike the three references we
* talked about in the last paragraph, this reference voltage does not depend on VCC, which
* makes it very useful for measuring the battery voltage (since you can't really compare
* VCC to itself). You can change the INTREF voltage to 2.048 or 4.096 V by poking at the
* supply controller's VREF register, but the watch library does not support this use case.
**/
void watch_set_analog_reference_voltage(watch_adc_reference_voltage reference);
/** @brief Returns the voltage of the VCC supply in millivolts (i.e. 3000 mV == 3.0 V). If running on
* a coin cell, this will be the battery voltage.
* @details Unlike other ADC functions, this function does not return a raw value from the ADC, but
* rather scales it to an actual number of millivolts. This is because the ADC doesn't let
* us measure VCC per se; it instead lets us measure VCC / 4, and we choose to measure it
* against the internal reference voltage of 1.024 V. In short, the ADC gives us a number
* that's complicated to deal with, so we just turn it into a useful number for you :)
* @note This function depends on INTREF being 1.024V. If you have changed it by poking at the supply
* controller's VREF.SEL bits, this function will return inaccurate values.
*/
uint16_t watch_get_vcc_voltage(void);
/** @brief Disables the analog circuitry on the selected pin.
* @param pin One of pins A0-A4.
*/
void watch_disable_analog_input(const uint8_t pin);
/** @brief Disables the ADC peripheral.
* @note You will need to call watch_enable_adc to re-enable the ADC peripheral. When you do, it will
* have the default settings of 16 samples and 1 measurement cycle; if you customized these
* parameters, you will need to set them up again.
**/
void watch_disable_adc(void);
/// @}
#endif

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_APP_H_INCLUDED
#define _WATCH_APP_H_INCLUDED
////< @file watch_app.h
/** @addtogroup app Application Framework
* @brief This section covers the functions that you will implement in your app.c file when designing a Sensor Watch app.
* @details You should be able to write a watch app by simply implementing these functions and declaring callbacks for
* various GPIO and peripheral interrupts. The main.c file takes care of calling these functions for you. The
* general flow:
*
* 1. Your app_init() function is called.
* - This method should only be used to set your initial application state.
* 2. If your app is waking from BACKUP, app_wake_from_backup() is called.
* - If you saved state in the RTC's backup registers, you can restore it here.
* 3. Your app_setup() method is called.
* - You may wish to enable some functionality and peripherals here.
* - You should definitely set up some interrupts here.
* 4. The main run loop begins: your app_loop() function is called.
* - Run code and update your UI here.
* - Return true if your app is prepared to enter STANDBY mode.
* 5. This step differs depending on the value returned by app_loop:
* - If you returned false, execution resumes at (4).
* - If you returned true, app_prepare_for_standby() is called; execution moves on to (6).
* 6. The microcontroller enters STANDBY mode.
* - No user code will run, and the watch will enter a low power mode.
* - The watch will remain in this state until an interrupt wakes it.
* 7. Once woken from STANDBY, your app_wake_from_standby() function is called.
* - After this, execution resumes at (4).
*/
/// @{
/** @brief A function you will implement to initialize your application state. The app_init function is called before
* anything else. Use it to set up any internal data structures or application state required by your app,
* but don't configure any peripherals just yet.
*/
void app_init(void);
/** @brief A function you will implement to wake from BACKUP mode, which wipes the system's RAM, and with it, your
* application's state. You may have chosen to store some important application state in the RTC's backup
* registers prior to entering this mode. You may restore that state here.
*/
void app_wake_from_backup(void);
/** @brief A function you will implement to set up your application. The app_setup function is like setup() in Arduino.
* It is called once when the program begins. You should set pin modes and enable any peripherals you want to
* set up (real-time clock, I2C, etc.) Depending on your application, you may or may not want to configure
* sensors on your sensor board here. For example, a low-power accelerometer that will run at all times should
* be configured here, whereas you may want to enable a more power-hungry sensor only when you need it.
* @note If your app enters the ultra-low power BACKUP sleep mode, this function will be called again when it wakes
* from that deep sleep state. In this state, the RTC will still be configured with the correct date and time.
*/
void app_setup(void);
/** @brief A function you will implement to serve as the app's main run loop. This method will be called repeatedly,
or if you enter STANDBY mode, as soon as the device wakes from sleep.
* @return You should return true if your app is prepared to enter STANDBY mode. If you return false, your app's
* app_loop method will be called again immediately. Note that in STANDBY mode, the watch will consume only
* about 95 microamperes of power, whereas if you return false and keep the app awake, it will consume about
* 355 microamperes. This is the difference between months of battery life and days. As much as possible,
* you should limit the amount of time your app spends awake.
* @note Only the RTC, the segment LCD controller and the external interrupt controller run in STANDBY mode. If you
* are using, e.g. the PWM function to set a custom LED color, you should return false here until you are
* finished with that operation. Note however that the peripherals will continue running after waking up,
* so e.g. the I2C controller, if configured, will sleep in STANDBY. But you can use it again as soon as your
* app wakes up.
*/
bool app_loop(void);
/** @brief A function you will implement to prepare to enter STANDBY mode. The app_prepare_for_standby function is
* called after your app_loop function returns true, and just before the watch enters STANDBY mode. In this
* mode most peripherals are shut down, and no code will run until the watch receives an interrupt (generally
* either the 1Hz tick or a press on one of the buttons).
* @note If you are PWM'ing the LED or playing a sound on the buzzer, the TC/TCC peripherals that drive those operations
* will not run in STANDBY. BUT! the output pins will retain the state they had when entering standby. This means
* you could end up entering standby with an LED on and draining power, or with a DC potential across the piezo
* buzzer that could damage it if left in this state. If your app_loop does not prevent sleep during these
* activities, you should make sure to disable these outputs in app_prepare_for_standby.
*/
void app_prepare_for_standby(void);
/** @brief A method you will implement to configure the app after waking from STANDBY mode.
*/
void app_wake_from_standby(void);
/// @}
#endif

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_BUZZER_H_INCLUDED
#define _WATCH_BUZZER_H_INCLUDED
////< @file watch_buzzer.h
#include "watch.h"
/** @addtogroup buzzer Buzzer
* @brief This section covers functions related to the piezo buzzer embedded in the F-91W's back plate.
*/
/// @{
/** @brief Enables the TCC peripheral, which drives the buzzer.
*/
void watch_enable_buzzer(void);
/** @brief Sets the period of the buzzer.
* @param period The period of a single cycle for the TCC peripheral. You can determine the period for
* a desired frequency with the following formula: period = 1000000 / freq
*/
void watch_set_buzzer_period(uint32_t period);
/** @brief Disables the TCC peripheral that drives the buzzer.
* @note If you are using PWM to set custom LED colors, this method will also disable the LED PWM driver,
* since the buzzer and LED both make use of the same peripheral to drive their PWM behavior.
*/
void watch_disable_buzzer(void);
/** @brief Turns the buzzer output on. It will emit a continuous sound at the given frequency.
* @note The TCC peripheral that drives the buzzer does not run in standby mode; if you wish for buzzer
* output to continue, you should prevent your app from going to sleep.
*/
void watch_set_buzzer_on(void);
/** @brief Turns the buzzer output off.
*/
void watch_set_buzzer_off(void);
/// @brief 87 notes for use with watch_buzzer_play_note
typedef enum BuzzerNote {
BUZZER_NOTE_A1, ///< 55.00 Hz
BUZZER_NOTE_A1SHARP_B1FLAT, ///< 58.27 Hz
BUZZER_NOTE_B1, ///< 61.74 Hz
BUZZER_NOTE_C2, ///< 65.41 Hz
BUZZER_NOTE_C2SHARP_D2FLAT, ///< 69.30 Hz
BUZZER_NOTE_D2, ///< 73.42 Hz
BUZZER_NOTE_D2SHARP_E2FLAT, ///< 77.78 Hz
BUZZER_NOTE_E2, ///< 82.41 Hz
BUZZER_NOTE_F2, ///< 87.31 Hz
BUZZER_NOTE_F2SHARP_G2FLAT, ///< 92.50 Hz
BUZZER_NOTE_G2, ///< 98.00 Hz
BUZZER_NOTE_G2SHARP_A2FLAT, ///< 103.83 Hz
BUZZER_NOTE_A2, ///< 110.00 Hz
BUZZER_NOTE_A2SHARP_B2FLAT, ///< 116.54 Hz
BUZZER_NOTE_B2, ///< 123.47 Hz
BUZZER_NOTE_C3, ///< 130.81 Hz
BUZZER_NOTE_C3SHARP_D3FLAT, ///< 138.59 Hz
BUZZER_NOTE_D3, ///< 146.83 Hz
BUZZER_NOTE_D3SHARP_E3FLAT, ///< 155.56 Hz
BUZZER_NOTE_E3, ///< 164.81 Hz
BUZZER_NOTE_F3, ///< 174.61 Hz
BUZZER_NOTE_F3SHARP_G3FLAT, ///< 185.00 Hz
BUZZER_NOTE_G3, ///< 196.00 Hz
BUZZER_NOTE_G3SHARP_A3FLAT, ///< 207.65 Hz
BUZZER_NOTE_A3, ///< 220.00 Hz
BUZZER_NOTE_A3SHARP_B3FLAT, ///< 233.08 Hz
BUZZER_NOTE_B3, ///< 246.94 Hz
BUZZER_NOTE_C4, ///< 261.63 Hz
BUZZER_NOTE_C4SHARP_D4FLAT, ///< 277.18 Hz
BUZZER_NOTE_D4, ///< 293.66 Hz
BUZZER_NOTE_D4SHARP_E4FLAT, ///< 311.13 Hz
BUZZER_NOTE_E4, ///< 329.63 Hz
BUZZER_NOTE_F4, ///< 349.23 Hz
BUZZER_NOTE_F4SHARP_G4FLAT, ///< 369.99 Hz
BUZZER_NOTE_G4, ///< 392.00 Hz
BUZZER_NOTE_G4SHARP_A4FLAT, ///< 415.30 Hz
BUZZER_NOTE_A4, ///< 440.00 Hz
BUZZER_NOTE_A4SHARP_B4FLAT, ///< 466.16 Hz
BUZZER_NOTE_B4, ///< 493.88 Hz
BUZZER_NOTE_C5, ///< 523.25 Hz
BUZZER_NOTE_C5SHARP_D5FLAT, ///< 554.37 Hz
BUZZER_NOTE_D5, ///< 587.33 Hz
BUZZER_NOTE_D5SHARP_E5FLAT, ///< 622.25 Hz
BUZZER_NOTE_E5, ///< 659.25 Hz
BUZZER_NOTE_F5, ///< 698.46 Hz
BUZZER_NOTE_F5SHARP_G5FLAT, ///< 739.99 Hz
BUZZER_NOTE_G5, ///< 783.99 Hz
BUZZER_NOTE_G5SHARP_A5FLAT, ///< 830.61 Hz
BUZZER_NOTE_A5, ///< 880.00 Hz
BUZZER_NOTE_A5SHARP_B5FLAT, ///< 932.33 Hz
BUZZER_NOTE_B5, ///< 987.77 Hz
BUZZER_NOTE_C6, ///< 1046.50 Hz
BUZZER_NOTE_C6SHARP_D6FLAT, ///< 1108.73 Hz
BUZZER_NOTE_D6, ///< 1174.66 Hz
BUZZER_NOTE_D6SHARP_E6FLAT, ///< 1244.51 Hz
BUZZER_NOTE_E6, ///< 1318.51 Hz
BUZZER_NOTE_F6, ///< 1396.91 Hz
BUZZER_NOTE_F6SHARP_G6FLAT, ///< 1479.98 Hz
BUZZER_NOTE_G6, ///< 1567.98 Hz
BUZZER_NOTE_G6SHARP_A6FLAT, ///< 1661.22 Hz
BUZZER_NOTE_A6, ///< 1760.00 Hz
BUZZER_NOTE_A6SHARP_B6FLAT, ///< 1864.66 Hz
BUZZER_NOTE_B6, ///< 1975.53 Hz
BUZZER_NOTE_C7, ///< 2093.00 Hz
BUZZER_NOTE_C7SHARP_D7FLAT, ///< 2217.46 Hz
BUZZER_NOTE_D7, ///< 2349.32 Hz
BUZZER_NOTE_D7SHARP_E7FLAT, ///< 2489.02 Hz
BUZZER_NOTE_E7, ///< 2637.02 Hz
BUZZER_NOTE_F7, ///< 2793.83 Hz
BUZZER_NOTE_F7SHARP_G7FLAT, ///< 2959.96 Hz
BUZZER_NOTE_G7, ///< 3135.96 Hz
BUZZER_NOTE_G7SHARP_A7FLAT, ///< 3322.44 Hz
BUZZER_NOTE_A7, ///< 3520.00 Hz
BUZZER_NOTE_A7SHARP_B7FLAT, ///< 3729.31 Hz
BUZZER_NOTE_B7, ///< 3951.07 Hz
BUZZER_NOTE_C8, ///< 4186.01 Hz
BUZZER_NOTE_C8SHARP_D8FLAT, ///< 4434.92 Hz
BUZZER_NOTE_D8, ///< 4698.63 Hz
BUZZER_NOTE_D8SHARP_E8FLAT, ///< 4978.03 Hz
BUZZER_NOTE_E8, ///< 5274.04 Hz
BUZZER_NOTE_F8, ///< 5587.65 Hz
BUZZER_NOTE_F8SHARP_G8FLAT, ///< 5919.91 Hz
BUZZER_NOTE_G8, ///< 6271.93 Hz
BUZZER_NOTE_G8SHARP_A8FLAT, ///< 6644.88 Hz
BUZZER_NOTE_A8, ///< 7040.00 Hz
BUZZER_NOTE_A8SHARP_B8FLAT, ///< 7458.62 Hz
BUZZER_NOTE_B8, ///< 7902.13 Hz
BUZZER_NOTE_REST ///< no sound
} BuzzerNote;
/** @brief Plays the given note for a set duration.
* @param note The note you wish to play, or BUZZER_NOTE_REST to disable output for the given duration.
* @param duration_ms The duration of the note.
* @note Note that this will block your UI for the duration of the note's play time, and it will
* after this call, the buzzer period will be set to the period of this note.
*/
void watch_buzzer_play_note(BuzzerNote note, uint16_t duration_ms);
/// @brief An array of periods for all the notes on a piano, corresponding to the names in BuzzerNote.
extern const uint16_t NotePeriods[108];
/// @}
#endif

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_DEEPSLEEP_H_INCLUDED
#define _WATCH_DEEPSLEEP_H_INCLUDED
////< @file watch_deepsleep.h
#include "watch.h"
// These are declared in watch_rtc.c.
extern ext_irq_cb_t btn_alarm_callback;
extern ext_irq_cb_t a2_callback;
extern ext_irq_cb_t a4_callback;
/** @addtogroup deepsleep Sleep Control
* @brief This section covers functions related to the various sleep modes available to the watch,
* including Sleep, Deep Sleep, and BACKUP mode.
* @details These terms changed meaning a bit over the course of development; if you are coming
* to this documentation after having worked with an earlier version of the library,
* these definitions should clarify the terminology. Terms in all caps are modes of the
* SAM L22; terms in Title Case are specific implementations in this library.
* - ACTIVE mode is the mode the SAM L22 is in when both the main clock and the CPU are
* running. It is the most power-hungry mode. If you ever call delay_ms to wait a beat,
* the watch will remain in ACTIVE mode while taking that delay. In addition, whenever
* your `app_loop` function returns false, the device will remain in ACTIVE mode and
* call your `app_loop` function again.
* - STANDBY mode turns off the main clock and halts the CPU. Since the PWM driver is
* run from the main clock, it also stops the buzzer and any dimming of the LEDs.
* In this mode, the watch can wake from any interrupt source. Whenever your `app_loop`
* function returns true, the watch enters STANDBY mode until the next tick or other
* interrupt. This mode uses much less power than ACTIVE mode.
* - Sleep Mode is a special case of STANDBY mode. In this mode, the watch turns off
* almost all peripherals (including the external interrupt controller), and disables
* all pins except for the external wake pins. In this mode the watch can only wake
* from the RTC alarm interrupt or an external wake pin (A2, A4 or the alarm button),
* but the display remains on and your app's state is retained. You can enter this
* mode by calling `watch_enter_sleep_mode`. It consumes an order of magnitude less
* power than STANDBY mode.
* - Deep Sleep Mode is identical to sleep mode, but it also turns off the LCD to save
* a bit more power. You can enter this mode by calling `watch_enter_deep_sleep_mode`.
* - BACKUP mode is the lowest possible power mode on the SAM L22. It turns off all pins
* and peripherals except for the RTC. It also turns off the RAM, obliterating your
* application's state. The only way to wake from this mode is by setting an external
* wake interrupt on pin A2 or pin A4, and when you do wake it will be much like a
* wake from reset. You can enter this mode by calling `watch_enter_backup_mode`.
*/
/// @{
/** @brief Registers a callback on one of the RTC's external wake pins, which can wake the device
* from Sleep, Deep Sleep and BACKUP modes (but see warning re: BACKUP mode).
* @param pin Either pin BTN_ALARM, A2, or A4. These are the three external wake pins. If the pin
* is BTN_ALARM, this function also enables an internal pull down on that pin.
* @param callback The callback to be called if this pin triggers outside of BACKUP mode. If this is
* NULL, no callback will be called even in normal modes, but the interrupt will
* still be enabled so that it can wake the device.
* @param level The level you wish to scan for: true for rising, false for falling. Note that you
* cannot scan for both rising and falling edges like you can with the external interrupt
* pins; with the external wake interrupt, you can only get one or the other.
* @note When in ACTIVE, STANDBY and Sleep / Deep sleep modes, this will function much like a standard
* external interrupt situation: these pins will wake the device, and your callback will be
* called. However, if the device enters BACKUP mode and one of these pins wakes the device, your
* callback WILL NOT be called, as the device is basically waking from reset at that point.
* @warning As of the current SAM L22 silicon revision (rev B), the BTN_ALARM pin cannot wake the
* device from BACKUP mode. You can still use this function to register a BTN_ALARM interrupt
* in normal or deep sleep mode, but to wake from BACKUP, you will need to use pin A2 or A4.
*/
void watch_register_extwake_callback(uint8_t pin, ext_irq_cb_t callback, bool level);
/** @brief Unregisters the RTC interrupt on one of the EXTWAKE pins. This will prevent a value change on
* one of these pins from waking the device.
* @param pin Either pin BTN_ALARM, A2, or A4. If the pin is BTN_ALARM, this function DOES NOT disable
* the internal pull down on that pin.
*/
void watch_disable_extwake_interrupt(uint8_t pin);
/** @brief Stores data in one of the RTC's backup registers, which retain their data in BACKUP mode.
* @param data An unsigned 32 bit integer with the data you wish to store.
* @param reg A register from 0-7.
*/
void watch_store_backup_data(uint32_t data, uint8_t reg);
/** @brief Gets 32 bits of data from the RTC's BACKUP register.
* @param reg A register from 0-7.
* @return An unsigned 32 bit integer with the from the backup register.
*/
uint32_t watch_get_backup_data(uint8_t reg);
/** @brief enters Sleep Mode by disabling all pins and peripherals except the RTC and the LCD.
* @details This sleep mode is not the lowest power mode available, but it has the benefit of allowing you
* to display a message to the user while asleep. You can also set an alarm interrupt to wake at a
* configfurable interval (every minute, hour or day) to update the display. You can wake from this
* mode by pressing the ALARM button, if you registered an extwake callback on the ALARM button.
* Also note that when your app wakes from this sleep mode, your app_setup method will be called
* again, since this function will have disabled things you set up there.
*
* Note that to wake from either the ALARM button, the A2 interrupt or the A4 interrupt, you
* must first configure this by calling watch_register_extwake_callback.
*
* You can estimate the power consumption of this mode to be on the order of 30 microwatts
* (about 10 µA at 3 V).
*/
void watch_enter_sleep_mode(void);
/** @brief enters Deep Sleep Mode by disabling all pins and peripherals except the RTC.
* @details Short of BACKUP mode, this is the lowest power mode you can enter while retaining your
* application state (and the ability to wake with the alarm button). Just note that the display
* will be completely off, so you should document to the user of your application that they will
* need to press the alarm button to wake the device, or use a sensor board with support for
* an external wake pin.
*
* All notes from watch_enter_sleep_mode apply here, except for power consumption. You can estimate
* the power consumption of this mode to be on the order of 12 microwatts (about 4µA at 3 V).
*/
void watch_enter_deep_sleep_mode(void);
/** @brief Enters the SAM L22's lowest-power mode, BACKUP.
* @details This function does some housekeeping before entering BACKUP mode. It first disables all pins
* and peripherals except for the RTC, and disables the tick interrupt (since that would wake
* us up from BACKUP mode). Once again, if you wish to wake from the A2 or the A4 interrupt,
* you must first configure this by calling watch_register_extwake_callback.
* @note If you have a callback set for an external wake interrupt, it will be called if triggered while
* in ACTIVE, STANDBY, Sleep and Deep Sleep modes, but it *will not be called* when waking from
* BACKUP mode. Waking from backup is effectively like waking from reset, except that your
* @ref app_wake_from_backup function will be called.
* @warning On current revisions of the SAM L22 silicon, the ALARM_BTN pin (PA02 RTC/IN2) cannot wake
* the device from deep sleep mode. There is an errata note (Reference: 15010) that says that
* due to a silicon bug, RTC/IN2 is not functional in BACKUP. As a result, you should not call
* this function unless you have a device on the nine-pin connector with an external interrupt
* on pin A2 or A4 (i.e. an accelerometer with an interrupt pin).
*/
void watch_enter_backup_mode(void);
__attribute__((deprecated("Use watch_enter_sleep_mode or watch_enter_deep_sleep_mode instead")))
void watch_enter_shallow_sleep(bool display_on);
__attribute__((deprecated("Use watch_enter_backup_mode instead")))
void watch_enter_deep_sleep(void);
/// @}
#endif

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_EXTINT_H_INCLUDED
#define _WATCH_EXTINT_H_INCLUDED
////< @file watch_extint.h
#include "watch.h"
#include "hal_ext_irq.h"
/** @addtogroup buttons Buttons & External Interrupts
* @brief This section covers functions related to the three buttons: Light, Mode and Alarm, as well as
* external interrupts from devices on the nine-pin connector.
* @details The buttons are the core input UI of the watch, and the way the user will interact with
* your application. They are active high, pulled down by the microcontroller, and triggered
* when one of the "pushers" brings a tab from the metal frame into contact with the edge
* of the board. Note that the buttons can only wake the watch from STANDBY mode, at least as
* of the current SAM L22 silicon revision. The external interrupt controller runs in STANDBY
* mode, but it does not run in BACKUP mode; to wake from BACKUP, buttons will not cut it.
*/
/// @{
///@brief An enum defining the types of interrupt trigger you wish to scan for.
typedef enum watch_interrupt_trigger {
INTERRUPT_TRIGGER_NONE = 0,
INTERRUPT_TRIGGER_RISING,
INTERRUPT_TRIGGER_FALLING,
INTERRUPT_TRIGGER_BOTH,
} watch_interrupt_trigger;
/// @brief Enables the external interrupt controller.
void watch_enable_external_interrupts(void);
/// @brief Disables the external interrupt controller.
void watch_disable_external_interrupts(void);
/** @brief Configures an external interrupt callback on one of the external interrupt pins.
* @details You can set one interrupt callback per pin, and you can monitor for a rising condition,
* a falling condition, or both. If you just want to detect a button press, register your
* interrupt with INTERRUPT_TRIGGER_RISING; if you want to detect an active-low interrupt
* signal from a device on the nine-pin connector, use INTERRUPT_TRIGGER_FALLING. If you
* want to detect both rising and falling conditions (i.e. button down and button up), use
* INTERRUPT_TRIGGER_BOTH and use watch_get_pin_level to check the pin level in your callback
* to determine which condition caused the interrupt.
* @param pin One of BTN_LIGHT, BTN_MODE, BTN_ALARM, A0, A1, A3 or A4. If the pin parameter matches one of
* the three button pins, this function will also enable an internal pull-down resistor. If
* the pin parameter is A0-A4, you are responsible for setting any required pull configuration
* using watch_enable_pull_up or watch_enable_pull_down.
* @param callback The function you wish to have called when the button is pressed.
* @param trigger The condition on which you wish to trigger: rising, falling or both.
* @note Pins A2 and A4 can also generate interrupts via the watch_register_extwake_callback function, which
* will allow them to trigger even when the watch is in deep sleep mode.
* @warning As of now, A2 is not usable via the watch_register_interrupt_callback function. To enable an
* external interrupt on pin A2, use the watch_register_extwake_callback function. This issue will be
* addressed in a future revision of the watch library.
*/
void watch_register_interrupt_callback(const uint8_t pin, ext_irq_cb_t callback, watch_interrupt_trigger trigger);
__attribute__((deprecated("Use watch_register_interrupt_callback or watch_register_extwake_callback instead")))
void watch_register_button_callback(const uint8_t pin, ext_irq_cb_t callback);
__attribute__((deprecated("Use watch_enable_external_interrupts instead")))
void watch_enable_buttons(void);
/// @}
#endif

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_GPIO_H_INCLUDED
#define _WATCH_GPIO_H_INCLUDED
////< @file watch_gpio.h
#include "watch.h"
/** @addtogroup gpio Digital Input and Output
* @brief This section covers functions related to general-purpose input and output signals.
*/
/// @{
/** @brief Configures the selected pin for digital input.
* @param pin The pin that you wish to act as an input.
*/
void watch_enable_digital_input(const uint8_t pin);
/** @brief Disables any digital input, along with any pull-up or pull-down configuration.
* @param pin The pin that you wish to disable.
*/
void watch_disable_digital_input(const uint8_t pin);
/** @brief Enables a pull-up resistor on the selected pin.
* @param pin The pin that you wish to configure.
*/
void watch_enable_pull_up(const uint8_t pin);
/** @brief Enables a pull-down resistor on the selected pin.
* @param pin The pin that you wish to configure.
*/
void watch_enable_pull_down(const uint8_t pin);
/** @brief Gets the level of the selected pin.
* @param pin The pin whose value you wish to read.
* @return true if the pin was logic high; otherwise, false.
*/
bool watch_get_pin_level(const uint8_t pin);
/** @brief Configures the selected pin for digital output.
* @param pin The pin that you wish to act as an output.
*/
void watch_enable_digital_output(const uint8_t pin);
/** @brief Disables digital output on the selected pin.
* @param pin The pin that you wish disable.
*/
void watch_disable_digital_output(const uint8_t pin);
/** @brief Sets the level of the selected pin.
* @param pin The pin whose value you wish to set.
* @param level The level you wish to set: true for high, false for low.
*/
void watch_set_pin_level(const uint8_t pin, const bool level);
/// @}
#endif

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_I2C_H_INCLUDED
#define _WATCH_I2C_H_INCLUDED
////< @file watch_i2c.h
#include "watch.h"
/** @addtogroup i2c I2C Controller Driver
* @brief This section covers functions related to the SAM L22's built-I2C driver, including
* configuring the I2C bus, putting values directly on the bus and reading data from
* registers on I2C devices.
*/
/// @{
/** @brief Enables the I2C peripheral. Call this before attempting to interface with I2C devices.
*/
void watch_enable_i2c(void);
/** @brief Disables the I2C peripheral.
*/
void watch_disable_i2c(void);
/** @brief Sends a series of values to a device on the I2C bus.
* @param addr The address of the device you wish to talk to.
* @param buf A series of unsigned bytes; the data you wish to transmit.
* @param length The number of bytes in buf that you wish to send.
*/
void watch_i2c_send(int16_t addr, uint8_t *buf, uint16_t length);
/** @brief Receives a series of values from a device on the I2C bus.
* @param addr The address of the device you wish to hear from.
* @param buf Storage for the incoming bytes; on return, it will contain the received data.
* @param length The number of bytes that you wish to receive.
*/
void watch_i2c_receive(int16_t addr, uint8_t *buf, uint16_t length);
/** @brief Writes a byte to a register in an I2C device.
* @param addr The address of the device you wish to address.
* @param reg The register on the device that you wish to set.
* @param data The value that you wish to set the register to.
*/
void watch_i2c_write8(int16_t addr, uint8_t reg, uint8_t data);
/** @brief Reads a byte from a register in an I2C device.
* @param addr The address of the device you wish to address.
* @param reg The register on the device that you wish to read.
* @return An unsigned byte representing the value of the register that was read.
*/
uint8_t watch_i2c_read8(int16_t addr, uint8_t reg);
/** @brief Reads an unsigned little-endian word from a register in an I2C device.
* @param addr The address of the device you wish to address.
* @param reg The register on the device that you wish to read.
* @return An unsigned word representing the value of the register that was read.
* @note This reads two bytes into the word in bus order. If the device returns
the LSB first and then the MSB, you can use this value as returned.
If the device returns the data in big-endian order or uses some other
kind of fancy bit packing, you may need to shuffle some bits around.
*/
uint16_t watch_i2c_read16(int16_t addr, uint8_t reg);
/** @brief Reads three bytes as an unsigned little-endian int from a register in an I2C device.
* @param addr The address of the device you wish to address.
* @param reg The register on the device that you wish to read.
* @return An unsigned word representing the value of the register that was read.
* @note This reads three bytes into the word in bus order. If the device returns
these bytes LSB first, you can use this value as returned. If there is a
sign bit, the device returns the data in big-endian order, or it uses some
other kind of fancy bit packing, you may need to shuffle some bits around.
*/
uint32_t watch_i2c_read24(int16_t addr, uint8_t reg);
/** @brief Reads an unsigned little-endian int from a register in an I2C device.
* @param addr The address of the device you wish to address.
* @param reg The register on the device that you wish to read.
* @return An unsigned word representing the value of the register that was read.
* @note This reads three bytes into the word in bus order. If the device returns
these bytes LSB first, you can use this value as returned. If the device
returns the data in big-endian order, or it uses some other kind of fancy
bit packing, you may need to shuffle some bits around.
*/
uint32_t watch_i2c_read32(int16_t addr, uint8_t reg);
/// @}
#endif

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_LED_H_INCLUDED
#define _WATCH_LED_H_INCLUDED
////< @file watch_led.h
#include "watch.h"
/** @addtogroup led LED Control
* @brief This section covers functions related to the bi-color red/green LED mounted behind the LCD.
* @details The SAM L22 is an exceedingly power efficient chip, whereas the LED's are relatively power-
* hungry. The green LED, at full power, consumes more power than the whole chip in active mode,
* and the red LED consumes about twelve times as much power! The LED's should thus be used only
* sparingly in order to preserve battery life.
* @note Some watches use a red/blue LED instead of a red/green LED. You will be able to determine this
* easily when you double tap the reset button: if the pulsing bootloader LED is red, you have a
* red/green edition; if it is blue, you have a red/blue edition. For red/blue watches, build your
* project with the command `make LED=BLUE`, and the watch library will automatically swap the pins
* so that watch_set_led_red sets the red LED, and watch_set_led_green sets the blue one.
*/
/// @{
/** @brief Enables the bi-color LED.
* @note The TCC peripheral that drives the LEDs does not run in STANDBY mode — but the outputs do! This
* means that if you set either red, green or both LEDs to full power, they will shine even when
* your app is asleep. If, however, you set a custom color using watch_set_led_color, the color will
* not display correctly in STANDBY mode. You will need to keep your app running while the LED is on.
*/
void watch_enable_leds(void);
/** @brief Disables the LEDs.
* @note This method will also disable the buzzer, since the buzzer and LED both make use of the same
* peripheral to drive their PWM behavior.
*/
void watch_disable_leds(void);
/** @brief Sets the LED to a custom color by modulating each output's duty cycle.
* @param red The red value from 0-255.
* @param green The green value from 0-255. If your watch has a red/blue LED, this will be the blue value.
* @note If you are displaying a custom color, you will need to prevent your app from going to sleep
* while the LED is on; otherwise, the color will not display correctly. You can do this by
* returning false in your app_loop method.
*/
void watch_set_led_color(uint8_t red, uint8_t green);
/** @brief Sets the red LED to full brightness, and turns the green LED off.
* @details Of the two LED's in the RG bi-color LED, the red LED is the less power-efficient one (~4.5 mA).
*/
void watch_set_led_red(void);
/** @brief Sets the green LED to full brightness, and turns the red LED off.
* @details Of the two LED's in the RG bi-color LED, the green LED is the more power-efficient one (~0.44 mA).
* @note If your watch has a red/blue LED, this method will set the LED to blue.
*/
void watch_set_led_green(void);
/** @brief Sets both red and green LEDs to full brightness.
* @details The total current draw between the two LED's in this mode will be ~5 mA, which is more than the
* watch draws in any other mode. Take care not to drain the battery.
* @note If your watch has a red/blue LED, this method will set the LED to pink.
*/
void watch_set_led_yellow(void);
/** @brief Turns both the red and the green LEDs off. */
void watch_set_led_off(void);
__attribute__((deprecated("Use watch_enable_leds instead")))
void watch_enable_led(bool unused);
__attribute__((deprecated("Use watch_disable_leds instead")))
void watch_disable_led(bool unused);
/// @}
#endif

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/*
* MIT License
*
* Copyright (c) 2021 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_PRIVATE_H_INCLUDED
#define _WATCH_PRIVATE_H_INCLUDED
#include "watch.h"
/// Called by main.c while setting up the app. You should not call this from your app.
void _watch_init(void);
/// Initializes the real-time clock peripheral.
void _watch_rtc_init(void);
/// Called by buzzer and LED setup functions. You should not call this from your app.
void _watch_enable_tcc(void);
/// Called by buzzer and LED teardown functions. You should not call this from your app.
void _watch_disable_tcc(void);
/// Called by main.c if plugged in to USB. You should not call this from your app.
void _watch_enable_usb(void);
// this function ends up getting called by printf to log stuff to the USB console.
int _write(int file, char *ptr, int len);
// this method could be overridden to read stuff from the USB console? but no need rn.
int _read(void);
#endif

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "watch_slcd.h"
#include "watch_private_display.h"
static const uint32_t IndicatorSegments[] = {
SLCD_SEGID(0, 17), // WATCH_INDICATOR_SIGNAL
SLCD_SEGID(0, 16), // WATCH_INDICATOR_BELL
SLCD_SEGID(2, 17), // WATCH_INDICATOR_PM
SLCD_SEGID(2, 16), // WATCH_INDICATOR_24H
SLCD_SEGID(1, 10), // WATCH_INDICATOR_LAP
};
void watch_display_character(uint8_t character, uint8_t position) {
// special cases for positions 4 and 6
if (position == 4 || position == 6) {
if (character == '7') character = '&'; // "lowercase" 7
else if (character == 'A') character = 'a'; // A needs to be lowercase
else if (character == 'o') character = 'O'; // O needs to be uppercase
else if (character == 'L') character = '!'; // L needs to be in top half
else if (character == 'M' || character == 'm' || character == 'N') character = 'n'; // M and uppercase N need to be lowercase n
else if (character == 'c') character = 'C'; // C needs to be uppercase
else if (character == 'J') character = 'j'; // same
else if (character == 'v' || character == 'V' || character == 'U' || character == 'W' || character == 'w') character = 'u'; // bottom segment duplicated, so show in top half
} else {
if (character == 'u') character = 'v'; // we can use the bottom segment; move to lower half
else if (character == 'j') character = 'J'; // same but just display a normal J
}
if (position > 1) {
if (character == 'T') character = 't'; // uppercase T only works in positions 0 and 1
}
if (position == 1) {
if (character == 'o') character = 'O'; // O needs to be uppercase
if (character == 'i') character = 'l'; // I needs to be uppercase (use an l, it looks the same)
if (character == 'n') character = 'N'; // N needs to be uppercase
if (character == 'r') character = 'R'; // R needs to be uppercase
if (character == 'd') character = 'D'; // D needs to be uppercase
if (character == 'v' || character == 'V' || character == 'u') character = 'U'; // side segments shared, make uppercase
if (character == 'b') character = 'B'; // B needs to be uppercase
if (character == 'c') character = 'C'; // C needs to be uppercase
} else {
if (character == 'R') character = 'r'; // R needs to be lowercase almost everywhere
}
if (position == 0) {
watch_clear_pixel(0, 15); // clear funky ninth segment
} else {
if (character == 'I') character = 'l'; // uppercase I only works in position 0
}
uint64_t segmap = Segment_Map[position];
uint64_t segdata = Character_Set[character - 0x20];
for (int i = 0; i < 8; i++) {
uint8_t com = (segmap & 0xFF) >> 6;
if (com > 2) {
// COM3 means no segment exists; skip it.
segmap = segmap >> 8;
segdata = segdata >> 1;
continue;
}
uint8_t seg = segmap & 0x3F;
watch_clear_pixel(com, seg);
if (segdata & 1) watch_set_pixel(com, seg);
segmap = segmap >> 8;
segdata = segdata >> 1;
}
if (character == 'T' && position == 1) watch_set_pixel(1, 12); // add descender
else if (position == 0 && (character == 'B' || character == 'D')) watch_set_pixel(0, 15); // add funky ninth segment
else if (position == 1 && (character == 'B' || character == 'D' || character == '@')) watch_set_pixel(0, 12); // add funky ninth segment
}
void watch_display_string(char *string, uint8_t position) {
size_t i = 0;
while(string[i] != 0) {
watch_display_character(string[i], position + i);
i++;
if (position + i >= Num_Chars) break;
}
// uncomment this line to see screen output on terminal, i.e.
// FR 29
// 11 50 23
// note that for partial displays (positon > 0) it will only show the characters that were updated.
// printf("________\n %c%c %c%c\n%c%c %c%c %c%c\n--------\n", (position > 0) ? ' ' : string[0], (position > 1) ? ' ' : string[1 - position], (position > 2) ? ' ' : string[2 - position], (position > 3) ? ' ' : string[3 - position], (position > 4) ? ' ' : string[4 - position], (position > 5) ? ' ' : string[5 - position], (position > 6) ? ' ' : string[6 - position], (position > 7) ? ' ' : string[7 - position], (position > 8) ? ' ' : string[8 - position], (position > 9) ? ' ' : string[9 - position]);
}
void watch_set_colon(void) {
watch_set_pixel(1, 16);
}
void watch_clear_colon(void) {
watch_clear_pixel(1, 16);
}
void watch_set_indicator(WatchIndicatorSegment indicator) {
uint32_t value = IndicatorSegments[indicator];
uint8_t com = SLCD_COMNUM(value);
uint8_t seg = SLCD_SEGNUM(value);
watch_set_pixel(com, seg);
}
void watch_clear_indicator(WatchIndicatorSegment indicator) {
uint32_t value = IndicatorSegments[indicator];
uint8_t com = SLCD_COMNUM(value);
uint8_t seg = SLCD_SEGNUM(value);
watch_clear_pixel(com, seg);
}
void watch_clear_all_indicators(void) {
watch_clear_pixel(2, 17);
watch_clear_pixel(2, 16);
watch_clear_pixel(0, 17);
watch_clear_pixel(0, 16);
watch_clear_pixel(1, 10);
}

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_PRIVATE_DISPLAY_H_INCLUDED
#define _WATCH_PRIVATE_DISPLAY_H_INCLUDED
#include "hpl_slcd_config.h"
#include "driver_init.h"
static const uint8_t Character_Set[] =
{
0b00000000, //
0b01100000, // ! (L in the top half for positions 4 and 6)
0b00100010, // "
0b01100011, // # (degree symbol, hash mark doesn't fit)
0b00000000, // $ (unused)
0b00000000, // % (unused)
0b01000100, // & ("lowercase 7" for positions 4 and 6)
0b00100000, // '
0b00111001, // (
0b00001111, // )
0b00000000, // * (unused)
0b11000000, // + (only works in position 0)
0b00000100, // ,
0b01000000, // -
0b01000000, // . (same as -, semantically most useful)
0b00010010, // /
0b00111111, // 0
0b00000110, // 1
0b01011011, // 2
0b01001111, // 3
0b01100110, // 4
0b01101101, // 5
0b01111101, // 6
0b00000111, // 7
0b01111111, // 8
0b01101111, // 9
0b00000000, // : (unused)
0b00000000, // ; (unused)
0b01011000, // <
0b01001000, // =
0b01001100, // >
0b01010011, // ?
0b11111111, // @ (all segments on)
0b01110111, // A
0b01111111, // B
0b00111001, // C
0b00111111, // D
0b01111001, // E
0b01110001, // F
0b00111101, // G
0b01110110, // H
0b10001001, // I (only works in position 0)
0b00001110, // J
0b01110101, // K
0b00111000, // L
0b10110111, // M (only works in position 0)
0b00110111, // N
0b00111111, // O
0b01110011, // P
0b01100111, // Q
0b11110111, // R (only works in position 1)
0b01101101, // S
0b10000001, // T (only works in position 0; set (1, 12) to make it work in position 1)
0b00111110, // U
0b00111110, // V
0b10111110, // W (only works in position 0)
0b01111110, // X
0b01101110, // Y
0b00011011, // Z
0b00111001, // [
0b00100100, // backslash
0b00001111, // ]
0b00100011, // ^
0b00001000, // _
0b00000010, // `
0b01011111, // a
0b01111100, // b
0b01011000, // c
0b01011110, // d
0b01111011, // e
0b01110001, // f
0b01101111, // g
0b01110100, // h
0b00010000, // i
0b01000010, // j (appears as superscript to work in more positions)
0b01110101, // k
0b00110000, // l
0b10110111, // m (only works in position 0)
0b01010100, // n
0b01011100, // o
0b01110011, // p
0b01100111, // q
0b01010000, // r
0b01101101, // s
0b01111000, // t
0b01100010, // u (appears in (u)pper half to work in more positions)
0b00011100, // v (looks like u but in the lower half)
0b10111110, // w (only works in position 0)
0b01111110, // x
0b01101110, // y
0b00011011, // z
0b00111001, // {
0b00110000, // |
0b00001111, // }
0b00000001, // ~
};
static const uint64_t Segment_Map[] = {
0x4e4f0e8e8f8d4d0d, // Position 0, mode
0xc8c4c4c8b4b4b0b, // Position 1, mode (Segments B and C shared, as are segments E and F)
0xc049c00a49890949, // Position 2, day of month (Segments A, D, G shared; missing segment F)
0xc048088886874707, // Position 3, day of month
0xc053921252139352, // Position 4, clock hours (Segments A and D shared)
0xc054511415559594, // Position 5, clock hours
0xc057965616179716, // Position 6, clock minutes (Segments A and D shared)
0xc041804000018a81, // Position 7, clock minutes
0xc043420203048382, // Position 8, clock seconds
0xc045440506468584, // Position 9, clock seconds
};
static const uint8_t Num_Chars = 10;
void watch_display_character(uint8_t character, uint8_t position);
#endif

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_RTC_H_INCLUDED
#define _WATCH_RTC_H_INCLUDED
////< @file watch_rtc.h
#include "watch.h"
#include "hpl_calendar.h"
/** @addtogroup rtc Real-Time Clock
* @brief This section covers functions related to the SAM L22's real-time clock peripheral, including
* date, time and alarm functions.
* @details The real-time clock is the only peripheral that main.c enables for you. It is the cornerstone
* of low power operation on the watch, and it is required for several key functions that we
* assume will be available, namely the wake from BACKUP mode and the callback on the ALARM button.
* It is also required for the operation of the 1 Hz tick interrupt, which you will most likely use
* to wake from STANDBY mode.
*/
/// @{
#define WATCH_RTC_REFERENCE_YEAR (2020)
typedef union {
struct {
uint32_t second : 6; // 0-59
uint32_t minute : 6; // 0-59
uint32_t hour : 5; // 0-23
uint32_t day : 5; // 1-31
uint32_t month : 4; // 1-12
uint32_t year : 6; // 0-63 (representing 2020-2083)
} unit;
uint32_t reg; // the bit-packed value as expected by the RTC peripheral's CLOCK register.
} watch_date_time;
typedef enum watch_rtc_alarm_match {
ALARM_MATCH_DISABLED = 0,
ALARM_MATCH_SS,
ALARM_MATCH_MMSS,
ALARM_MATCH_HHMMSS,
} watch_rtc_alarm_match;
/** @brief Called by main.c to check if the RTC is enabled.
* You may call this function, but outside of app_init, it should always return true.
*/
bool _watch_rtc_is_enabled(void);
/** @brief Sets the date and time.
* @param date_time The date and time you wish to set, with a year value from 0-63 representing 2020-2083.
* @note The SAM L22 stores the year as six bits representing a value from 0 to 63. It treats this as a year
* offset from a reference year, which must be a leap year. Since 2020 was a leap year, and it allows
* useful dates through 2083, it is assumed that watch apps will use 2020 as the reference year; thus
* 1 means 2021, 2 means 2022, etc. **You will be responsible for handling this offset in your code**,
* if the calendar year is needed for timestamp calculation logic or display purposes.
*/
void watch_rtc_set_date_time(watch_date_time date_time);
/** @brief Returns the date and time.
* @return A watch_date_time with the current date and time, with a year value from 0-63 representing 2020-2083.
* @see watch_rtc_set_date_time for notes about how the year is stored.
*/
watch_date_time watch_rtc_get_date_time(void);
/** @brief Registers an alarm callback that will be called when the RTC time matches the target time, as masked
* by the provided mask.
* @param callback The function you wish to have called when the alarm fires. If this value is NULL, the alarm
* interrupt will still be enabled, but no callback function will be called.
* @param alarm_time The time that you wish to match. The date is currently ignored.
* @param mask One of the values in watch_rtc_alarm_match indicating which values to check.
* @details The alarm interrupt is a versatile tool for scheduling events in the future, especially since it can
* wake the device from all sleep modes. The key to its versatility is the mask parameter.
* Suppose we set an alarm for midnight, 00:00:00.
* * if mask is ALARM_MATCH_SS, the alarm will fire every minute when the clock ticks to seconds == 0.
* * with ALARM_MATCH_MMSS, the alarm will once an hour, at the top of each hour.
* * with ALARM_MATCH_HHMMSS, the alarm will fire at midnight every day.
* In theory the SAM L22's alarm function can match on days, months and even years, but I have not had
* success with this yet; as such, I am omitting these options for now.
*/
void watch_rtc_register_alarm_callback(ext_irq_cb_t callback, watch_date_time alarm_time, watch_rtc_alarm_match mask);
/** @brief Disables the alarm callback.
*/
void watch_rtc_disable_alarm_callback(void);
/** @brief Registers a "tick" callback that will be called once per second.
* @param callback The function you wish to have called when the clock ticks. If you pass in NULL, the tick
* interrupt will still be enabled, but no callback function will be called.
* @note this is equivalent to calling watch_rtc_register_periodic_callback with a frequency of 1. It can be
* disabled with either watch_rtc_disable_tick_callback() or watch_rtc_disable_periodic_callback(1),
* and will also be disabled when watch_rtc_disable_all_periodic_callbacks is called.
*/
void watch_rtc_register_tick_callback(ext_irq_cb_t callback);
/** @brief Disables the tick callback for the given period.
*/
void watch_rtc_disable_tick_callback(void);
/** @brief Registers a callback that will be called at a configurable period.
* @param callback The function you wish to have called at the specified period. If you pass in NULL, the periodic
* interrupt will still be enabled, but no callback function will be called.
* @param frequency The frequency of the tick in Hz. **Must be a power of 2**, from 1 to 128 inclusive.
* @note A 1 Hz tick (@see watch_rtc_register_tick_callback) is suitable for most applications, in that it gives you a
* chance to update the display once a second — an ideal update rate for a watch! If however you are displaying
* a value (such as an accelerometer output) that updates more frequently than once per second, you may want to
* tick at 16 or 32 Hz to update the screen more quickly. Just remember that the more frequent the tick, the more
* power your app will consume. Ideally you should enable the fast tick only when the user requires it (i.e. in
* response to an input event), and move back to the slow tick after some time.
*
* Also note that the RTC peripheral does not have sub-second resolution, so even if you set a 2 or 4 Hz interval,
* the system will not have any way of telling you where you are within a given second; watch_rtc_get_date_time
* will return the exact same timestamp until the second ticks over.
*/
void watch_rtc_register_periodic_callback(ext_irq_cb_t callback, uint8_t frequency);
/** @brief Disables the tick callback for the given period.
* @param frequency The frequency of the tick you wish to disable, in Hz. **Must be a power of 2**, from 1 to 128.
*/
void watch_rtc_disable_periodic_callback(uint8_t frequency);
/** @brief Disables all periodic callbacks, including the once-per-second tick callback.
*/
void watch_rtc_disable_all_periodic_callbacks(void);
/** @brief Sets the system date and time.
* @param date_time A struct representing the date and time you wish to set.
*/
__attribute__((deprecated("Use watch_rtc_set_date_time function instead")))
void watch_set_date_time(struct calendar_date_time date_time);
/** @brief Returns the system date and time in the provided struct.
* @param date_time A pointer to a calendar_date_time struct. It will have with the correct date and time on return.
*/
__attribute__((deprecated("Use the watch_rtc_get_date_time function instead")))
void watch_get_date_time(struct calendar_date_time *date_time);
/** @brief Registers a "tick" callback that will be called once per second.
* @param callback The function you wish to have called when the clock ticks. If you pass in NULL, the tick
* interrupt will still be enabled, but no callback function will be called.
*/
__attribute__((deprecated("Use the watch_rtc_register_tick_callback function instead")))
void watch_register_tick_callback(ext_irq_cb_t callback);
/// @}
#endif

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_SLCD_H_INCLUDED
#define _WATCH_SLCD_H_INCLUDED
////< @file watch_slcd.h
#include "watch.h"
/** @addtogroup slcd Segment LCD Display
* @brief This section covers functions related to the Segment LCD display driver, which is responsible
* for displaying strings of characters and indicators on the main watch display.
* @details The segment LCD controller consumes about 3 microamperes of power with no segments on, and
* about 4 microamperes with all segments on. There is also a slight power impact associated
* with updating the screen (about 1 microampere to update at 1 Hz). For the absolute lowest
* power operation, update the display only when its contents have changed, and disable the
* SLCD peripheral when the screen is not in use.
* For a map of all common and segment pins, see <a href="segmap.html">segmap.html</a>. You can
* hover over any segment in that diagram to view the common and segment pins associated with
* each segment of the display.
*/
/// @{
/// An enum listing the icons and indicators available on the watch.
typedef enum WatchIndicatorSegment {
WATCH_INDICATOR_SIGNAL = 0, ///< The hourly signal indicator; also useful for indicating that sensors are on.
WATCH_INDICATOR_BELL, ///< The small bell indicating that an alarm is set.
WATCH_INDICATOR_PM, ///< The PM indicator, indicating that a time is in the afternoon.
WATCH_INDICATOR_24H, ///< The 24H indicator, indicating that the watch is in a 24-hour mode.
WATCH_INDICATOR_LAP ///< The LAP indicator; the F-91W uses this in its stopwatch UI.
} WatchIndicatorSegment;
/** @brief Enables the Segment LCD display.
* Call this before attempting to set pixels or display strings.
*/
void watch_enable_display(void);
/** @brief Sets a pixel. Use this to manually set a pixel with a given common and segment number.
* See <a href="segmap.html">segmap.html</a>.
* @param com the common pin, numbered from 0-2.
* @param seg the segment pin, numbered from 0-23.
*/
void watch_set_pixel(uint8_t com, uint8_t seg);
/** @brief Clears a pixel. Use this to manually clear a pixel with a given common and segment number.
* See <a href="segmap.html">segmap.html</a>.
* @param com the common pin, numbered from 0-2.
* @param seg the segment pin, numbered from 0-23.
*/
void watch_clear_pixel(uint8_t com, uint8_t seg);
/** @brief Clears all segments of the display, including incicators and the colon.
*/
void watch_clear_display(void);
/** @brief Displays a string at the given position, starting from the top left. There are ten digits.
A space in any position will clear that digit.
* @param string A null-terminated string.
* @param position The position where you wish to start displaying the string. The day of week digits
* are positions 0 and 1; the day of month digits are positions 2 and 3, and the main
* clock line occupies positions 4-9.
* @note This method does not clear the display; if for example you display a two-character string at
position 0, positions 2-9 will retain whatever state they were previously displaying.
*/
void watch_display_string(char *string, uint8_t position);
/** @brief Turns the colon segment on.
*/
void watch_set_colon(void);
/** @brief Turns the colon segment off.
*/
void watch_clear_colon(void);
/** @brief Sets an indicator on the LCD. Use this to turn on one of the indicator segments.
* @param indicator One of the indicator segments from the enum. @see WatchIndicatorSegment
*/
void watch_set_indicator(WatchIndicatorSegment indicator);
/** @brief Clears an indicator on the LCD. Use this to turn off one of the indicator segments.
* @param indicator One of the indicator segments from the enum. @see WatchIndicatorSegment
*/
void watch_clear_indicator(WatchIndicatorSegment indicator);
/** @brief Clears all indicator segments.
* @see WatchIndicatorSegment
*/
void watch_clear_all_indicators(void);
/** @brief Blinks a single character in position 7. Does not affect other positions.
* @details Six of the seven segments in position 7 (and only position 7) are capable of autonomous
* blinking. This blinking does not require any CPU resources, and will continue even in
* STANDBY and Sleep mode (but not Deep Sleep mode, since that mode turns off the LCD).
* @param character The character you wish to blink.
* @param duration The duration of the on/off cycle in milliseconds, from 50 to ~4250 ms.
* @note Segment B of position 7 cannot blink autonomously, so not all characters will work well.
* Supported characters for blinking:
* * Punctuation: underscore, apostrophe, comma, hyphen, equals sign, tilde (top segment only)
* * Numbers: 5, 6, ampersand (lowercase 7)
* * Letters: b, C, c, E, F, h, i, L, l, n, o, S, t
*/
void watch_start_character_blink(char character, uint32_t duration);
/** @brief Stops and clears all blinking segments.
* @details This will stop all blinking in position 7, and clear all segments in that digit.
*/
void watch_stop_blink(void);
/** @brief Begins a two-segment "tick-tock" animation in position 8.
* @details Six of the seven segments in position 8 (and only position 8) are capable of autonomous
* animation. This animation is very basic, and consists of moving a bit pattern forward
* or backward in a shift register whose positions map to fixed segments on the LCD. Given
* this constraint, an animation across all six segments does not make sense; so the watch
* library offers only a simple "tick/tock" in segments D and E. This animation does not
* require any CPU resources, and will continue even in STANDBY and Sleep mode (but not Deep
* Sleep mode, since that mode turns off the LCD).
* @param duration The duration of each frame in ms. 500 milliseconds produces a classic tick/tock.
*/
void watch_start_tick_animation(uint32_t duration);
/** @brief Checks if the tick animation is currently running.
* @return true if the animation is running; false otherwise.
*/
bool watch_tick_animation_is_running(void);
/** @brief Stops the tick/tock animation and clears all animating segments.
* @details This will stop the animation and clear all segments in position 8.
*/
void watch_stop_tick_animation(void);
/// @}
#endif

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/*
* MIT License
*
* Copyright (c) 2020 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_UART_H_INCLUDED
#define _WATCH_UART_H_INCLUDED
////< @file watch_uart.h
#include "watch.h"
/** @addtogroup debug Debug UART
* @brief This section covers functions related to the debug UART, available on
* pin D1 of the 9-pin connector.
* @warning These functions were used early on in development, before the TinyUSB
* CDC was implemented. You can now print debug messages to the USB console
* using printf, rendering this bit irrelevant. These methods will likely
* be refactored out in the future, in favor of a more full-featured UART
* on the nine-pin connector.
**/
/// @{
/** @brief Initializes the debug UART.
* @param baud The baud rate
*/
__attribute__((deprecated("Use printf to log debug messages over USB.")))
void watch_enable_debug_uart(uint32_t baud);
/** @brief Outputs a single character on the debug UART.
* @param c The character you wish to output.
*/
__attribute__((deprecated("Use printf to log debug messages over USB.")))
void watch_debug_putc(char c);
/** @brief Outputs a string on the debug UART.
* @param s A null-terminated string.
*/
__attribute__((deprecated("Use printf to log debug messages over USB.")))
void watch_debug_puts(char *s);
/// @}
#endif

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/*
* MIT License
*
* Copyright (c) 2021 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <math.h>
#include "watch_utility.h"
const char * watch_utility_get_weekday(watch_date_time date_time) {
static const char weekdays[7][3] = {"SA", "SU", "MO", "TU", "WE", "TH", "FR"};
date_time.unit.year += 20;
if (date_time.unit.month <= 2) {
date_time.unit.month += 12;
date_time.unit.year--;
}
return weekdays[(date_time.unit.day + 13 * (date_time.unit.month + 1) / 5 + date_time.unit.year + date_time.unit.year / 4 + 525) % 7];
}
uint32_t watch_utility_convert_to_unix_time(uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second, uint32_t utc_offset) {
uint16_t DAYS_SO_FAR[] = {
0, // Jan
31, // Feb
59, // March
90, // April
120, // May
151, // June
181, // July
212, // August
243, // September
273, // October
304, // November
334 // December
};
uint32_t year_adj = year + 4800;
uint32_t febs = year_adj - (month <= 2 ? 1 : 0); /* Februaries since base. */
uint32_t leap_days = 1 + (febs / 4) - (febs / 100) + (febs / 400);
uint32_t days = 365 * year_adj + leap_days + DAYS_SO_FAR[month - 1] + day - 1;
days -= 2472692; /* Adjust to Unix epoch. */
uint32_t timestamp = days * 86400;
timestamp += hour * 3600;
timestamp += minute * 60;
timestamp += second;
timestamp -= utc_offset;
return timestamp;
}
uint32_t watch_utility_date_time_to_unix_time(watch_date_time date_time, uint32_t utc_offset) {
return watch_utility_convert_to_unix_time(date_time.unit.year + WATCH_RTC_REFERENCE_YEAR, date_time.unit.month, date_time.unit.day, date_time.unit.hour, date_time.unit.minute, date_time.unit.second, utc_offset);
}
#define LEAPOCH (946684800LL + 86400*(31+29))
#define DAYS_PER_400Y (365*400 + 97)
#define DAYS_PER_100Y (365*100 + 24)
#define DAYS_PER_4Y (365*4 + 1)
watch_date_time watch_utility_date_time_from_unix_time(uint32_t timestamp, uint32_t utc_offset) {
watch_date_time retval;
retval.reg = 0;
int32_t days, secs;
int32_t remdays, remsecs, remyears;
int32_t qc_cycles, c_cycles, q_cycles;
int32_t years, months;
int32_t wday, yday, leap;
static const int8_t days_in_month[] = {31,30,31,30,31,31,30,31,30,31,31,29};
timestamp += utc_offset;
secs = timestamp - LEAPOCH;
days = secs / 86400;
remsecs = secs % 86400;
if (remsecs < 0) {
remsecs += 86400;
days--;
}
wday = (3+days)%7;
if (wday < 0) wday += 7;
qc_cycles = (int)(days / DAYS_PER_400Y);
remdays = days % DAYS_PER_400Y;
if (remdays < 0) {
remdays += DAYS_PER_400Y;
qc_cycles--;
}
c_cycles = remdays / DAYS_PER_100Y;
if (c_cycles == 4) c_cycles--;
remdays -= c_cycles * DAYS_PER_100Y;
q_cycles = remdays / DAYS_PER_4Y;
if (q_cycles == 25) q_cycles--;
remdays -= q_cycles * DAYS_PER_4Y;
remyears = remdays / 365;
if (remyears == 4) remyears--;
remdays -= remyears * 365;
leap = !remyears && (q_cycles || !c_cycles);
yday = remdays + 31 + 28 + leap;
if (yday >= 365+leap) yday -= 365+leap;
years = remyears + 4*q_cycles + 100*c_cycles + 400*qc_cycles;
for (months=0; days_in_month[months] <= remdays; months++)
remdays -= days_in_month[months];
years += 2000;
months += 2;
if (months >= 12) {
months -=12;
years++;
}
if (years < 2020 || years > 2083) return retval;
retval.unit.year = years - WATCH_RTC_REFERENCE_YEAR;
retval.unit.month = months + 1;
retval.unit.day = remdays + 1;
retval.unit.hour = remsecs / 3600;
retval.unit.minute = remsecs / 60 % 60;
retval.unit.second = remsecs % 60;
return retval;
}
watch_date_time watch_utility_date_time_convert_zone(watch_date_time date_time, uint32_t origin_utc_offset, uint32_t destination_utc_offset) {
uint32_t timestamp = watch_utility_date_time_to_unix_time(date_time, origin_utc_offset);
return watch_utility_date_time_from_unix_time(timestamp, destination_utc_offset);
}
float watch_utility_thermistor_temperature(uint16_t value, bool highside, float b_coefficient, float nominal_temperature, float nominal_resistance, float series_resistance) {
float reading = (float)value;
if (highside) {
reading = (1023.0 * series_resistance) / (reading / 64.0);
reading -= series_resistance;
} else {
reading = series_resistance / (65535.0 / value - 1.0);
}
reading = reading / nominal_resistance;
reading = log(reading);
reading /= b_coefficient;
reading += 1.0 / (nominal_temperature + 273.15);
reading = 1.0 / reading;
reading -= 273.15;
return reading;
}

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/*
* MIT License
*
* Copyright (c) 2021 Joey Castillo
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _WATCH_UTILITY_H_INCLUDED
#define _WATCH_UTILITY_H_INCLUDED
////< @file watch_utility.h
#include "watch.h"
/** @addtogroup utility Utility Functions
* @brief This section covers various useful functions that don't fit anywhere else.
**/
/// @{
/** @brief Returns a two-letter weekday for the given timestamp, suitable for display
* in positions 0-1 of the watch face
* @param date_time The watch_date_time whose weekday you want.
*/
const char * watch_utility_get_weekday(watch_date_time date_time);
/** @brief Returns the UNIX time (seconds since 1970) for a given date/time in UTC.
* @param date_time The watch_date_time that you wish to convert.
* @param year The year of the date you wish to convert.
* @param month The month of the date you wish to convert.
* @param day The day of the date you wish to convert.
* @param hour The hour of the date you wish to convert.
* @param minute The minute of the date you wish to convert.
* @param second The second of the date you wish to convert.
* @param utc_offset The number of seconds that date_time is offset from UTC, or 0 if the time is UTC.
* @return A UNIX timestamp for the given date/time and UTC offset.
* @note Implemented by Wesley Ellis (tahnok) and based on BSD-licensed code by Josh Haberman:
* https://blog.reverberate.org/2020/05/12/optimizing-date-algorithms.html
*/
uint32_t watch_utility_convert_to_unix_time(uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second, uint32_t utc_offset);
/** @brief Returns the UNIX time (seconds since 1970) for a given watch_date_time struct.
* @param date_time The watch_date_time that you wish to convert.
* @param utc_offset The number of seconds that date_time is offset from UTC, or 0 if the time is UTC.
* @return A UNIX timestamp for the given watch_date_time and UTC offset.
*/
uint32_t watch_utility_date_time_to_unix_time(watch_date_time date_time, uint32_t utc_offset);
/** @brief Returns the UNIX time (seconds since 1970) for a given watch_date_time struct.
* @param timestamp The UNIX timestamp that you wish to convert.
* @param utc_offset The number of seconds that you wish date_time to be offset from UTC.
* @return A watch_date_time for the given UNIX timestamp and UTC offset, or if outside the range that
* watch_date_time can represent, a watch_date_time with all fields set to 0.
* @note Adapted from MIT-licensed code from musl, Copyright © 2005-2014 Rich Felker, et al.:
* https://github.com/esmil/musl/blob/1cc81f5cb0df2b66a795ff0c26d7bbc4d16e13c6/src/time/__secs_to_tm.c
*/
watch_date_time watch_utility_date_time_from_unix_time(uint32_t timestamp, uint32_t utc_offset);
/** @brief Converts a time from a given time zone to another time zone.
* @param date_time The watch_date_time that you wish to convert
* @param origin_utc_offset The number of seconds from UTC in the origin time zone
* @param destination_utc_offset The number of seconds from UTC in the destination time zone
* @return A watch_date_time for the given UNIX timestamp and UTC offset, or if outside the range that
* watch_date_time can represent, a watch_date_time with all fields set to 0.
* @note Adapted from MIT-licensed code from musl, Copyright © 2005-2014 Rich Felker, et al.:
* https://github.com/esmil/musl/blob/1cc81f5cb0df2b66a795ff0c26d7bbc4d16e13c6/src/time/__secs_to_tm.c
*/
watch_date_time watch_utility_date_time_convert_zone(watch_date_time date_time, uint32_t origin_utc_offset, uint32_t destination_utc_offset);
/** @brief Returns a temperature in degrees Celsius for a given thermistor voltage divider circuit.
* @param value The raw analog reading from the thermistor pin (0-65535)
* @param highside True if the thermistor is connected to VCC and the series resistor is connected
* to GND; false if the thermistor is connected to GND and the series resistor is
* connected to VCC.
* @param b_coefficient From your thermistor's data sheet, the B25/85 coefficient. A typical value
* will be between 2000 and 5000.
* @param nominal_temperature From your thermistor's data sheet, the temperature (in Celsius) at
* which the thermistor's resistance is at its nominal value.
* @param nominal_resistance The thermistor's resistance at the nominal temperature.
* @param series_resistance The value of the other resistor in the voltage divider.
* @note Ported from Adafruit's MIT-licensed CircuitPython thermistor code, (c) 2017 Scott Shawcroft:
* https://github.com/adafruit/Adafruit_CircuitPython_Thermistor/blob/main/adafruit_thermistor.py
*/
float watch_utility_thermistor_temperature(uint16_t value, bool highside, float b_coefficient, float nominal_temperature, float nominal_resistance, float series_resistance);
#endif