diff --git a/Smol Watch Project/My Project/.atmelstart/AtmelStart.env_conf b/Smol Watch Project/My Project/.atmelstart/AtmelStart.env_conf
new file mode 100644
index 00000000..4b12c8d7
--- /dev/null
+++ b/Smol Watch Project/My Project/.atmelstart/AtmelStart.env_conf
@@ -0,0 +1,6 @@
+
+
+
+
+
+
diff --git a/Smol Watch Project/My Project/.atmelstart/AtmelStart.gpdsc b/Smol Watch Project/My Project/.atmelstart/AtmelStart.gpdsc
new file mode 100644
index 00000000..563240fe
--- /dev/null
+++ b/Smol Watch Project/My Project/.atmelstart/AtmelStart.gpdsc
@@ -0,0 +1,242 @@
+
+ Atmel
+ My Project
+ Project generated by Atmel Start
+ http://start.atmel.com/
+
+ Initial version
+
+
+ Configuration Files generated by Atmel Start
+
+
+
+ Atmel Start
+
+ http://start.atmel.com/
+
+
+
+
+
+
+
+
+ Dependency on CMSIS core and Device Startup components
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Atmel Start Framework
+ #define ATMEL_START
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Smol Watch Project/My Project/.atmelstart/atmel_start_config.atstart b/Smol Watch Project/My Project/.atmelstart/atmel_start_config.atstart
new file mode 100644
index 00000000..0e0d365d
--- /dev/null
+++ b/Smol Watch Project/My Project/.atmelstart/atmel_start_config.atstart
@@ -0,0 +1,1698 @@
+format_version: '2'
+name: My Project
+versions:
+ api: '1.0'
+ backend: 1.8.543
+ commit: 931b2422bde1a793dea853de68547f48bf245b0f
+ content: unknown
+ content_pack_name: unknown
+ format: '2'
+ frontend: 1.8.543
+ packs_version_avr8: 1.0.1457
+ packs_version_qtouch: unknown
+ packs_version_sam: 1.0.1726
+ version_backend: 1.8.543
+ version_frontend: ''
+board:
+ identifier: CustomBoard
+ device: SAML22J18A-AN
+details: null
+application: null
+middlewares:
+ SLEEP_MANAGER_0:
+ user_label: SLEEP_MANAGER_0
+ configuration: {}
+ definition: Atmel:Sleep_Manager:0.0.1::Sleep_manager
+ functionality: Sleep_Manager
+ api: Sleep-Manager:Sleep-Manager:API
+ dependencies: {}
+drivers:
+ ADC_0:
+ user_label: ADC_0
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::ADC::driver_config_definition::ADC::HAL:Driver:ADC.Sync
+ functionality: ADC
+ api: HAL:Driver:ADC_Sync
+ configuration:
+ adc_advanced_settings: false
+ adc_arch_adjres: 0
+ adc_arch_corren: false
+ adc_arch_dbgrun: false
+ adc_arch_event_settings: false
+ adc_arch_flushei: false
+ adc_arch_flushinv: false
+ adc_arch_gaincorr: 0
+ adc_arch_leftadj: false
+ adc_arch_offcomp: false
+ adc_arch_offsetcorr: 0
+ adc_arch_ondemand: false
+ adc_arch_refcomp: false
+ adc_arch_resrdyeo: false
+ adc_arch_runstdby: false
+ adc_arch_samplen: 0
+ adc_arch_samplenum: 1 sample
+ adc_arch_seqen: 0
+ adc_arch_startei: false
+ adc_arch_startinv: false
+ adc_arch_winlt: 0
+ adc_arch_winmode: No window mode
+ adc_arch_winmoneo: false
+ adc_arch_winut: 0
+ adc_differential_mode: false
+ adc_freerunning_mode: false
+ adc_pinmux_negative: ADC AIN0 pin
+ adc_pinmux_positive: ADC AIN0 pin
+ adc_prescaler: Peripheral clock divided by 2
+ adc_reference: Internal bandgap reference
+ adc_resolution: 12-bit
+ optional_signals:
+ - identifier: ADC_0:AIN/9
+ pad: PB01
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::ADC.AIN.9
+ name: ADC/AIN/9
+ label: AIN/9
+ - identifier: ADC_0:AIN/10
+ pad: PB02
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::ADC.AIN.10
+ name: ADC/AIN/10
+ label: AIN/10
+ - identifier: ADC_0:AIN/12
+ pad: PB04
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::ADC.AIN.12
+ name: ADC/AIN/12
+ label: AIN/12
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: ADC
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ adc_gclk_selection: Generic clock generator 0
+ DMAC:
+ user_label: DMAC
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
+ functionality: System
+ api: HAL:HPL:DMAC
+ configuration:
+ dmac_beatsize_0: 8-bit bus transfer
+ dmac_beatsize_1: 8-bit bus transfer
+ dmac_beatsize_10: 8-bit bus transfer
+ dmac_beatsize_11: 8-bit bus transfer
+ dmac_beatsize_12: 8-bit bus transfer
+ dmac_beatsize_13: 8-bit bus transfer
+ dmac_beatsize_14: 8-bit bus transfer
+ dmac_beatsize_15: 8-bit bus transfer
+ dmac_beatsize_2: 8-bit bus transfer
+ dmac_beatsize_3: 8-bit bus transfer
+ dmac_beatsize_4: 8-bit bus transfer
+ dmac_beatsize_5: 8-bit bus transfer
+ dmac_beatsize_6: 8-bit bus transfer
+ dmac_beatsize_7: 8-bit bus transfer
+ dmac_beatsize_8: 8-bit bus transfer
+ dmac_beatsize_9: 8-bit bus transfer
+ dmac_blockact_0: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_1: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_10: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_11: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_12: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_13: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_14: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_15: Channel will be disabled if it is the last block transfer
+ in the transaction
+ dmac_blockact_2: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_3: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_4: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_5: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_6: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_7: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_8: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_blockact_9: Channel will be disabled if it is the last block transfer in
+ the transaction
+ dmac_channel_0_settings: false
+ dmac_channel_10_settings: false
+ dmac_channel_11_settings: false
+ dmac_channel_12_settings: false
+ dmac_channel_13_settings: false
+ dmac_channel_14_settings: false
+ dmac_channel_15_settings: false
+ dmac_channel_1_settings: false
+ dmac_channel_2_settings: false
+ dmac_channel_3_settings: false
+ dmac_channel_4_settings: false
+ dmac_channel_5_settings: false
+ dmac_channel_6_settings: false
+ dmac_channel_7_settings: false
+ dmac_channel_8_settings: false
+ dmac_channel_9_settings: false
+ dmac_dbgrun: false
+ dmac_dqos: Background (no sensitive operation)
+ dmac_dstinc_0: false
+ dmac_dstinc_1: false
+ dmac_dstinc_10: false
+ dmac_dstinc_11: false
+ dmac_dstinc_12: false
+ dmac_dstinc_13: false
+ dmac_dstinc_14: false
+ dmac_dstinc_15: false
+ dmac_dstinc_2: false
+ dmac_dstinc_3: false
+ dmac_dstinc_4: false
+ dmac_dstinc_5: false
+ dmac_dstinc_6: false
+ dmac_dstinc_7: false
+ dmac_dstinc_8: false
+ dmac_dstinc_9: false
+ dmac_enable: false
+ dmac_enable_0: false
+ dmac_enable_1: false
+ dmac_enable_10: false
+ dmac_enable_11: false
+ dmac_enable_12: false
+ dmac_enable_13: false
+ dmac_enable_14: false
+ dmac_enable_15: false
+ dmac_enable_2: false
+ dmac_enable_3: false
+ dmac_enable_4: false
+ dmac_enable_5: false
+ dmac_enable_6: false
+ dmac_enable_7: false
+ dmac_enable_8: false
+ dmac_enable_9: false
+ dmac_evact_0: No action
+ dmac_evact_1: No action
+ dmac_evact_10: No action
+ dmac_evact_11: No action
+ dmac_evact_12: No action
+ dmac_evact_13: No action
+ dmac_evact_14: No action
+ dmac_evact_15: No action
+ dmac_evact_2: No action
+ dmac_evact_3: No action
+ dmac_evact_4: No action
+ dmac_evact_5: No action
+ dmac_evact_6: No action
+ dmac_evact_7: No action
+ dmac_evact_8: No action
+ dmac_evact_9: No action
+ dmac_evie_0: false
+ dmac_evie_1: false
+ dmac_evie_10: false
+ dmac_evie_11: false
+ dmac_evie_12: false
+ dmac_evie_13: false
+ dmac_evie_14: false
+ dmac_evie_15: false
+ dmac_evie_2: false
+ dmac_evie_3: false
+ dmac_evie_4: false
+ dmac_evie_5: false
+ dmac_evie_6: false
+ dmac_evie_7: false
+ dmac_evie_8: false
+ dmac_evie_9: false
+ dmac_evoe_0: false
+ dmac_evoe_1: false
+ dmac_evoe_10: false
+ dmac_evoe_11: false
+ dmac_evoe_12: false
+ dmac_evoe_13: false
+ dmac_evoe_14: false
+ dmac_evoe_15: false
+ dmac_evoe_2: false
+ dmac_evoe_3: false
+ dmac_evoe_4: false
+ dmac_evoe_5: false
+ dmac_evoe_6: false
+ dmac_evoe_7: false
+ dmac_evoe_8: false
+ dmac_evoe_9: false
+ dmac_evosel_0: Event generation disabled
+ dmac_evosel_1: Event generation disabled
+ dmac_evosel_10: Event generation disabled
+ dmac_evosel_11: Event generation disabled
+ dmac_evosel_12: Event generation disabled
+ dmac_evosel_13: Event generation disabled
+ dmac_evosel_14: Event generation disabled
+ dmac_evosel_15: Event generation disabled
+ dmac_evosel_2: Event generation disabled
+ dmac_evosel_3: Event generation disabled
+ dmac_evosel_4: Event generation disabled
+ dmac_evosel_5: Event generation disabled
+ dmac_evosel_6: Event generation disabled
+ dmac_evosel_7: Event generation disabled
+ dmac_evosel_8: Event generation disabled
+ dmac_evosel_9: Event generation disabled
+ dmac_fqos: Background (no sensitive operation)
+ dmac_lvl_0: Channel priority 0
+ dmac_lvl_1: Channel priority 0
+ dmac_lvl_10: Channel priority 0
+ dmac_lvl_11: Channel priority 0
+ dmac_lvl_12: Channel priority 0
+ dmac_lvl_13: Channel priority 0
+ dmac_lvl_14: Channel priority 0
+ dmac_lvl_15: Channel priority 0
+ dmac_lvl_2: Channel priority 0
+ dmac_lvl_3: Channel priority 0
+ dmac_lvl_4: Channel priority 0
+ dmac_lvl_5: Channel priority 0
+ dmac_lvl_6: Channel priority 0
+ dmac_lvl_7: Channel priority 0
+ dmac_lvl_8: Channel priority 0
+ dmac_lvl_9: Channel priority 0
+ dmac_lvlen0: false
+ dmac_lvlen1: false
+ dmac_lvlen2: false
+ dmac_lvlen3: false
+ dmac_lvlpri0: 0
+ dmac_lvlpri1: 0
+ dmac_lvlpri2: 0
+ dmac_lvlpri3: 0
+ dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
+ dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
+ dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
+ dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
+ dmac_runstdby_0: false
+ dmac_runstdby_1: false
+ dmac_runstdby_10: false
+ dmac_runstdby_11: false
+ dmac_runstdby_12: false
+ dmac_runstdby_13: false
+ dmac_runstdby_14: false
+ dmac_runstdby_15: false
+ dmac_runstdby_2: false
+ dmac_runstdby_3: false
+ dmac_runstdby_4: false
+ dmac_runstdby_5: false
+ dmac_runstdby_6: false
+ dmac_runstdby_7: false
+ dmac_runstdby_8: false
+ dmac_runstdby_9: false
+ dmac_srcinc_0: false
+ dmac_srcinc_1: false
+ dmac_srcinc_10: false
+ dmac_srcinc_11: false
+ dmac_srcinc_12: false
+ dmac_srcinc_13: false
+ dmac_srcinc_14: false
+ dmac_srcinc_15: false
+ dmac_srcinc_2: false
+ dmac_srcinc_3: false
+ dmac_srcinc_4: false
+ dmac_srcinc_5: false
+ dmac_srcinc_6: false
+ dmac_srcinc_7: false
+ dmac_srcinc_8: false
+ dmac_srcinc_9: false
+ dmac_stepsel_0: Step size settings apply to the destination address
+ dmac_stepsel_1: Step size settings apply to the destination address
+ dmac_stepsel_10: Step size settings apply to the destination address
+ dmac_stepsel_11: Step size settings apply to the destination address
+ dmac_stepsel_12: Step size settings apply to the destination address
+ dmac_stepsel_13: Step size settings apply to the destination address
+ dmac_stepsel_14: Step size settings apply to the destination address
+ dmac_stepsel_15: Step size settings apply to the destination address
+ dmac_stepsel_2: Step size settings apply to the destination address
+ dmac_stepsel_3: Step size settings apply to the destination address
+ dmac_stepsel_4: Step size settings apply to the destination address
+ dmac_stepsel_5: Step size settings apply to the destination address
+ dmac_stepsel_6: Step size settings apply to the destination address
+ dmac_stepsel_7: Step size settings apply to the destination address
+ dmac_stepsel_8: Step size settings apply to the destination address
+ dmac_stepsel_9: Step size settings apply to the destination address
+ dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+ dmac_trifsrc_0: Only software/event triggers
+ dmac_trifsrc_1: Only software/event triggers
+ dmac_trifsrc_10: Only software/event triggers
+ dmac_trifsrc_11: Only software/event triggers
+ dmac_trifsrc_12: Only software/event triggers
+ dmac_trifsrc_13: Only software/event triggers
+ dmac_trifsrc_14: Only software/event triggers
+ dmac_trifsrc_15: Only software/event triggers
+ dmac_trifsrc_2: Only software/event triggers
+ dmac_trifsrc_3: Only software/event triggers
+ dmac_trifsrc_4: Only software/event triggers
+ dmac_trifsrc_5: Only software/event triggers
+ dmac_trifsrc_6: Only software/event triggers
+ dmac_trifsrc_7: Only software/event triggers
+ dmac_trifsrc_8: Only software/event triggers
+ dmac_trifsrc_9: Only software/event triggers
+ dmac_trigact_0: One trigger required for each block transfer
+ dmac_trigact_1: One trigger required for each block transfer
+ dmac_trigact_10: One trigger required for each block transfer
+ dmac_trigact_11: One trigger required for each block transfer
+ dmac_trigact_12: One trigger required for each block transfer
+ dmac_trigact_13: One trigger required for each block transfer
+ dmac_trigact_14: One trigger required for each block transfer
+ dmac_trigact_15: One trigger required for each block transfer
+ dmac_trigact_2: One trigger required for each block transfer
+ dmac_trigact_3: One trigger required for each block transfer
+ dmac_trigact_4: One trigger required for each block transfer
+ dmac_trigact_5: One trigger required for each block transfer
+ dmac_trigact_6: One trigger required for each block transfer
+ dmac_trigact_7: One trigger required for each block transfer
+ dmac_trigact_8: One trigger required for each block transfer
+ dmac_trigact_9: One trigger required for each block transfer
+ dmac_wrbqos: Background (no sensitive operation)
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ EXTERNAL_IRQ_0:
+ user_label: EXTERNAL_IRQ_0
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ
+ functionality: External_IRQ
+ api: HAL:Driver:Ext_IRQ
+ configuration:
+ eic_arch_asynch0: false
+ eic_arch_asynch1: false
+ eic_arch_asynch10: false
+ eic_arch_asynch11: false
+ eic_arch_asynch12: false
+ eic_arch_asynch13: false
+ eic_arch_asynch14: false
+ eic_arch_asynch15: false
+ eic_arch_asynch2: false
+ eic_arch_asynch3: false
+ eic_arch_asynch4: false
+ eic_arch_asynch5: false
+ eic_arch_asynch6: false
+ eic_arch_asynch7: false
+ eic_arch_asynch8: false
+ eic_arch_asynch9: false
+ eic_arch_cksel: Clocked by GCLK
+ eic_arch_enable_irq_setting0: false
+ eic_arch_enable_irq_setting1: false
+ eic_arch_enable_irq_setting10: false
+ eic_arch_enable_irq_setting11: false
+ eic_arch_enable_irq_setting12: false
+ eic_arch_enable_irq_setting13: false
+ eic_arch_enable_irq_setting14: false
+ eic_arch_enable_irq_setting15: false
+ eic_arch_enable_irq_setting2: false
+ eic_arch_enable_irq_setting3: false
+ eic_arch_enable_irq_setting4: false
+ eic_arch_enable_irq_setting5: true
+ eic_arch_enable_irq_setting6: true
+ eic_arch_enable_irq_setting7: true
+ eic_arch_enable_irq_setting8: false
+ eic_arch_enable_irq_setting9: false
+ eic_arch_extinteo0: false
+ eic_arch_extinteo1: false
+ eic_arch_extinteo10: false
+ eic_arch_extinteo11: false
+ eic_arch_extinteo12: false
+ eic_arch_extinteo13: false
+ eic_arch_extinteo14: false
+ eic_arch_extinteo15: false
+ eic_arch_extinteo2: false
+ eic_arch_extinteo3: false
+ eic_arch_extinteo4: false
+ eic_arch_extinteo5: false
+ eic_arch_extinteo6: false
+ eic_arch_extinteo7: false
+ eic_arch_extinteo8: false
+ eic_arch_extinteo9: false
+ eic_arch_filten0: false
+ eic_arch_filten1: false
+ eic_arch_filten10: false
+ eic_arch_filten11: false
+ eic_arch_filten12: false
+ eic_arch_filten13: false
+ eic_arch_filten14: false
+ eic_arch_filten15: false
+ eic_arch_filten2: false
+ eic_arch_filten3: false
+ eic_arch_filten4: false
+ eic_arch_filten5: false
+ eic_arch_filten6: false
+ eic_arch_filten7: false
+ eic_arch_filten8: false
+ eic_arch_filten9: false
+ eic_arch_nmi_ctrl: false
+ eic_arch_nmiasynch: false
+ eic_arch_nmifilten: false
+ eic_arch_nmisense: No detection
+ eic_arch_sense0: No detection
+ eic_arch_sense1: No detection
+ eic_arch_sense10: No detection
+ eic_arch_sense11: No detection
+ eic_arch_sense12: No detection
+ eic_arch_sense13: No detection
+ eic_arch_sense14: No detection
+ eic_arch_sense15: No detection
+ eic_arch_sense2: No detection
+ eic_arch_sense3: No detection
+ eic_arch_sense4: No detection
+ eic_arch_sense5: Rising-edge detection
+ eic_arch_sense6: Rising-edge detection
+ eic_arch_sense7: Rising-edge detection
+ eic_arch_sense8: No detection
+ eic_arch_sense9: No detection
+ optional_signals:
+ - identifier: EXTERNAL_IRQ_0:EXTINT/5
+ pad: PB05
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::EIC.EXTINT.5
+ name: EIC/EXTINT/5
+ label: EXTINT/5
+ - identifier: EXTERNAL_IRQ_0:EXTINT/6
+ pad: PA22
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::EIC.EXTINT.6
+ name: EIC/EXTINT/6
+ label: EXTINT/6
+ - identifier: EXTERNAL_IRQ_0:EXTINT/7
+ pad: PA23
+ mode: Enabled
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::EIC.EXTINT.7
+ name: EIC/EXTINT/7
+ label: EXTINT/7
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: EIC
+ input: Generic clock generator 3
+ external: false
+ external_frequency: 0
+ configuration:
+ eic_gclk_selection: Generic clock generator 3
+ GCLK:
+ user_label: GCLK
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
+ functionality: System
+ api: HAL:HPL:GCLK
+ configuration:
+ $input: 400000
+ $input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
+ RESERVED_InputFreq: 400000
+ RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
+ _$freq_output_Generic clock generator 0: 4000000
+ _$freq_output_Generic clock generator 1: 400000
+ _$freq_output_Generic clock generator 2: 400000
+ _$freq_output_Generic clock generator 3: 32768
+ _$freq_output_Generic clock generator 4: 400000
+ enable_gclk_gen_0: true
+ enable_gclk_gen_0__externalclock: 1000000
+ enable_gclk_gen_1: false
+ enable_gclk_gen_1__externalclock: 1000000
+ enable_gclk_gen_2: false
+ enable_gclk_gen_2__externalclock: 1000000
+ enable_gclk_gen_3: true
+ enable_gclk_gen_3__externalclock: 1000000
+ enable_gclk_gen_4: false
+ enable_gclk_gen_4__externalclock: 1000000
+ gclk_arch_gen_0_enable: true
+ gclk_arch_gen_0_idc: false
+ gclk_arch_gen_0_oe: false
+ gclk_arch_gen_0_oov: false
+ gclk_arch_gen_0_runstdby: false
+ gclk_arch_gen_1_enable: false
+ gclk_arch_gen_1_idc: false
+ gclk_arch_gen_1_oe: false
+ gclk_arch_gen_1_oov: false
+ gclk_arch_gen_1_runstdby: false
+ gclk_arch_gen_2_enable: false
+ gclk_arch_gen_2_idc: false
+ gclk_arch_gen_2_oe: false
+ gclk_arch_gen_2_oov: false
+ gclk_arch_gen_2_runstdby: false
+ gclk_arch_gen_3_enable: true
+ gclk_arch_gen_3_idc: true
+ gclk_arch_gen_3_oe: false
+ gclk_arch_gen_3_oov: false
+ gclk_arch_gen_3_runstdby: true
+ gclk_arch_gen_4_enable: false
+ gclk_arch_gen_4_idc: false
+ gclk_arch_gen_4_oe: false
+ gclk_arch_gen_4_oov: false
+ gclk_arch_gen_4_runstdby: false
+ gclk_gen_0_div: 1
+ gclk_gen_0_div_sel: false
+ gclk_gen_0_oscillator: 16MHz Internal Oscillator (OSC16M)
+ gclk_gen_1_div: 1
+ gclk_gen_1_div_sel: false
+ gclk_gen_1_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+ gclk_gen_2_div: 1
+ gclk_gen_2_div_sel: false
+ gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+ gclk_gen_3_div: 1
+ gclk_gen_3_div_sel: false
+ gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
+ gclk_gen_4_div: 1
+ gclk_gen_4_div_sel: false
+ gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ MCLK:
+ user_label: MCLK
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
+ functionality: System
+ api: HAL:HPL:MCLK
+ configuration:
+ $input: 4000000
+ $input_id: Generic clock generator 0
+ RESERVED_InputFreq: 4000000
+ RESERVED_InputFreq_id: Generic clock generator 0
+ _$freq_output_CPU: 4000000
+ cpu_clock_source: Generic clock generator 0
+ cpu_div: '1'
+ enable_cpu_clock: true
+ mclk_arch_bupdiv: Divide by 8
+ nvm_wait_states: '0'
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: CPU
+ input: CPU
+ external: false
+ external_frequency: 0
+ configuration: {}
+ OSC32KCTRL:
+ user_label: OSC32KCTRL
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
+ functionality: System
+ api: HAL:HPL:OSC32KCTRL
+ configuration:
+ $input: 32768
+ $input_id: 32kHz External Crystal Oscillator (XOSC32K)
+ RESERVED_InputFreq: 32768
+ RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
+ _$freq_output_RTC source: 1024
+ enable_osculp32k: true
+ enable_rtc_source: false
+ enable_slcd_source: false
+ enable_xosc32k: true
+ osculp32k_calib: 0
+ osculp32k_calib_enable: false
+ rtc_1khz_selection: true
+ rtc_source_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
+ slcd_source_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
+ xosc32k_arch_cfden: false
+ xosc32k_arch_cfdeo: false
+ xosc32k_arch_en1k: true
+ xosc32k_arch_en32k: true
+ xosc32k_arch_enable: true
+ xosc32k_arch_ondemand: true
+ xosc32k_arch_runstdby: false
+ xosc32k_arch_startup: 62592us
+ xosc32k_arch_swben: false
+ xosc32k_arch_xtalen: true
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ OSCCTRL:
+ user_label: OSCCTRL
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
+ functionality: System
+ api: HAL:HPL:OSCCTRL
+ configuration:
+ $input: 32768
+ $input_id: 32kHz External Crystal Oscillator (XOSC32K)
+ RESERVED_InputFreq: 32768
+ RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
+ _$freq_output_16MHz Internal Oscillator (OSC16M): 4000000
+ _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
+ _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
+ _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 47998976
+ dfll48m_arch_enable: false
+ dfll48m_mode: Open Loop Mode
+ dfll48m_mul: 0
+ dfll48m_ref_clock: Generic clock generator 3
+ dfll_arch_bplckc: false
+ dfll_arch_calibration: false
+ dfll_arch_ccdis: false
+ dfll_arch_coarse: 31
+ dfll_arch_cstep: 1
+ dfll_arch_fine: 512
+ dfll_arch_fstep: 1
+ dfll_arch_llaw: false
+ dfll_arch_ondemand: true
+ dfll_arch_qldis: false
+ dfll_arch_runstdby: false
+ dfll_arch_stable: false
+ dfll_arch_usbcrm: false
+ dfll_arch_waitlock: false
+ enable_dfll48m: false
+ enable_fdpll96m: false
+ enable_osc16m: true
+ enable_xosc: false
+ fdpll96m_arch_enable: false
+ fdpll96m_arch_filter: Default filter mode
+ fdpll96m_arch_lbypass: false
+ fdpll96m_arch_lpen: false
+ fdpll96m_arch_ltime: No time-out, automatic lock
+ fdpll96m_arch_ondemand: true
+ fdpll96m_arch_refclk: XOSC32K clock reference
+ fdpll96m_arch_runstdby: false
+ fdpll96m_arch_wuf: false
+ fdpll96m_clock_div: 0
+ fdpll96m_ldr: 1463
+ fdpll96m_ldrfrac: 13
+ fdpll96m_presc: '1'
+ fdpll96m_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
+ osc16m_arch_12m_fcal: 0
+ osc16m_arch_12m_tcal: 0
+ osc16m_arch_16m_tcal: 0
+ osc16m_arch_4m_fcal: 0
+ osc16m_arch_4m_tcal: 0
+ osc16m_arch_8m_fcal: 0
+ osc16m_arch_8m_tcal: 0
+ osc16m_arch_calib_enable: false
+ osc16m_arch_enable: true
+ osc16m_arch_fcal: 0
+ osc16m_arch_ondemand: true
+ osc16m_arch_runstdby: false
+ osc16m_freq: '4'
+ xosc_arch_ampgc: false
+ xosc_arch_cfden: false
+ xosc_arch_cfdeo: false
+ xosc_arch_enable: false
+ xosc_arch_gain: 2MHz
+ xosc_arch_ondemand: true
+ xosc_arch_runstdby: false
+ xosc_arch_startup: 31us
+ xosc_arch_swben: false
+ xosc_arch_xtalen: false
+ xosc_frequency: 400000
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ PORT:
+ user_label: PORT
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::PORT::driver_config_definition::PORT::HAL:HPL:PORT
+ functionality: System
+ api: HAL:HPL:PORT
+ configuration:
+ enable_port_input_event_0: false
+ enable_port_input_event_1: false
+ enable_port_input_event_2: false
+ enable_port_input_event_3: false
+ porta_event_action_0: Output register of pin will be set to level of event
+ porta_event_action_1: Output register of pin will be set to level of event
+ porta_event_action_2: Output register of pin will be set to level of event
+ porta_event_action_3: Output register of pin will be set to level of event
+ porta_event_pin_identifier_0: 0
+ porta_event_pin_identifier_1: 0
+ porta_event_pin_identifier_2: 0
+ porta_event_pin_identifier_3: 0
+ porta_input_event_enable_0: false
+ porta_input_event_enable_1: false
+ porta_input_event_enable_2: false
+ porta_input_event_enable_3: false
+ portb_event_action_0: Output register of pin will be set to level of event
+ portb_event_action_1: Output register of pin will be set to level of event
+ portb_event_action_2: Output register of pin will be set to level of event
+ portb_event_action_3: Output register of pin will be set to level of event
+ portb_event_pin_identifier_0: 0
+ portb_event_pin_identifier_1: 0
+ portb_event_pin_identifier_2: 0
+ portb_event_pin_identifier_3: 0
+ portb_input_event_enable_0: false
+ portb_input_event_enable_1: false
+ portb_input_event_enable_2: false
+ portb_input_event_enable_3: false
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ CALENDAR_0:
+ user_label: CALENDAR_0
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::RTC::driver_config_definition::Calendar::HAL:Driver:Calendar
+ functionality: Calendar
+ api: HAL:Driver:Calendar
+ configuration:
+ rtc_arch_init_reset: true
+ rtc_arch_prescaler: Peripheral clock divided by 1024
+ rtc_cmpeo0: false
+ rtc_event_control: false
+ rtc_ovfeo: false
+ rtc_pereo0: false
+ rtc_pereo1: false
+ rtc_pereo2: false
+ rtc_pereo3: false
+ rtc_pereo4: false
+ rtc_pereo5: false
+ rtc_pereo6: false
+ rtc_pereo7: false
+ rtc_tamper_active_layer_frequency_prescalar: DIV2 CLK_RTC_OUT is CLK_RTC /2
+ rtc_tamper_debounce_frequency_prescalar: DIV2 CLK_RTC_DEB is CLK_RTC /2
+ rtc_tamper_input_action_0: OFF(Disabled)
+ rtc_tamper_input_action_1: OFF(Disabled)
+ rtc_tamper_input_action_2: OFF(Disabled)
+ rtc_tamper_input_action_3: OFF(Disabled)
+ rtc_tamper_input_action_4: OFF(Disabled)
+ tamper_debounce_enable_0: false
+ tamper_debounce_enable_1: false
+ tamper_debounce_enable_2: false
+ tamper_debounce_enable_3: false
+ tamper_debounce_enable_4: false
+ tamper_input_0_settings: false
+ tamper_input_1_settings: false
+ tamper_input_2_settings: false
+ tamper_input_3_settings: false
+ tamper_input_4_settings: false
+ tamper_level_0: false
+ tamper_level_1: false
+ tamper_level_2: false
+ tamper_level_3: false
+ tamper_level_4: false
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: RTC
+ input: RTC source
+ external: false
+ external_frequency: 0
+ configuration:
+ rtc_clk_selection: RTC source
+ I2C_0:
+ user_label: I2C_0
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::SERCOM1::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync
+ functionality: I2C
+ api: HAL:Driver:I2C_Master_Sync
+ configuration:
+ i2c_master_advanced: false
+ i2c_master_arch_dbgstop: Keep running
+ i2c_master_arch_inactout: Disabled
+ i2c_master_arch_lowtout: false
+ i2c_master_arch_mexttoen: false
+ i2c_master_arch_runstdby: false
+ i2c_master_arch_sdahold: 300-600ns hold time
+ i2c_master_arch_sexttoen: false
+ i2c_master_arch_trise: 215
+ i2c_master_baud_rate: 100000
+ optional_signals: []
+ variant:
+ specification: SDA=0, SCL=1
+ required_signals:
+ - name: SERCOM1/PAD/0
+ pad: PB30
+ label: SDA
+ - name: SERCOM1/PAD/1
+ pad: PB31
+ label: SCL
+ clocks:
+ domain_group:
+ nodes:
+ - name: Core
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ - name: Slow
+ input: Generic clock generator 3
+ external: false
+ external_frequency: 0
+ configuration:
+ core_gclk_selection: Generic clock generator 0
+ slow_gclk_selection: Generic clock generator 3
+ DELAY_0:
+ user_label: DELAY_0
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::SysTick::driver_config_definition::Delay::HAL:Driver:Delay
+ functionality: Delay
+ api: HAL:Driver:Delay
+ configuration:
+ systick_arch_tickint: false
+ optional_signals: []
+ variant: null
+ clocks:
+ domain_group: null
+ PWM_0:
+ user_label: PWM_0
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::TC3::driver_config_definition::PWM::HAL:Driver:PWM
+ functionality: PWM
+ api: HAL:Driver:PWM
+ configuration:
+ tc_arch_alock: The Lock Update bit is not affected on overflow/underflow and
+ re-trigger event
+ tc_arch_dbgrun: false
+ tc_arch_evact: Event action disabled
+ tc_arch_mceo0: false
+ tc_arch_mceo1: false
+ tc_arch_ondemand: false
+ tc_arch_ovfeo: false
+ tc_arch_presync: Reload or reset counter on next GCLK
+ tc_arch_runstdby: false
+ tc_arch_tcei: false
+ tc_arch_tcinv: false
+ tc_arch_wave_duty_val: 500
+ tc_arch_wave_per_val: 1000
+ tc_mode: Counter in 16-bit mode
+ tc_prescaler: No division
+ timer_event_control: false
+ optional_signals:
+ - identifier: PWM_0:WO/0
+ pad: PA20
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::TC3.WO.0
+ name: TC3/WO/0
+ label: WO/0
+ - identifier: PWM_0:WO/1
+ pad: PA21
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::TC3.WO.1
+ name: TC3/WO/1
+ label: WO/1
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: TC
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ tc_gclk_selection: Generic clock generator 0
+ PWM_1:
+ user_label: PWM_1
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::TCC0::driver_config_definition::PWM::HAL:Driver:PWM
+ functionality: PWM
+ api: HAL:Driver:PWM
+ configuration:
+ tcc_arch_alock: false
+ tcc_arch_cc0: 0
+ tcc_arch_cc1: 0
+ tcc_arch_cc2: 0
+ tcc_arch_cc3: 0
+ tcc_arch_cnteo: false
+ tcc_arch_cntsel: An interrupt/event is generated when a new counter cycle starts
+ tcc_arch_cpten0: false
+ tcc_arch_cpten1: false
+ tcc_arch_cpten2: false
+ tcc_arch_cpten3: false
+ tcc_arch_cpten4: false
+ tcc_arch_cpten5: false
+ tcc_arch_cpten6: false
+ tcc_arch_cpten7: false
+ tcc_arch_dbgrun: false
+ tcc_arch_evact0: Event action disabled
+ tcc_arch_evact1: Event action disabled
+ tcc_arch_lupd: true
+ tcc_arch_mcei0: false
+ tcc_arch_mcei1: false
+ tcc_arch_mcei2: false
+ tcc_arch_mcei3: false
+ tcc_arch_mceo0: false
+ tcc_arch_mceo1: false
+ tcc_arch_mceo2: false
+ tcc_arch_mceo3: false
+ tcc_arch_ovfeo: false
+ tcc_arch_prescsync: Reload or reset counter on next GCLK
+ tcc_arch_runstdby: false
+ tcc_arch_sel_ch: 1
+ tcc_arch_tcei0: false
+ tcc_arch_tcei1: false
+ tcc_arch_tceinv0: false
+ tcc_arch_tceinv1: false
+ tcc_arch_trgeo: false
+ tcc_arch_wave_duty_val: 500
+ tcc_arch_wave_per_val: 1000
+ tcc_arch_wavegen: Single-slope PWM
+ tcc_per: 10000
+ tcc_prescaler: Divide by 8
+ timer_event_control: false
+ optional_signals:
+ - identifier: PWM_1:WO/5
+ pad: PA27
+ mode: PWM output
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::TCC0.WO.5
+ name: TCC0/WO/5
+ label: WO/5
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: TCC
+ input: Generic clock generator 0
+ external: false
+ external_frequency: 0
+ configuration:
+ tcc_gclk_selection: Generic clock generator 0
+ SEGMENT_LCD_0:
+ user_label: SEGMENT_LCD_0
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::SLCD::driver_config_definition::SLCD::HAL:Driver:SLCD.Sync
+ functionality: Segment_LCD
+ api: HAL:Driver:SLCD_Sync
+ configuration:
+ slcd_arch_advanced_settings: false
+ slcd_arch_bbd: 2
+ slcd_arch_bben: true
+ slcd_arch_bias: THIRD
+ slcd_arch_char0_com_idx: 0
+ slcd_arch_char0_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char0_seg_idx: 1
+ slcd_arch_char0_seg_num: 1
+ slcd_arch_char0_setting: false
+ slcd_arch_char10_com_idx: 0
+ slcd_arch_char10_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char10_seg_idx: 1
+ slcd_arch_char10_seg_num: 1
+ slcd_arch_char10_setting: false
+ slcd_arch_char11_com_idx: 0
+ slcd_arch_char11_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char11_seg_idx: 1
+ slcd_arch_char11_seg_num: 1
+ slcd_arch_char11_setting: false
+ slcd_arch_char12_com_idx: 0
+ slcd_arch_char12_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char12_seg_idx: 1
+ slcd_arch_char12_seg_num: 1
+ slcd_arch_char12_setting: false
+ slcd_arch_char13_com_idx: 0
+ slcd_arch_char13_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char13_seg_idx: 1
+ slcd_arch_char13_seg_num: 1
+ slcd_arch_char13_setting: false
+ slcd_arch_char14_com_idx: 0
+ slcd_arch_char14_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char14_seg_idx: 1
+ slcd_arch_char14_seg_num: 1
+ slcd_arch_char14_setting: false
+ slcd_arch_char15_com_idx: 0
+ slcd_arch_char15_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char15_seg_idx: 1
+ slcd_arch_char15_seg_num: 1
+ slcd_arch_char15_setting: false
+ slcd_arch_char16_com_idx: 0
+ slcd_arch_char16_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char16_seg_idx: 1
+ slcd_arch_char16_seg_num: 1
+ slcd_arch_char16_setting: false
+ slcd_arch_char17_com_idx: 0
+ slcd_arch_char17_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char17_seg_idx: 1
+ slcd_arch_char17_seg_num: 1
+ slcd_arch_char17_setting: false
+ slcd_arch_char18_com_idx: 0
+ slcd_arch_char18_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char18_seg_idx: 1
+ slcd_arch_char18_seg_num: 1
+ slcd_arch_char18_setting: false
+ slcd_arch_char19_com_idx: 0
+ slcd_arch_char19_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char19_seg_idx: 1
+ slcd_arch_char19_seg_num: 1
+ slcd_arch_char19_setting: false
+ slcd_arch_char1_com_idx: 0
+ slcd_arch_char1_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char1_seg_idx: 1
+ slcd_arch_char1_seg_num: 1
+ slcd_arch_char1_setting: false
+ slcd_arch_char20_com_idx: 0
+ slcd_arch_char20_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char20_seg_idx: 1
+ slcd_arch_char20_seg_num: 1
+ slcd_arch_char20_setting: false
+ slcd_arch_char21_com_idx: 0
+ slcd_arch_char21_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char21_seg_idx: 1
+ slcd_arch_char21_seg_num: 1
+ slcd_arch_char21_setting: false
+ slcd_arch_char22_com_idx: 0
+ slcd_arch_char22_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char22_seg_idx: 1
+ slcd_arch_char22_seg_num: 1
+ slcd_arch_char22_setting: false
+ slcd_arch_char23_com_idx: 0
+ slcd_arch_char23_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char23_seg_idx: 1
+ slcd_arch_char23_seg_num: 1
+ slcd_arch_char23_setting: false
+ slcd_arch_char24_com_idx: 0
+ slcd_arch_char24_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char24_seg_idx: 1
+ slcd_arch_char24_seg_num: 1
+ slcd_arch_char24_setting: false
+ slcd_arch_char25_com_idx: 0
+ slcd_arch_char25_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char25_seg_idx: 1
+ slcd_arch_char25_seg_num: 1
+ slcd_arch_char25_setting: false
+ slcd_arch_char26_com_idx: 0
+ slcd_arch_char26_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char26_seg_idx: 1
+ slcd_arch_char26_seg_num: 1
+ slcd_arch_char26_setting: false
+ slcd_arch_char27_com_idx: 0
+ slcd_arch_char27_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char27_seg_idx: 1
+ slcd_arch_char27_seg_num: 1
+ slcd_arch_char27_setting: false
+ slcd_arch_char28_com_idx: 0
+ slcd_arch_char28_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char28_seg_idx: 1
+ slcd_arch_char28_seg_num: 1
+ slcd_arch_char28_setting: false
+ slcd_arch_char29_com_idx: 0
+ slcd_arch_char29_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char29_seg_idx: 1
+ slcd_arch_char29_seg_num: 1
+ slcd_arch_char29_setting: false
+ slcd_arch_char2_com_idx: 0
+ slcd_arch_char2_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char2_seg_idx: 1
+ slcd_arch_char2_seg_num: 1
+ slcd_arch_char2_setting: false
+ slcd_arch_char30_com_idx: 0
+ slcd_arch_char30_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char30_seg_idx: 1
+ slcd_arch_char30_seg_num: 1
+ slcd_arch_char30_setting: false
+ slcd_arch_char31_com_idx: 0
+ slcd_arch_char31_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char31_seg_idx: 1
+ slcd_arch_char31_seg_num: 1
+ slcd_arch_char31_setting: false
+ slcd_arch_char32_com_idx: 0
+ slcd_arch_char32_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char32_seg_idx: 1
+ slcd_arch_char32_seg_num: 1
+ slcd_arch_char32_setting: false
+ slcd_arch_char33_com_idx: 0
+ slcd_arch_char33_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char33_seg_idx: 1
+ slcd_arch_char33_seg_num: 1
+ slcd_arch_char33_setting: false
+ slcd_arch_char34_com_idx: 0
+ slcd_arch_char34_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char34_seg_idx: 1
+ slcd_arch_char34_seg_num: 1
+ slcd_arch_char34_setting: false
+ slcd_arch_char35_com_idx: 0
+ slcd_arch_char35_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char35_seg_idx: 1
+ slcd_arch_char35_seg_num: 1
+ slcd_arch_char35_setting: false
+ slcd_arch_char36_com_idx: 0
+ slcd_arch_char36_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char36_seg_idx: 1
+ slcd_arch_char36_seg_num: 1
+ slcd_arch_char36_setting: false
+ slcd_arch_char37_com_idx: 0
+ slcd_arch_char37_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char37_seg_idx: 1
+ slcd_arch_char37_seg_num: 1
+ slcd_arch_char37_setting: false
+ slcd_arch_char38_com_idx: 0
+ slcd_arch_char38_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char38_seg_idx: 1
+ slcd_arch_char38_seg_num: 1
+ slcd_arch_char38_setting: false
+ slcd_arch_char39_com_idx: 0
+ slcd_arch_char39_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char39_seg_idx: 1
+ slcd_arch_char39_seg_num: 1
+ slcd_arch_char39_setting: false
+ slcd_arch_char3_com_idx: 0
+ slcd_arch_char3_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char3_seg_idx: 1
+ slcd_arch_char3_seg_num: 1
+ slcd_arch_char3_setting: false
+ slcd_arch_char40_com_idx: 0
+ slcd_arch_char40_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char40_seg_idx: 1
+ slcd_arch_char40_seg_num: 1
+ slcd_arch_char40_setting: false
+ slcd_arch_char41_com_idx: 0
+ slcd_arch_char41_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char41_seg_idx: 1
+ slcd_arch_char41_seg_num: 1
+ slcd_arch_char41_setting: false
+ slcd_arch_char42_com_idx: 0
+ slcd_arch_char42_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char42_seg_idx: 1
+ slcd_arch_char42_seg_num: 1
+ slcd_arch_char42_setting: false
+ slcd_arch_char43_com_idx: 0
+ slcd_arch_char43_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char43_seg_idx: 1
+ slcd_arch_char43_seg_num: 1
+ slcd_arch_char43_setting: false
+ slcd_arch_char4_com_idx: 0
+ slcd_arch_char4_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char4_seg_idx: 1
+ slcd_arch_char4_seg_num: 1
+ slcd_arch_char4_setting: false
+ slcd_arch_char5_com_idx: 0
+ slcd_arch_char5_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char5_seg_idx: 1
+ slcd_arch_char5_seg_num: 1
+ slcd_arch_char5_setting: false
+ slcd_arch_char6_com_idx: 0
+ slcd_arch_char6_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char6_seg_idx: 1
+ slcd_arch_char6_seg_num: 1
+ slcd_arch_char6_setting: false
+ slcd_arch_char7_com_idx: 0
+ slcd_arch_char7_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char7_seg_idx: 1
+ slcd_arch_char7_seg_num: 1
+ slcd_arch_char7_setting: false
+ slcd_arch_char8_com_idx: 0
+ slcd_arch_char8_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char8_seg_idx: 1
+ slcd_arch_char8_seg_num: 1
+ slcd_arch_char8_setting: false
+ slcd_arch_char9_com_idx: 0
+ slcd_arch_char9_mapping_table: 7 Segments Mapping Table
+ slcd_arch_char9_seg_idx: 1
+ slcd_arch_char9_seg_num: 1
+ slcd_arch_char9_setting: false
+ slcd_arch_ckdiv: '4'
+ slcd_arch_cm_14segs_0_mapping_setting: '0'
+ slcd_arch_cm_14segs_10_mapping_setting: '10'
+ slcd_arch_cm_14segs_11_mapping_setting: '11'
+ slcd_arch_cm_14segs_12_mapping_setting: '12'
+ slcd_arch_cm_14segs_13_mapping_setting: '13'
+ slcd_arch_cm_14segs_1_mapping_setting: '1'
+ slcd_arch_cm_14segs_2_mapping_setting: '2'
+ slcd_arch_cm_14segs_3_mapping_setting: '3'
+ slcd_arch_cm_14segs_4_mapping_setting: '4'
+ slcd_arch_cm_14segs_5_mapping_setting: '5'
+ slcd_arch_cm_14segs_6_mapping_setting: '6'
+ slcd_arch_cm_14segs_7_mapping_setting: '7'
+ slcd_arch_cm_14segs_8_mapping_setting: '8'
+ slcd_arch_cm_14segs_9_mapping_setting: '9'
+ slcd_arch_cm_14segs_enable: false
+ slcd_arch_cm_7segs_0_mapping_setting: '0'
+ slcd_arch_cm_7segs_1_mapping_setting: '1'
+ slcd_arch_cm_7segs_2_mapping_setting: '2'
+ slcd_arch_cm_7segs_3_mapping_setting: '3'
+ slcd_arch_cm_7segs_4_mapping_setting: '4'
+ slcd_arch_cm_7segs_5_mapping_setting: '5'
+ slcd_arch_cm_7segs_6_mapping_setting: '6'
+ slcd_arch_cm_7segs_setting: false
+ slcd_arch_cm_setting: false
+ slcd_arch_com_num: '3'
+ slcd_arch_contrast_adjust: 3.4398V
+ slcd_arch_presc: '64'
+ slcd_arch_prf: 250Hz
+ slcd_arch_rrf: 2kHz
+ slcd_arch_runstdby: false
+ slcd_arch_seg_num: 24
+ slcd_arch_wmod: Low Power Waveform(frame-inversion)
+ slcd_arch_xvlcd: false
+ optional_signals:
+ - identifier: SEGMENT_LCD_0:LP/0
+ pad: PB06
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.0
+ name: SLCD/LP/0
+ label: LP/0
+ - identifier: SEGMENT_LCD_0:LP/1
+ pad: PB07
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.1
+ name: SLCD/LP/1
+ label: LP/1
+ - identifier: SEGMENT_LCD_0:LP/2
+ pad: PB08
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.2
+ name: SLCD/LP/2
+ label: LP/2
+ - identifier: SEGMENT_LCD_0:LP/3
+ pad: PB09
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.3
+ name: SLCD/LP/3
+ label: LP/3
+ - identifier: SEGMENT_LCD_0:LP/4
+ pad: PA04
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.4
+ name: SLCD/LP/4
+ label: LP/4
+ - identifier: SEGMENT_LCD_0:LP/5
+ pad: PA05
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.5
+ name: SLCD/LP/5
+ label: LP/5
+ - identifier: SEGMENT_LCD_0:LP/6
+ pad: PA06
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.6
+ name: SLCD/LP/6
+ label: LP/6
+ - identifier: SEGMENT_LCD_0:LP/7
+ pad: PA07
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.7
+ name: SLCD/LP/7
+ label: LP/7
+ - identifier: SEGMENT_LCD_0:LP/11
+ pad: PA08
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.11
+ name: SLCD/LP/11
+ label: LP/11
+ - identifier: SEGMENT_LCD_0:LP/12
+ pad: PA09
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.12
+ name: SLCD/LP/12
+ label: LP/12
+ - identifier: SEGMENT_LCD_0:LP/13
+ pad: PA10
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.13
+ name: SLCD/LP/13
+ label: LP/13
+ - identifier: SEGMENT_LCD_0:LP/14
+ pad: PA11
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.14
+ name: SLCD/LP/14
+ label: LP/14
+ - identifier: SEGMENT_LCD_0:LP/21
+ pad: PB11
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.21
+ name: SLCD/LP/21
+ label: LP/21
+ - identifier: SEGMENT_LCD_0:LP/22
+ pad: PB12
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.22
+ name: SLCD/LP/22
+ label: LP/22
+ - identifier: SEGMENT_LCD_0:LP/23
+ pad: PB13
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.23
+ name: SLCD/LP/23
+ label: LP/23
+ - identifier: SEGMENT_LCD_0:LP/24
+ pad: PB14
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.24
+ name: SLCD/LP/24
+ label: LP/24
+ - identifier: SEGMENT_LCD_0:LP/25
+ pad: PB15
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.25
+ name: SLCD/LP/25
+ label: LP/25
+ - identifier: SEGMENT_LCD_0:LP/28
+ pad: PA12
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.28
+ name: SLCD/LP/28
+ label: LP/28
+ - identifier: SEGMENT_LCD_0:LP/29
+ pad: PA13
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.29
+ name: SLCD/LP/29
+ label: LP/29
+ - identifier: SEGMENT_LCD_0:LP/30
+ pad: PA14
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.30
+ name: SLCD/LP/30
+ label: LP/30
+ - identifier: SEGMENT_LCD_0:LP/31
+ pad: PA15
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.31
+ name: SLCD/LP/31
+ label: LP/31
+ - identifier: SEGMENT_LCD_0:LP/32
+ pad: PA16
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.32
+ name: SLCD/LP/32
+ label: LP/32
+ - identifier: SEGMENT_LCD_0:LP/33
+ pad: PA17
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.33
+ name: SLCD/LP/33
+ label: LP/33
+ - identifier: SEGMENT_LCD_0:LP/34
+ pad: PA18
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.34
+ name: SLCD/LP/34
+ label: LP/34
+ - identifier: SEGMENT_LCD_0:LP/35
+ pad: PA19
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.35
+ name: SLCD/LP/35
+ label: LP/35
+ - identifier: SEGMENT_LCD_0:LP/42
+ pad: PB16
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.42
+ name: SLCD/LP/42
+ label: LP/42
+ - identifier: SEGMENT_LCD_0:LP/43
+ pad: PB17
+ mode: LCD pin
+ configuration: null
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.43
+ name: SLCD/LP/43
+ label: LP/43
+ variant: null
+ clocks:
+ domain_group:
+ nodes:
+ - name: SLCD
+ input: SLCD source
+ external: false
+ external_frequency: 0
+ configuration:
+ slcd_clk_selection: SLCD source
+pads:
+ VBUS_DET:
+ name: PA02
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA02
+ mode: Digital input
+ user_label: VBUS_DET
+ configuration:
+ pad_pull_config: Pull-down
+ A0:
+ name: PB04
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB04
+ mode: Analog
+ user_label: A0
+ configuration: null
+ BTN_ALARM:
+ name: PB05
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB05
+ mode: Digital input
+ user_label: BTN_ALARM
+ configuration:
+ pad_pull_config: Pull-down
+ COM0:
+ name: PB06
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB06
+ mode: Peripheral IO
+ user_label: COM0
+ configuration: null
+ COM1:
+ name: PB07
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB07
+ mode: Peripheral IO
+ user_label: COM1
+ configuration: null
+ COM2:
+ name: PB08
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB08
+ mode: Peripheral IO
+ user_label: COM2
+ configuration: null
+ SEG0:
+ name: PB09
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB09
+ mode: Peripheral IO
+ user_label: SEG0
+ configuration: null
+ SEG1:
+ name: PA04
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA04
+ mode: Peripheral IO
+ user_label: SEG1
+ configuration: null
+ SEG2:
+ name: PA05
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA05
+ mode: Peripheral IO
+ user_label: SEG2
+ configuration: null
+ SEG3:
+ name: PA06
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA06
+ mode: Peripheral IO
+ user_label: SEG3
+ configuration: null
+ SEG4:
+ name: PA07
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA07
+ mode: Peripheral IO
+ user_label: SEG4
+ configuration: null
+ SEG5:
+ name: PA08
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA08
+ mode: Peripheral IO
+ user_label: SEG5
+ configuration: null
+ SEG6:
+ name: PA09
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA09
+ mode: Peripheral IO
+ user_label: SEG6
+ configuration: null
+ SEG7:
+ name: PA10
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA10
+ mode: Peripheral IO
+ user_label: SEG7
+ configuration: null
+ SEG8:
+ name: PA11
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA11
+ mode: Peripheral IO
+ user_label: SEG8
+ configuration: null
+ SEG9:
+ name: PB11
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB11
+ mode: Peripheral IO
+ user_label: SEG9
+ configuration: null
+ SEG10:
+ name: PB12
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB12
+ mode: Peripheral IO
+ user_label: SEG10
+ configuration: null
+ SEG11:
+ name: PB13
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB13
+ mode: Peripheral IO
+ user_label: SEG11
+ configuration: null
+ SEG12:
+ name: PB14
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB14
+ mode: Peripheral IO
+ user_label: SEG12
+ configuration: null
+ SEG13:
+ name: PB15
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB15
+ mode: Peripheral IO
+ user_label: SEG13
+ configuration: null
+ SEG14:
+ name: PA12
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA12
+ mode: Peripheral IO
+ user_label: SEG14
+ configuration: null
+ SEG15:
+ name: PA13
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA13
+ mode: Peripheral IO
+ user_label: SEG15
+ configuration: null
+ SEG16:
+ name: PA14
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA14
+ mode: Peripheral IO
+ user_label: SEG16
+ configuration: null
+ SEG17:
+ name: PA15
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA15
+ mode: Peripheral IO
+ user_label: SEG17
+ configuration: null
+ SEG18:
+ name: PA16
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA16
+ mode: Peripheral IO
+ user_label: SEG18
+ configuration: null
+ SEG19:
+ name: PA17
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA17
+ mode: Peripheral IO
+ user_label: SEG19
+ configuration: null
+ SEG20:
+ name: PA18
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA18
+ mode: Peripheral IO
+ user_label: SEG20
+ configuration: null
+ SEG21:
+ name: PA19
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA19
+ mode: Peripheral IO
+ user_label: SEG21
+ configuration: null
+ SEG22:
+ name: PB16
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB16
+ mode: Peripheral IO
+ user_label: SEG22
+ configuration: null
+ SEG23:
+ name: PB17
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB17
+ mode: Peripheral IO
+ user_label: SEG23
+ configuration: null
+ RED:
+ name: PA20
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA20
+ mode: Peripheral IO
+ user_label: RED
+ configuration: null
+ GREEN:
+ name: PA21
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA21
+ mode: Peripheral IO
+ user_label: GREEN
+ configuration: null
+ BTN_LIGHT:
+ name: PA22
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA22
+ mode: Digital input
+ user_label: BTN_LIGHT
+ configuration:
+ pad_pull_config: Pull-down
+ BTN_MODE:
+ name: PA23
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA23
+ mode: Digital input
+ user_label: BTN_MODE
+ configuration:
+ pad_pull_config: Pull-down
+ BUZZER:
+ name: PA27
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA27
+ mode: Peripheral IO
+ user_label: BUZZER
+ configuration: null
+ SDA:
+ name: PB30
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB30
+ mode: I2C
+ user_label: SDA
+ configuration: null
+ SCL:
+ name: PB31
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB31
+ mode: I2C
+ user_label: SCL
+ configuration: null
+ D1:
+ name: PB00
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB00
+ mode: Digital output
+ user_label: D1
+ configuration: null
+ A1:
+ name: PB01
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB01
+ mode: Analog
+ user_label: A1
+ configuration: null
+ A2:
+ name: PB02
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB02
+ mode: Analog
+ user_label: A2
+ configuration: null
+ D0:
+ name: PB03
+ definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB03
+ mode: Digital output
+ user_label: D0
+ configuration: null
+toolchain_options: []
diff --git a/Smol Watch Project/My Project/Config/RTE_Components.h b/Smol Watch Project/My Project/Config/RTE_Components.h
new file mode 100644
index 00000000..3ba6b1ba
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/RTE_Components.h
@@ -0,0 +1,54 @@
+ /**
+ * \file
+ *
+ * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
+ *
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.
+ *
+ * \acme_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \acme_license_stop
+ *
+ * Project: My Project
+ * Target: ATSAML22J18A
+ *
+ **/
+
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+#define ATMEL_START
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Smol Watch Project/My Project/Config/hpl_adc_config.h b/Smol Watch Project/My Project/Config/hpl_adc_config.h
new file mode 100644
index 00000000..e15dc52f
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_adc_config.h
@@ -0,0 +1,305 @@
+/* Auto-generated config file hpl_adc_config.h */
+#ifndef HPL_ADC_CONFIG_H
+#define HPL_ADC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#ifndef CONF_ADC_0_ENABLE
+#define CONF_ADC_0_ENABLE 1
+#endif
+
+// Basic Configuration
+
+// Conversion Result Resolution
+// <0x0=>12-bit
+// <0x1=>16-bit (averaging must be enabled)
+// <0x2=>10-bit
+// <0x3=>8-bit
+// Defines the bit resolution for the ADC sample values (RESSEL)
+// adc_resolution
+#ifndef CONF_ADC_0_RESSEL
+#define CONF_ADC_0_RESSEL 0x0
+#endif
+
+// Reference Selection
+// <0x0=>Internal bandgap reference
+// <0x1=>1/1.6 VDDANA
+// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
+// <0x3=>External reference A
+// <0x4=>External reference B
+// <0x5=>VDDANA
+// Select the reference for the ADC (REFSEL)
+// adc_reference
+#ifndef CONF_ADC_0_REFSEL
+#define CONF_ADC_0_REFSEL 0x0
+#endif
+
+// Prescaler configuration
+// <0x0=>Peripheral clock divided by 2
+// <0x1=>Peripheral clock divided by 4
+// <0x2=>Peripheral clock divided by 8
+// <0x3=>Peripheral clock divided by 16
+// <0x4=>Peripheral clock divided by 32
+// <0x5=>Peripheral clock divided by 64
+// <0x6=>Peripheral clock divided by 128
+// <0x7=>Peripheral clock divided by 256
+// These bits define the ADC clock relative to the peripheral clock (PRESCALER)
+// adc_prescaler
+#ifndef CONF_ADC_0_PRESCALER
+#define CONF_ADC_0_PRESCALER 0x0
+#endif
+
+// Free Running Mode
+// When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
+// adc_freerunning_mode
+#ifndef CONF_ADC_0_FREERUN
+#define CONF_ADC_0_FREERUN 0
+#endif
+
+// Differential Mode
+// In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
+// adc_differential_mode
+#ifndef CONF_ADC_0_DIFFMODE
+#define CONF_ADC_0_DIFFMODE 0
+#endif
+
+// Positive Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x08=>ADC AIN8 pin
+// <0x09=>ADC AIN9 pin
+// <0x0A=>ADC AIN10 pin
+// <0x0B=>ADC AIN11 pin
+// <0x0C=>ADC AIN12 pin
+// <0x0D=>ADC AIN13 pin
+// <0x0E=>ADC AIN14 pin
+// <0x0F=>ADC AIN15 pin
+// <0x10=>ADC AIN16 pin
+// <0x11=>ADC AIN17 pin
+// <0x12=>ADC AIN18 pin
+// <0x13=>ADC AIN19 pin
+// <0x18=>Temperature reference
+// <0x19=>Bandgap voltage
+// <0x1A=>1/4 scaled core supply
+// <0x1B=>1/4 scaled I/O supply
+// <0x1D=>1/4 Scaled VBAT Supply
+// <0x1E=>CTAT Output
+// These bits define the Mux selection for the positive ADC input. (MUXPOS)
+// adc_pinmux_positive
+#ifndef CONF_ADC_0_MUXPOS
+#define CONF_ADC_0_MUXPOS 0x0
+#endif
+
+// Negative Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x18=>Internal ground
+// These bits define the Mux selection for the negative ADC input. (MUXNEG)
+// adc_pinmux_negative
+#ifndef CONF_ADC_0_MUXNEG
+#define CONF_ADC_0_MUXNEG 0x0
+#endif
+
+//
+
+// Advanced Configuration
+// adc_advanced_settings
+#ifndef CONF_ADC_0_ADVANCED
+#define CONF_ADC_0_ADVANCED 0
+#endif
+
+// Run in standby
+// Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
+// adc_arch_runstdby
+#ifndef CONF_ADC_0_RUNSTDBY
+#define CONF_ADC_0_RUNSTDBY 0
+#endif
+
+// Debug Run
+// If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
+// adc_arch_dbgrun
+#ifndef CONF_ADC_0_DBGRUN
+#define CONF_ADC_0_DBGRUN 0
+#endif
+
+// On Demand Control
+// Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
+// adc_arch_ondemand
+#ifndef CONF_ADC_0_ONDEMAND
+#define CONF_ADC_0_ONDEMAND 0
+#endif
+
+// Left-Adjusted Result
+// When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
+// adc_arch_leftadj
+#ifndef CONF_ADC_0_LEFTADJ
+#define CONF_ADC_0_LEFTADJ 0
+#endif
+
+// Reference Buffer Offset Compensation Enable
+// The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
+// adc_arch_refcomp
+#ifndef CONF_ADC_0_REFCOMP
+#define CONF_ADC_0_REFCOMP 0
+#endif
+
+// Comparator Offset Compensation Enable
+// This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
+// adc_arch_offcomp
+#ifndef CONF_ADC_0_OFFCOMP
+#define CONF_ADC_0_OFFCOMP 0
+#endif
+
+// Digital Correction Logic Enabled
+// When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
+// adc_arch_corren
+#ifndef CONF_ADC_0_CORREN
+#define CONF_ADC_0_CORREN 0
+#endif
+
+// Offset Correction Value <0-4095>
+// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
+// adc_arch_offsetcorr
+#ifndef CONF_ADC_0_OFFSETCORR
+#define CONF_ADC_0_OFFSETCORR 0
+#endif
+
+// Gain Correction Value <0-4095>
+// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
+// adc_arch_gaincorr
+#ifndef CONF_ADC_0_GAINCORR
+#define CONF_ADC_0_GAINCORR 0
+#endif
+
+// Adjusting Result / Division Coefficient <0-7>
+// These bits define the division coefficient in 2n steps. (ADJRES)
+// adc_arch_adjres
+#ifndef CONF_ADC_0_ADJRES
+#define CONF_ADC_0_ADJRES 0x0
+#endif
+
+// Number of Samples to be Collected
+// <0x0=>1 sample
+// <0x1=>2 samples
+// <0x2=>4 samples
+// <0x3=>8 samples
+// <0x4=>16 samples
+// <0x5=>32 samples
+// <0x6=>64 samples
+// <0x7=>128 samples
+// <0x8=>256 samples
+// <0x9=>512 samples
+// <0xA=>1024 samples
+// Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
+// adc_arch_samplenum
+#ifndef CONF_ADC_0_SAMPLENUM
+#define CONF_ADC_0_SAMPLENUM 0x0
+#endif
+
+// Sampling Time Length <0-63>
+// These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
+// adc_arch_samplen
+#ifndef CONF_ADC_0_SAMPLEN
+#define CONF_ADC_0_SAMPLEN 0
+#endif
+
+// Window Monitor Mode
+// <0x0=>No window mode
+// <0x1=>Mode 1: RESULT above lower threshold
+// <0x2=>Mode 2: RESULT beneath upper threshold
+// <0x3=>Mode 3: RESULT inside lower and upper threshold
+// <0x4=>Mode 4: RESULT outside lower and upper threshold
+// These bits enable and define the window monitor mode. (WINMODE)
+// adc_arch_winmode
+#ifndef CONF_ADC_0_WINMODE
+#define CONF_ADC_0_WINMODE 0x0
+#endif
+
+// Window Monitor Lower Threshold <0-65535>
+// If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
+// adc_arch_winlt
+#ifndef CONF_ADC_0_WINLT
+#define CONF_ADC_0_WINLT 0
+#endif
+
+// Window Monitor Upper Threshold <0-65535>
+// If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
+// adc_arch_winut
+#ifndef CONF_ADC_0_WINUT
+#define CONF_ADC_0_WINUT 0
+#endif
+
+// Bitmask for positive input sequence <0-4294967295>
+// Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
+// adc_arch_seqen
+#ifndef CONF_ADC_0_SEQEN
+#define CONF_ADC_0_SEQEN 0x0
+#endif
+
+//
+
+// Event Control
+// adc_arch_event_settings
+#ifndef CONF_ADC_0_EVENT_CONTROL
+#define CONF_ADC_0_EVENT_CONTROL 0
+#endif
+
+// Window Monitor Event Out
+// Enables event output on window event (WINMONEO)
+// adc_arch_winmoneo
+#ifndef CONF_ADC_0_WINMONEO
+#define CONF_ADC_0_WINMONEO 0
+#endif
+
+// Result Ready Event Out
+// Enables event output on result ready event (RESRDEO)
+// adc_arch_resrdyeo
+#ifndef CONF_ADC_0_RESRDYEO
+#define CONF_ADC_0_RESRDYEO 0
+#endif
+
+// Invert flush Event Signal
+// Invert the flush event input signal (FLUSHINV)
+// adc_arch_flushinv
+#ifndef CONF_ADC_0_FLUSHINV
+#define CONF_ADC_0_FLUSHINV 0
+#endif
+
+// Trigger Flush On Event
+// Trigger an ADC pipeline flush on event (FLUSHEI)
+// adc_arch_flushei
+#ifndef CONF_ADC_0_FLUSHEI
+#define CONF_ADC_0_FLUSHEI 0
+#endif
+
+// Invert Start Conversion Event Signal
+// Invert the start conversion event input signal (STARTINV)
+// adc_arch_startinv
+#ifndef CONF_ADC_0_STARTINV
+#define CONF_ADC_0_STARTINV 0
+#endif
+
+// Trigger Conversion On Event
+// Trigger a conversion on event. (STARTEI)
+// adc_arch_startei
+#ifndef CONF_ADC_0_STARTEI
+#define CONF_ADC_0_STARTEI 0
+#endif
+
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_ADC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_dmac_config.h b/Smol Watch Project/My Project/Config/hpl_dmac_config.h
new file mode 100644
index 00000000..36adb88b
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_dmac_config.h
@@ -0,0 +1,3122 @@
+/* Auto-generated config file hpl_dmac_config.h */
+#ifndef HPL_DMAC_CONFIG_H
+#define HPL_DMAC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// DMAC enable
+// Indicates whether dmac is enabled or not
+// dmac_enable
+#ifndef CONF_DMAC_ENABLE
+#define CONF_DMAC_ENABLE 0
+#endif
+
+// Priority Level 0
+// Indicates whether Priority Level 0 is enabled or not
+// dmac_lvlen0
+#ifndef CONF_DMAC_LVLEN0
+#define CONF_DMAC_LVLEN0 0
+#endif
+
+// Level 0 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 0
+// <1=> Round-robin arbitration scheme for channel with priority 0
+// Defines Level 0 Arbitration for DMA channels
+// dmac_rrlvlen0
+#ifndef CONF_DMAC_RRLVLEN0
+#define CONF_DMAC_RRLVLEN0 0
+#endif
+
+// Level 0 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri0
+#ifndef CONF_DMAC_LVLPRI0
+#define CONF_DMAC_LVLPRI0 0
+#endif
+
+// Priority Level 1
+// Indicates whether Priority Level 1 is enabled or not
+// dmac_lvlen1
+#ifndef CONF_DMAC_LVLEN1
+#define CONF_DMAC_LVLEN1 0
+#endif
+
+// Level 1 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 1
+// <1=> Round-robin arbitration scheme for channel with priority 1
+// Defines Level 1 Arbitration for DMA channels
+// dmac_rrlvlen1
+#ifndef CONF_DMAC_RRLVLEN1
+#define CONF_DMAC_RRLVLEN1 0
+#endif
+
+// Level 1 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri1
+#ifndef CONF_DMAC_LVLPRI1
+#define CONF_DMAC_LVLPRI1 0
+#endif
+
+// Priority Level 2
+// Indicates whether Priority Level 2 is enabled or not
+// dmac_lvlen2
+#ifndef CONF_DMAC_LVLEN2
+#define CONF_DMAC_LVLEN2 0
+#endif
+
+// Level 2 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 2
+// <1=> Round-robin arbitration scheme for channel with priority 2
+// Defines Level 2 Arbitration for DMA channels
+// dmac_rrlvlen2
+#ifndef CONF_DMAC_RRLVLEN2
+#define CONF_DMAC_RRLVLEN2 0
+#endif
+
+// Level 2 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri2
+#ifndef CONF_DMAC_LVLPRI2
+#define CONF_DMAC_LVLPRI2 0
+#endif
+
+// Priority Level 3
+// Indicates whether Priority Level 3 is enabled or not
+// dmac_lvlen3
+#ifndef CONF_DMAC_LVLEN3
+#define CONF_DMAC_LVLEN3 0
+#endif
+
+// Level 3 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 3
+// <1=> Round-robin arbitration scheme for channel with priority 3
+// Defines Level 3 Arbitration for DMA channels
+// dmac_rrlvlen3
+#ifndef CONF_DMAC_RRLVLEN3
+#define CONF_DMAC_RRLVLEN3 0
+#endif
+
+// Level 3 Channel Priority Number <0x00-0xFF>
+// dmac_lvlpri3
+#ifndef CONF_DMAC_LVLPRI3
+#define CONF_DMAC_LVLPRI3 0
+#endif
+
+// Data Transfer Quality of Service
+// <0=> Background (no sensitive operation)
+// <1=> Sensitive bandwidth
+// <2=> Sensitive latency
+// <3=> Critical latency
+// Defines the memory priority access during the data transfer operation
+// dmac_dqos
+#ifndef CONF_DMAC_DQOS
+#define CONF_DMAC_DQOS 0
+#endif
+
+// Fetch Quality of Service
+// <0=> Background (no sensitive operation)
+// <1=> Sensitive bandwidth
+// <2=> Sensitive latency
+// <3=> Critical latency
+// Defines the memory priority access during the fetch operation
+// dmac_fqos
+#ifndef CONF_DMAC_FQOS
+#define CONF_DMAC_FQOS 0
+#endif
+
+// Write-Back Quality of Service
+// <0=> Background (no sensitive operation)
+// <1=> Sensitive bandwidth
+// <2=> Sensitive latency
+// <3=> Critical latency
+// Defines the memory priority access during the write-back operation
+// dmac_wrbqos
+#ifndef CONF_DMAC_WRBQOS
+#define CONF_DMAC_WRBQOS 0
+#endif
+
+// Debug Run
+// Indicates whether Debug Run is enabled or not
+// dmac_dbgrun
+#ifndef CONF_DMAC_DBGRUN
+#define CONF_DMAC_DBGRUN 0
+#endif
+
+// Channel 0 settings
+// dmac_channel_0_settings
+#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
+#define CONF_DMAC_CHANNEL_0_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 0 is enabled or not
+// dmac_enable_0
+#ifndef CONF_DMAC_ENABLE_0
+#define CONF_DMAC_ENABLE_0 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 0 is running in standby mode or not
+// dmac_runstdby_0
+#ifndef CONF_DMAC_RUNSTDBY_0
+#define CONF_DMAC_RUNSTDBY_0 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_0
+#ifndef CONF_DMAC_TRIGACT_0
+#define CONF_DMAC_TRIGACT_0 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_0
+#ifndef CONF_DMAC_TRIGSRC_0
+#define CONF_DMAC_TRIGSRC_0 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_0
+#ifndef CONF_DMAC_LVL_0
+#define CONF_DMAC_LVL_0 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_0
+#ifndef CONF_DMAC_EVOE_0
+#define CONF_DMAC_EVOE_0 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_0
+#ifndef CONF_DMAC_EVIE_0
+#define CONF_DMAC_EVIE_0 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_0
+#ifndef CONF_DMAC_EVACT_0
+#define CONF_DMAC_EVACT_0 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_0
+#ifndef CONF_DMAC_STEPSIZE_0
+#define CONF_DMAC_STEPSIZE_0 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_0
+#ifndef CONF_DMAC_STEPSEL_0
+#define CONF_DMAC_STEPSEL_0 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_0
+#ifndef CONF_DMAC_SRCINC_0
+#define CONF_DMAC_SRCINC_0 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_0
+#ifndef CONF_DMAC_DSTINC_0
+#define CONF_DMAC_DSTINC_0 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_0
+#ifndef CONF_DMAC_BEATSIZE_0
+#define CONF_DMAC_BEATSIZE_0 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_0
+#ifndef CONF_DMAC_BLOCKACT_0
+#define CONF_DMAC_BLOCKACT_0 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_0
+#ifndef CONF_DMAC_EVOSEL_0
+#define CONF_DMAC_EVOSEL_0 0
+#endif
+//
+
+// Channel 1 settings
+// dmac_channel_1_settings
+#ifndef CONF_DMAC_CHANNEL_1_SETTINGS
+#define CONF_DMAC_CHANNEL_1_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 1 is enabled or not
+// dmac_enable_1
+#ifndef CONF_DMAC_ENABLE_1
+#define CONF_DMAC_ENABLE_1 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 1 is running in standby mode or not
+// dmac_runstdby_1
+#ifndef CONF_DMAC_RUNSTDBY_1
+#define CONF_DMAC_RUNSTDBY_1 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_1
+#ifndef CONF_DMAC_TRIGACT_1
+#define CONF_DMAC_TRIGACT_1 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_1
+#ifndef CONF_DMAC_TRIGSRC_1
+#define CONF_DMAC_TRIGSRC_1 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_1
+#ifndef CONF_DMAC_LVL_1
+#define CONF_DMAC_LVL_1 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_1
+#ifndef CONF_DMAC_EVOE_1
+#define CONF_DMAC_EVOE_1 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_1
+#ifndef CONF_DMAC_EVIE_1
+#define CONF_DMAC_EVIE_1 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_1
+#ifndef CONF_DMAC_EVACT_1
+#define CONF_DMAC_EVACT_1 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_1
+#ifndef CONF_DMAC_STEPSIZE_1
+#define CONF_DMAC_STEPSIZE_1 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_1
+#ifndef CONF_DMAC_STEPSEL_1
+#define CONF_DMAC_STEPSEL_1 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_1
+#ifndef CONF_DMAC_SRCINC_1
+#define CONF_DMAC_SRCINC_1 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_1
+#ifndef CONF_DMAC_DSTINC_1
+#define CONF_DMAC_DSTINC_1 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_1
+#ifndef CONF_DMAC_BEATSIZE_1
+#define CONF_DMAC_BEATSIZE_1 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_1
+#ifndef CONF_DMAC_BLOCKACT_1
+#define CONF_DMAC_BLOCKACT_1 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_1
+#ifndef CONF_DMAC_EVOSEL_1
+#define CONF_DMAC_EVOSEL_1 0
+#endif
+//
+
+// Channel 2 settings
+// dmac_channel_2_settings
+#ifndef CONF_DMAC_CHANNEL_2_SETTINGS
+#define CONF_DMAC_CHANNEL_2_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 2 is enabled or not
+// dmac_enable_2
+#ifndef CONF_DMAC_ENABLE_2
+#define CONF_DMAC_ENABLE_2 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 2 is running in standby mode or not
+// dmac_runstdby_2
+#ifndef CONF_DMAC_RUNSTDBY_2
+#define CONF_DMAC_RUNSTDBY_2 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_2
+#ifndef CONF_DMAC_TRIGACT_2
+#define CONF_DMAC_TRIGACT_2 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_2
+#ifndef CONF_DMAC_TRIGSRC_2
+#define CONF_DMAC_TRIGSRC_2 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_2
+#ifndef CONF_DMAC_LVL_2
+#define CONF_DMAC_LVL_2 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_2
+#ifndef CONF_DMAC_EVOE_2
+#define CONF_DMAC_EVOE_2 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_2
+#ifndef CONF_DMAC_EVIE_2
+#define CONF_DMAC_EVIE_2 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_2
+#ifndef CONF_DMAC_EVACT_2
+#define CONF_DMAC_EVACT_2 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_2
+#ifndef CONF_DMAC_STEPSIZE_2
+#define CONF_DMAC_STEPSIZE_2 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_2
+#ifndef CONF_DMAC_STEPSEL_2
+#define CONF_DMAC_STEPSEL_2 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_2
+#ifndef CONF_DMAC_SRCINC_2
+#define CONF_DMAC_SRCINC_2 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_2
+#ifndef CONF_DMAC_DSTINC_2
+#define CONF_DMAC_DSTINC_2 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_2
+#ifndef CONF_DMAC_BEATSIZE_2
+#define CONF_DMAC_BEATSIZE_2 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_2
+#ifndef CONF_DMAC_BLOCKACT_2
+#define CONF_DMAC_BLOCKACT_2 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_2
+#ifndef CONF_DMAC_EVOSEL_2
+#define CONF_DMAC_EVOSEL_2 0
+#endif
+//
+
+// Channel 3 settings
+// dmac_channel_3_settings
+#ifndef CONF_DMAC_CHANNEL_3_SETTINGS
+#define CONF_DMAC_CHANNEL_3_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 3 is enabled or not
+// dmac_enable_3
+#ifndef CONF_DMAC_ENABLE_3
+#define CONF_DMAC_ENABLE_3 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 3 is running in standby mode or not
+// dmac_runstdby_3
+#ifndef CONF_DMAC_RUNSTDBY_3
+#define CONF_DMAC_RUNSTDBY_3 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_3
+#ifndef CONF_DMAC_TRIGACT_3
+#define CONF_DMAC_TRIGACT_3 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_3
+#ifndef CONF_DMAC_TRIGSRC_3
+#define CONF_DMAC_TRIGSRC_3 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_3
+#ifndef CONF_DMAC_LVL_3
+#define CONF_DMAC_LVL_3 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_3
+#ifndef CONF_DMAC_EVOE_3
+#define CONF_DMAC_EVOE_3 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_3
+#ifndef CONF_DMAC_EVIE_3
+#define CONF_DMAC_EVIE_3 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_3
+#ifndef CONF_DMAC_EVACT_3
+#define CONF_DMAC_EVACT_3 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_3
+#ifndef CONF_DMAC_STEPSIZE_3
+#define CONF_DMAC_STEPSIZE_3 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_3
+#ifndef CONF_DMAC_STEPSEL_3
+#define CONF_DMAC_STEPSEL_3 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_3
+#ifndef CONF_DMAC_SRCINC_3
+#define CONF_DMAC_SRCINC_3 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_3
+#ifndef CONF_DMAC_DSTINC_3
+#define CONF_DMAC_DSTINC_3 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_3
+#ifndef CONF_DMAC_BEATSIZE_3
+#define CONF_DMAC_BEATSIZE_3 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_3
+#ifndef CONF_DMAC_BLOCKACT_3
+#define CONF_DMAC_BLOCKACT_3 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_3
+#ifndef CONF_DMAC_EVOSEL_3
+#define CONF_DMAC_EVOSEL_3 0
+#endif
+//
+
+// Channel 4 settings
+// dmac_channel_4_settings
+#ifndef CONF_DMAC_CHANNEL_4_SETTINGS
+#define CONF_DMAC_CHANNEL_4_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 4 is enabled or not
+// dmac_enable_4
+#ifndef CONF_DMAC_ENABLE_4
+#define CONF_DMAC_ENABLE_4 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 4 is running in standby mode or not
+// dmac_runstdby_4
+#ifndef CONF_DMAC_RUNSTDBY_4
+#define CONF_DMAC_RUNSTDBY_4 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_4
+#ifndef CONF_DMAC_TRIGACT_4
+#define CONF_DMAC_TRIGACT_4 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_4
+#ifndef CONF_DMAC_TRIGSRC_4
+#define CONF_DMAC_TRIGSRC_4 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_4
+#ifndef CONF_DMAC_LVL_4
+#define CONF_DMAC_LVL_4 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_4
+#ifndef CONF_DMAC_EVOE_4
+#define CONF_DMAC_EVOE_4 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_4
+#ifndef CONF_DMAC_EVIE_4
+#define CONF_DMAC_EVIE_4 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_4
+#ifndef CONF_DMAC_EVACT_4
+#define CONF_DMAC_EVACT_4 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_4
+#ifndef CONF_DMAC_STEPSIZE_4
+#define CONF_DMAC_STEPSIZE_4 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_4
+#ifndef CONF_DMAC_STEPSEL_4
+#define CONF_DMAC_STEPSEL_4 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_4
+#ifndef CONF_DMAC_SRCINC_4
+#define CONF_DMAC_SRCINC_4 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_4
+#ifndef CONF_DMAC_DSTINC_4
+#define CONF_DMAC_DSTINC_4 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_4
+#ifndef CONF_DMAC_BEATSIZE_4
+#define CONF_DMAC_BEATSIZE_4 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_4
+#ifndef CONF_DMAC_BLOCKACT_4
+#define CONF_DMAC_BLOCKACT_4 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_4
+#ifndef CONF_DMAC_EVOSEL_4
+#define CONF_DMAC_EVOSEL_4 0
+#endif
+//
+
+// Channel 5 settings
+// dmac_channel_5_settings
+#ifndef CONF_DMAC_CHANNEL_5_SETTINGS
+#define CONF_DMAC_CHANNEL_5_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 5 is enabled or not
+// dmac_enable_5
+#ifndef CONF_DMAC_ENABLE_5
+#define CONF_DMAC_ENABLE_5 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 5 is running in standby mode or not
+// dmac_runstdby_5
+#ifndef CONF_DMAC_RUNSTDBY_5
+#define CONF_DMAC_RUNSTDBY_5 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_5
+#ifndef CONF_DMAC_TRIGACT_5
+#define CONF_DMAC_TRIGACT_5 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_5
+#ifndef CONF_DMAC_TRIGSRC_5
+#define CONF_DMAC_TRIGSRC_5 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_5
+#ifndef CONF_DMAC_LVL_5
+#define CONF_DMAC_LVL_5 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_5
+#ifndef CONF_DMAC_EVOE_5
+#define CONF_DMAC_EVOE_5 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_5
+#ifndef CONF_DMAC_EVIE_5
+#define CONF_DMAC_EVIE_5 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_5
+#ifndef CONF_DMAC_EVACT_5
+#define CONF_DMAC_EVACT_5 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_5
+#ifndef CONF_DMAC_STEPSIZE_5
+#define CONF_DMAC_STEPSIZE_5 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_5
+#ifndef CONF_DMAC_STEPSEL_5
+#define CONF_DMAC_STEPSEL_5 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_5
+#ifndef CONF_DMAC_SRCINC_5
+#define CONF_DMAC_SRCINC_5 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_5
+#ifndef CONF_DMAC_DSTINC_5
+#define CONF_DMAC_DSTINC_5 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_5
+#ifndef CONF_DMAC_BEATSIZE_5
+#define CONF_DMAC_BEATSIZE_5 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_5
+#ifndef CONF_DMAC_BLOCKACT_5
+#define CONF_DMAC_BLOCKACT_5 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_5
+#ifndef CONF_DMAC_EVOSEL_5
+#define CONF_DMAC_EVOSEL_5 0
+#endif
+//
+
+// Channel 6 settings
+// dmac_channel_6_settings
+#ifndef CONF_DMAC_CHANNEL_6_SETTINGS
+#define CONF_DMAC_CHANNEL_6_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 6 is enabled or not
+// dmac_enable_6
+#ifndef CONF_DMAC_ENABLE_6
+#define CONF_DMAC_ENABLE_6 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 6 is running in standby mode or not
+// dmac_runstdby_6
+#ifndef CONF_DMAC_RUNSTDBY_6
+#define CONF_DMAC_RUNSTDBY_6 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_6
+#ifndef CONF_DMAC_TRIGACT_6
+#define CONF_DMAC_TRIGACT_6 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_6
+#ifndef CONF_DMAC_TRIGSRC_6
+#define CONF_DMAC_TRIGSRC_6 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_6
+#ifndef CONF_DMAC_LVL_6
+#define CONF_DMAC_LVL_6 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_6
+#ifndef CONF_DMAC_EVOE_6
+#define CONF_DMAC_EVOE_6 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_6
+#ifndef CONF_DMAC_EVIE_6
+#define CONF_DMAC_EVIE_6 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_6
+#ifndef CONF_DMAC_EVACT_6
+#define CONF_DMAC_EVACT_6 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_6
+#ifndef CONF_DMAC_STEPSIZE_6
+#define CONF_DMAC_STEPSIZE_6 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_6
+#ifndef CONF_DMAC_STEPSEL_6
+#define CONF_DMAC_STEPSEL_6 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_6
+#ifndef CONF_DMAC_SRCINC_6
+#define CONF_DMAC_SRCINC_6 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_6
+#ifndef CONF_DMAC_DSTINC_6
+#define CONF_DMAC_DSTINC_6 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_6
+#ifndef CONF_DMAC_BEATSIZE_6
+#define CONF_DMAC_BEATSIZE_6 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_6
+#ifndef CONF_DMAC_BLOCKACT_6
+#define CONF_DMAC_BLOCKACT_6 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_6
+#ifndef CONF_DMAC_EVOSEL_6
+#define CONF_DMAC_EVOSEL_6 0
+#endif
+//
+
+// Channel 7 settings
+// dmac_channel_7_settings
+#ifndef CONF_DMAC_CHANNEL_7_SETTINGS
+#define CONF_DMAC_CHANNEL_7_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 7 is enabled or not
+// dmac_enable_7
+#ifndef CONF_DMAC_ENABLE_7
+#define CONF_DMAC_ENABLE_7 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 7 is running in standby mode or not
+// dmac_runstdby_7
+#ifndef CONF_DMAC_RUNSTDBY_7
+#define CONF_DMAC_RUNSTDBY_7 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_7
+#ifndef CONF_DMAC_TRIGACT_7
+#define CONF_DMAC_TRIGACT_7 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_7
+#ifndef CONF_DMAC_TRIGSRC_7
+#define CONF_DMAC_TRIGSRC_7 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_7
+#ifndef CONF_DMAC_LVL_7
+#define CONF_DMAC_LVL_7 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_7
+#ifndef CONF_DMAC_EVOE_7
+#define CONF_DMAC_EVOE_7 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_7
+#ifndef CONF_DMAC_EVIE_7
+#define CONF_DMAC_EVIE_7 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_7
+#ifndef CONF_DMAC_EVACT_7
+#define CONF_DMAC_EVACT_7 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_7
+#ifndef CONF_DMAC_STEPSIZE_7
+#define CONF_DMAC_STEPSIZE_7 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_7
+#ifndef CONF_DMAC_STEPSEL_7
+#define CONF_DMAC_STEPSEL_7 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_7
+#ifndef CONF_DMAC_SRCINC_7
+#define CONF_DMAC_SRCINC_7 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_7
+#ifndef CONF_DMAC_DSTINC_7
+#define CONF_DMAC_DSTINC_7 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_7
+#ifndef CONF_DMAC_BEATSIZE_7
+#define CONF_DMAC_BEATSIZE_7 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_7
+#ifndef CONF_DMAC_BLOCKACT_7
+#define CONF_DMAC_BLOCKACT_7 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_7
+#ifndef CONF_DMAC_EVOSEL_7
+#define CONF_DMAC_EVOSEL_7 0
+#endif
+//
+
+// Channel 8 settings
+// dmac_channel_8_settings
+#ifndef CONF_DMAC_CHANNEL_8_SETTINGS
+#define CONF_DMAC_CHANNEL_8_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 8 is enabled or not
+// dmac_enable_8
+#ifndef CONF_DMAC_ENABLE_8
+#define CONF_DMAC_ENABLE_8 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 8 is running in standby mode or not
+// dmac_runstdby_8
+#ifndef CONF_DMAC_RUNSTDBY_8
+#define CONF_DMAC_RUNSTDBY_8 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_8
+#ifndef CONF_DMAC_TRIGACT_8
+#define CONF_DMAC_TRIGACT_8 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_8
+#ifndef CONF_DMAC_TRIGSRC_8
+#define CONF_DMAC_TRIGSRC_8 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_8
+#ifndef CONF_DMAC_LVL_8
+#define CONF_DMAC_LVL_8 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_8
+#ifndef CONF_DMAC_EVOE_8
+#define CONF_DMAC_EVOE_8 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_8
+#ifndef CONF_DMAC_EVIE_8
+#define CONF_DMAC_EVIE_8 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_8
+#ifndef CONF_DMAC_EVACT_8
+#define CONF_DMAC_EVACT_8 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_8
+#ifndef CONF_DMAC_STEPSIZE_8
+#define CONF_DMAC_STEPSIZE_8 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_8
+#ifndef CONF_DMAC_STEPSEL_8
+#define CONF_DMAC_STEPSEL_8 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_8
+#ifndef CONF_DMAC_SRCINC_8
+#define CONF_DMAC_SRCINC_8 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_8
+#ifndef CONF_DMAC_DSTINC_8
+#define CONF_DMAC_DSTINC_8 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_8
+#ifndef CONF_DMAC_BEATSIZE_8
+#define CONF_DMAC_BEATSIZE_8 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_8
+#ifndef CONF_DMAC_BLOCKACT_8
+#define CONF_DMAC_BLOCKACT_8 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_8
+#ifndef CONF_DMAC_EVOSEL_8
+#define CONF_DMAC_EVOSEL_8 0
+#endif
+//
+
+// Channel 9 settings
+// dmac_channel_9_settings
+#ifndef CONF_DMAC_CHANNEL_9_SETTINGS
+#define CONF_DMAC_CHANNEL_9_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 9 is enabled or not
+// dmac_enable_9
+#ifndef CONF_DMAC_ENABLE_9
+#define CONF_DMAC_ENABLE_9 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 9 is running in standby mode or not
+// dmac_runstdby_9
+#ifndef CONF_DMAC_RUNSTDBY_9
+#define CONF_DMAC_RUNSTDBY_9 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_9
+#ifndef CONF_DMAC_TRIGACT_9
+#define CONF_DMAC_TRIGACT_9 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_9
+#ifndef CONF_DMAC_TRIGSRC_9
+#define CONF_DMAC_TRIGSRC_9 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_9
+#ifndef CONF_DMAC_LVL_9
+#define CONF_DMAC_LVL_9 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_9
+#ifndef CONF_DMAC_EVOE_9
+#define CONF_DMAC_EVOE_9 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_9
+#ifndef CONF_DMAC_EVIE_9
+#define CONF_DMAC_EVIE_9 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_9
+#ifndef CONF_DMAC_EVACT_9
+#define CONF_DMAC_EVACT_9 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_9
+#ifndef CONF_DMAC_STEPSIZE_9
+#define CONF_DMAC_STEPSIZE_9 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_9
+#ifndef CONF_DMAC_STEPSEL_9
+#define CONF_DMAC_STEPSEL_9 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_9
+#ifndef CONF_DMAC_SRCINC_9
+#define CONF_DMAC_SRCINC_9 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_9
+#ifndef CONF_DMAC_DSTINC_9
+#define CONF_DMAC_DSTINC_9 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_9
+#ifndef CONF_DMAC_BEATSIZE_9
+#define CONF_DMAC_BEATSIZE_9 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_9
+#ifndef CONF_DMAC_BLOCKACT_9
+#define CONF_DMAC_BLOCKACT_9 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_9
+#ifndef CONF_DMAC_EVOSEL_9
+#define CONF_DMAC_EVOSEL_9 0
+#endif
+//
+
+// Channel 10 settings
+// dmac_channel_10_settings
+#ifndef CONF_DMAC_CHANNEL_10_SETTINGS
+#define CONF_DMAC_CHANNEL_10_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 10 is enabled or not
+// dmac_enable_10
+#ifndef CONF_DMAC_ENABLE_10
+#define CONF_DMAC_ENABLE_10 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 10 is running in standby mode or not
+// dmac_runstdby_10
+#ifndef CONF_DMAC_RUNSTDBY_10
+#define CONF_DMAC_RUNSTDBY_10 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_10
+#ifndef CONF_DMAC_TRIGACT_10
+#define CONF_DMAC_TRIGACT_10 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_10
+#ifndef CONF_DMAC_TRIGSRC_10
+#define CONF_DMAC_TRIGSRC_10 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_10
+#ifndef CONF_DMAC_LVL_10
+#define CONF_DMAC_LVL_10 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_10
+#ifndef CONF_DMAC_EVOE_10
+#define CONF_DMAC_EVOE_10 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_10
+#ifndef CONF_DMAC_EVIE_10
+#define CONF_DMAC_EVIE_10 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_10
+#ifndef CONF_DMAC_EVACT_10
+#define CONF_DMAC_EVACT_10 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_10
+#ifndef CONF_DMAC_STEPSIZE_10
+#define CONF_DMAC_STEPSIZE_10 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_10
+#ifndef CONF_DMAC_STEPSEL_10
+#define CONF_DMAC_STEPSEL_10 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_10
+#ifndef CONF_DMAC_SRCINC_10
+#define CONF_DMAC_SRCINC_10 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_10
+#ifndef CONF_DMAC_DSTINC_10
+#define CONF_DMAC_DSTINC_10 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_10
+#ifndef CONF_DMAC_BEATSIZE_10
+#define CONF_DMAC_BEATSIZE_10 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_10
+#ifndef CONF_DMAC_BLOCKACT_10
+#define CONF_DMAC_BLOCKACT_10 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_10
+#ifndef CONF_DMAC_EVOSEL_10
+#define CONF_DMAC_EVOSEL_10 0
+#endif
+//
+
+// Channel 11 settings
+// dmac_channel_11_settings
+#ifndef CONF_DMAC_CHANNEL_11_SETTINGS
+#define CONF_DMAC_CHANNEL_11_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 11 is enabled or not
+// dmac_enable_11
+#ifndef CONF_DMAC_ENABLE_11
+#define CONF_DMAC_ENABLE_11 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 11 is running in standby mode or not
+// dmac_runstdby_11
+#ifndef CONF_DMAC_RUNSTDBY_11
+#define CONF_DMAC_RUNSTDBY_11 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_11
+#ifndef CONF_DMAC_TRIGACT_11
+#define CONF_DMAC_TRIGACT_11 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_11
+#ifndef CONF_DMAC_TRIGSRC_11
+#define CONF_DMAC_TRIGSRC_11 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_11
+#ifndef CONF_DMAC_LVL_11
+#define CONF_DMAC_LVL_11 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_11
+#ifndef CONF_DMAC_EVOE_11
+#define CONF_DMAC_EVOE_11 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_11
+#ifndef CONF_DMAC_EVIE_11
+#define CONF_DMAC_EVIE_11 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_11
+#ifndef CONF_DMAC_EVACT_11
+#define CONF_DMAC_EVACT_11 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_11
+#ifndef CONF_DMAC_STEPSIZE_11
+#define CONF_DMAC_STEPSIZE_11 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_11
+#ifndef CONF_DMAC_STEPSEL_11
+#define CONF_DMAC_STEPSEL_11 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_11
+#ifndef CONF_DMAC_SRCINC_11
+#define CONF_DMAC_SRCINC_11 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_11
+#ifndef CONF_DMAC_DSTINC_11
+#define CONF_DMAC_DSTINC_11 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_11
+#ifndef CONF_DMAC_BEATSIZE_11
+#define CONF_DMAC_BEATSIZE_11 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_11
+#ifndef CONF_DMAC_BLOCKACT_11
+#define CONF_DMAC_BLOCKACT_11 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_11
+#ifndef CONF_DMAC_EVOSEL_11
+#define CONF_DMAC_EVOSEL_11 0
+#endif
+//
+
+// Channel 12 settings
+// dmac_channel_12_settings
+#ifndef CONF_DMAC_CHANNEL_12_SETTINGS
+#define CONF_DMAC_CHANNEL_12_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 12 is enabled or not
+// dmac_enable_12
+#ifndef CONF_DMAC_ENABLE_12
+#define CONF_DMAC_ENABLE_12 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 12 is running in standby mode or not
+// dmac_runstdby_12
+#ifndef CONF_DMAC_RUNSTDBY_12
+#define CONF_DMAC_RUNSTDBY_12 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_12
+#ifndef CONF_DMAC_TRIGACT_12
+#define CONF_DMAC_TRIGACT_12 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_12
+#ifndef CONF_DMAC_TRIGSRC_12
+#define CONF_DMAC_TRIGSRC_12 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_12
+#ifndef CONF_DMAC_LVL_12
+#define CONF_DMAC_LVL_12 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_12
+#ifndef CONF_DMAC_EVOE_12
+#define CONF_DMAC_EVOE_12 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_12
+#ifndef CONF_DMAC_EVIE_12
+#define CONF_DMAC_EVIE_12 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_12
+#ifndef CONF_DMAC_EVACT_12
+#define CONF_DMAC_EVACT_12 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_12
+#ifndef CONF_DMAC_STEPSIZE_12
+#define CONF_DMAC_STEPSIZE_12 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_12
+#ifndef CONF_DMAC_STEPSEL_12
+#define CONF_DMAC_STEPSEL_12 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_12
+#ifndef CONF_DMAC_SRCINC_12
+#define CONF_DMAC_SRCINC_12 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_12
+#ifndef CONF_DMAC_DSTINC_12
+#define CONF_DMAC_DSTINC_12 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_12
+#ifndef CONF_DMAC_BEATSIZE_12
+#define CONF_DMAC_BEATSIZE_12 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_12
+#ifndef CONF_DMAC_BLOCKACT_12
+#define CONF_DMAC_BLOCKACT_12 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_12
+#ifndef CONF_DMAC_EVOSEL_12
+#define CONF_DMAC_EVOSEL_12 0
+#endif
+//
+
+// Channel 13 settings
+// dmac_channel_13_settings
+#ifndef CONF_DMAC_CHANNEL_13_SETTINGS
+#define CONF_DMAC_CHANNEL_13_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 13 is enabled or not
+// dmac_enable_13
+#ifndef CONF_DMAC_ENABLE_13
+#define CONF_DMAC_ENABLE_13 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 13 is running in standby mode or not
+// dmac_runstdby_13
+#ifndef CONF_DMAC_RUNSTDBY_13
+#define CONF_DMAC_RUNSTDBY_13 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_13
+#ifndef CONF_DMAC_TRIGACT_13
+#define CONF_DMAC_TRIGACT_13 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_13
+#ifndef CONF_DMAC_TRIGSRC_13
+#define CONF_DMAC_TRIGSRC_13 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_13
+#ifndef CONF_DMAC_LVL_13
+#define CONF_DMAC_LVL_13 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_13
+#ifndef CONF_DMAC_EVOE_13
+#define CONF_DMAC_EVOE_13 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_13
+#ifndef CONF_DMAC_EVIE_13
+#define CONF_DMAC_EVIE_13 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_13
+#ifndef CONF_DMAC_EVACT_13
+#define CONF_DMAC_EVACT_13 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_13
+#ifndef CONF_DMAC_STEPSIZE_13
+#define CONF_DMAC_STEPSIZE_13 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_13
+#ifndef CONF_DMAC_STEPSEL_13
+#define CONF_DMAC_STEPSEL_13 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_13
+#ifndef CONF_DMAC_SRCINC_13
+#define CONF_DMAC_SRCINC_13 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_13
+#ifndef CONF_DMAC_DSTINC_13
+#define CONF_DMAC_DSTINC_13 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_13
+#ifndef CONF_DMAC_BEATSIZE_13
+#define CONF_DMAC_BEATSIZE_13 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_13
+#ifndef CONF_DMAC_BLOCKACT_13
+#define CONF_DMAC_BLOCKACT_13 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_13
+#ifndef CONF_DMAC_EVOSEL_13
+#define CONF_DMAC_EVOSEL_13 0
+#endif
+//
+
+// Channel 14 settings
+// dmac_channel_14_settings
+#ifndef CONF_DMAC_CHANNEL_14_SETTINGS
+#define CONF_DMAC_CHANNEL_14_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 14 is enabled or not
+// dmac_enable_14
+#ifndef CONF_DMAC_ENABLE_14
+#define CONF_DMAC_ENABLE_14 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 14 is running in standby mode or not
+// dmac_runstdby_14
+#ifndef CONF_DMAC_RUNSTDBY_14
+#define CONF_DMAC_RUNSTDBY_14 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_14
+#ifndef CONF_DMAC_TRIGACT_14
+#define CONF_DMAC_TRIGACT_14 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_14
+#ifndef CONF_DMAC_TRIGSRC_14
+#define CONF_DMAC_TRIGSRC_14 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_14
+#ifndef CONF_DMAC_LVL_14
+#define CONF_DMAC_LVL_14 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_14
+#ifndef CONF_DMAC_EVOE_14
+#define CONF_DMAC_EVOE_14 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_14
+#ifndef CONF_DMAC_EVIE_14
+#define CONF_DMAC_EVIE_14 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_14
+#ifndef CONF_DMAC_EVACT_14
+#define CONF_DMAC_EVACT_14 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_14
+#ifndef CONF_DMAC_STEPSIZE_14
+#define CONF_DMAC_STEPSIZE_14 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_14
+#ifndef CONF_DMAC_STEPSEL_14
+#define CONF_DMAC_STEPSEL_14 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_14
+#ifndef CONF_DMAC_SRCINC_14
+#define CONF_DMAC_SRCINC_14 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_14
+#ifndef CONF_DMAC_DSTINC_14
+#define CONF_DMAC_DSTINC_14 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_14
+#ifndef CONF_DMAC_BEATSIZE_14
+#define CONF_DMAC_BEATSIZE_14 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_14
+#ifndef CONF_DMAC_BLOCKACT_14
+#define CONF_DMAC_BLOCKACT_14 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_14
+#ifndef CONF_DMAC_EVOSEL_14
+#define CONF_DMAC_EVOSEL_14 0
+#endif
+//
+
+// Channel 15 settings
+// dmac_channel_15_settings
+#ifndef CONF_DMAC_CHANNEL_15_SETTINGS
+#define CONF_DMAC_CHANNEL_15_SETTINGS 0
+#endif
+
+// Channel Enable
+// Indicates whether channel 15 is enabled or not
+// dmac_enable_15
+#ifndef CONF_DMAC_ENABLE_15
+#define CONF_DMAC_ENABLE_15 0
+#endif
+
+// Channel Run in Standby
+// Indicates whether channel 15 is running in standby mode or not
+// dmac_runstdby_15
+#ifndef CONF_DMAC_RUNSTDBY_15
+#define CONF_DMAC_RUNSTDBY_15 0
+#endif
+
+// Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// Defines the trigger action used for a transfer
+// dmac_trigact_15
+#ifndef CONF_DMAC_TRIGACT_15
+#define CONF_DMAC_TRIGACT_15 0
+#endif
+
+// Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// Defines the peripheral trigger which is source of the transfer
+// dmac_trifsrc_15
+#ifndef CONF_DMAC_TRIGSRC_15
+#define CONF_DMAC_TRIGSRC_15 0
+#endif
+
+// Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// Defines the arbitration level for this channel
+// dmac_lvl_15
+#ifndef CONF_DMAC_LVL_15
+#define CONF_DMAC_LVL_15 0
+#endif
+
+// Channel Event Output
+// Indicates whether channel event generation is enabled or not
+// dmac_evoe_15
+#ifndef CONF_DMAC_EVOE_15
+#define CONF_DMAC_EVOE_15 0
+#endif
+
+// Channel Event Input
+// Indicates whether channel event reception is enabled or not
+// dmac_evie_15
+#ifndef CONF_DMAC_EVIE_15
+#define CONF_DMAC_EVIE_15 0
+#endif
+
+// Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// Defines the event input action
+// dmac_evact_15
+#ifndef CONF_DMAC_EVACT_15
+#define CONF_DMAC_EVACT_15 0
+#endif
+
+// Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// Defines the address increment step size, applies to source or destination address
+// dmac_stepsize_15
+#ifndef CONF_DMAC_STEPSIZE_15
+#define CONF_DMAC_STEPSIZE_15 0
+#endif
+
+// Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// Defines whether source or destination addresses are using the step size settings
+// dmac_stepsel_15
+#ifndef CONF_DMAC_STEPSEL_15
+#define CONF_DMAC_STEPSEL_15 0
+#endif
+
+// Source Address Increment
+// Indicates whether the source address incrementation is enabled or not
+// dmac_srcinc_15
+#ifndef CONF_DMAC_SRCINC_15
+#define CONF_DMAC_SRCINC_15 0
+#endif
+
+// Destination Address Increment
+// Indicates whether the destination address incrementation is enabled or not
+// dmac_dstinc_15
+#ifndef CONF_DMAC_DSTINC_15
+#define CONF_DMAC_DSTINC_15 0
+#endif
+
+// Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// Defines the size of one beat
+// dmac_beatsize_15
+#ifndef CONF_DMAC_BEATSIZE_15
+#define CONF_DMAC_BEATSIZE_15 0
+#endif
+
+// Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// Defines the the DMAC should take after a block transfer has completed
+// dmac_blockact_15
+#ifndef CONF_DMAC_BLOCKACT_15
+#define CONF_DMAC_BLOCKACT_15 0
+#endif
+
+// Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// Defines the event output selection
+// dmac_evosel_15
+#ifndef CONF_DMAC_EVOSEL_15
+#define CONF_DMAC_EVOSEL_15 0
+#endif
+//
+
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_DMAC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_eic_config.h b/Smol Watch Project/My Project/Config/hpl_eic_config.h
new file mode 100644
index 00000000..3b268a10
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_eic_config.h
@@ -0,0 +1,730 @@
+/* Auto-generated config file hpl_eic_config.h */
+#ifndef HPL_EIC_CONFIG_H
+#define HPL_EIC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Basic Settings
+// Clock Selection
+// Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or
+// either by CLK_ULP32K when power consumption is the priority.
+// <0x0=> Clocked by GCLK
+// <0x1=> Clocked by ULPOSC32K
+// eic_arch_cksel
+#ifndef CONF_EIC_CKSEL
+#define CONF_EIC_CKSEL 0
+#endif
+
+//
+
+// Non-Maskable Interrupt Control
+// eic_arch_nmi_ctrl
+#ifndef CONF_EIC_ENABLE_NMI_CTRL
+#define CONF_EIC_ENABLE_NMI_CTRL 0
+#endif
+
+// Non-Maskable Interrupt Filter Enable
+// Indicates whether the mon-maskable interrupt filter is enabled or not
+// eic_arch_nmifilten
+#ifndef CONF_EIC_NMIFILTEN
+#define CONF_EIC_NMIFILTEN 0
+#endif
+
+// Non-Maskable Interrupt Sense
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines non-maskable interrupt sense
+// eic_arch_nmisense
+#ifndef CONF_EIC_NMISENSE
+#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// Asynchronous Edge Detection Mode
+// Indicates the interrupt detection mode operated synchronously or asynchronousl
+// eic_arch_nmiasynch
+#ifndef CONF_EIC_NMIASYNCH
+#define CONF_EIC_NMIASYNCH 0
+#endif
+//
+
+// Interrupt 0 Settings
+// eic_arch_enable_irq_setting0
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
+#define CONF_EIC_ENABLE_IRQ_SETTING0 0
+#endif
+
+// External Interrupt 0 Filter Enable
+// Indicates whether the external interrupt 0 filter is enabled or not
+// eic_arch_filten0
+#ifndef CONF_EIC_FILTEN0
+#define CONF_EIC_FILTEN0 0
+#endif
+
+// External Interrupt 0 Event Output Enable
+// Indicates whether the external interrupt 0 event output is enabled or not
+// eic_arch_extinteo0
+#ifndef CONF_EIC_EXTINTEO0
+#define CONF_EIC_EXTINTEO0 0
+#endif
+
+// Input 0 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense0
+#ifndef CONF_EIC_SENSE0
+#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 0 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch0
+#ifndef CONF_EIC_ASYNCH0
+#define CONF_EIC_ASYNCH0 0
+#endif
+
+//
+
+// Interrupt 1 Settings
+// eic_arch_enable_irq_setting1
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
+#define CONF_EIC_ENABLE_IRQ_SETTING1 0
+#endif
+
+// External Interrupt 1 Filter Enable
+// Indicates whether the external interrupt 1 filter is enabled or not
+// eic_arch_filten1
+#ifndef CONF_EIC_FILTEN1
+#define CONF_EIC_FILTEN1 0
+#endif
+
+// External Interrupt 1 Event Output Enable
+// Indicates whether the external interrupt 1 event output is enabled or not
+// eic_arch_extinteo1
+#ifndef CONF_EIC_EXTINTEO1
+#define CONF_EIC_EXTINTEO1 0
+#endif
+
+// Input 1 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense1
+#ifndef CONF_EIC_SENSE1
+#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 1 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch1
+#ifndef CONF_EIC_ASYNCH1
+#define CONF_EIC_ASYNCH1 0
+#endif
+
+//
+
+// Interrupt 2 Settings
+// eic_arch_enable_irq_setting2
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
+#define CONF_EIC_ENABLE_IRQ_SETTING2 0
+#endif
+
+// External Interrupt 2 Filter Enable
+// Indicates whether the external interrupt 2 filter is enabled or not
+// eic_arch_filten2
+#ifndef CONF_EIC_FILTEN2
+#define CONF_EIC_FILTEN2 0
+#endif
+
+// External Interrupt 2 Event Output Enable
+// Indicates whether the external interrupt 2 event output is enabled or not
+// eic_arch_extinteo2
+#ifndef CONF_EIC_EXTINTEO2
+#define CONF_EIC_EXTINTEO2 0
+#endif
+
+// Input 2 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense2
+#ifndef CONF_EIC_SENSE2
+#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 2 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch2
+#ifndef CONF_EIC_ASYNCH2
+#define CONF_EIC_ASYNCH2 0
+#endif
+
+//
+
+// Interrupt 3 Settings
+// eic_arch_enable_irq_setting3
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
+#define CONF_EIC_ENABLE_IRQ_SETTING3 0
+#endif
+
+// External Interrupt 3 Filter Enable
+// Indicates whether the external interrupt 3 filter is enabled or not
+// eic_arch_filten3
+#ifndef CONF_EIC_FILTEN3
+#define CONF_EIC_FILTEN3 0
+#endif
+
+// External Interrupt 3 Event Output Enable
+// Indicates whether the external interrupt 3 event output is enabled or not
+// eic_arch_extinteo3
+#ifndef CONF_EIC_EXTINTEO3
+#define CONF_EIC_EXTINTEO3 0
+#endif
+
+// Input 3 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense3
+#ifndef CONF_EIC_SENSE3
+#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 3 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch3
+#ifndef CONF_EIC_ASYNCH3
+#define CONF_EIC_ASYNCH3 0
+#endif
+
+//
+
+// Interrupt 4 Settings
+// eic_arch_enable_irq_setting4
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
+#define CONF_EIC_ENABLE_IRQ_SETTING4 0
+#endif
+
+// External Interrupt 4 Filter Enable
+// Indicates whether the external interrupt 4 filter is enabled or not
+// eic_arch_filten4
+#ifndef CONF_EIC_FILTEN4
+#define CONF_EIC_FILTEN4 0
+#endif
+
+// External Interrupt 4 Event Output Enable
+// Indicates whether the external interrupt 4 event output is enabled or not
+// eic_arch_extinteo4
+#ifndef CONF_EIC_EXTINTEO4
+#define CONF_EIC_EXTINTEO4 0
+#endif
+
+// Input 4 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense4
+#ifndef CONF_EIC_SENSE4
+#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 4 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch4
+#ifndef CONF_EIC_ASYNCH4
+#define CONF_EIC_ASYNCH4 0
+#endif
+
+//
+
+// Interrupt 5 Settings
+// eic_arch_enable_irq_setting5
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
+#define CONF_EIC_ENABLE_IRQ_SETTING5 1
+#endif
+
+// External Interrupt 5 Filter Enable
+// Indicates whether the external interrupt 5 filter is enabled or not
+// eic_arch_filten5
+#ifndef CONF_EIC_FILTEN5
+#define CONF_EIC_FILTEN5 0
+#endif
+
+// External Interrupt 5 Event Output Enable
+// Indicates whether the external interrupt 5 event output is enabled or not
+// eic_arch_extinteo5
+#ifndef CONF_EIC_EXTINTEO5
+#define CONF_EIC_EXTINTEO5 0
+#endif
+
+// Input 5 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense5
+#ifndef CONF_EIC_SENSE5
+#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_RISE_Val
+#endif
+
+// External Interrupt 5 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch5
+#ifndef CONF_EIC_ASYNCH5
+#define CONF_EIC_ASYNCH5 0
+#endif
+
+//
+
+// Interrupt 6 Settings
+// eic_arch_enable_irq_setting6
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
+#define CONF_EIC_ENABLE_IRQ_SETTING6 1
+#endif
+
+// External Interrupt 6 Filter Enable
+// Indicates whether the external interrupt 6 filter is enabled or not
+// eic_arch_filten6
+#ifndef CONF_EIC_FILTEN6
+#define CONF_EIC_FILTEN6 0
+#endif
+
+// External Interrupt 6 Event Output Enable
+// Indicates whether the external interrupt 6 event output is enabled or not
+// eic_arch_extinteo6
+#ifndef CONF_EIC_EXTINTEO6
+#define CONF_EIC_EXTINTEO6 0
+#endif
+
+// Input 6 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense6
+#ifndef CONF_EIC_SENSE6
+#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_RISE_Val
+#endif
+
+// External Interrupt 6 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch6
+#ifndef CONF_EIC_ASYNCH6
+#define CONF_EIC_ASYNCH6 0
+#endif
+
+//
+
+// Interrupt 7 Settings
+// eic_arch_enable_irq_setting7
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
+#define CONF_EIC_ENABLE_IRQ_SETTING7 1
+#endif
+
+// External Interrupt 7 Filter Enable
+// Indicates whether the external interrupt 7 filter is enabled or not
+// eic_arch_filten7
+#ifndef CONF_EIC_FILTEN7
+#define CONF_EIC_FILTEN7 0
+#endif
+
+// External Interrupt 7 Event Output Enable
+// Indicates whether the external interrupt 7 event output is enabled or not
+// eic_arch_extinteo7
+#ifndef CONF_EIC_EXTINTEO7
+#define CONF_EIC_EXTINTEO7 0
+#endif
+
+// Input 7 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense7
+#ifndef CONF_EIC_SENSE7
+#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_RISE_Val
+#endif
+
+// External Interrupt 7 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch7
+#ifndef CONF_EIC_ASYNCH7
+#define CONF_EIC_ASYNCH7 0
+#endif
+
+//
+
+// Interrupt 8 Settings
+// eic_arch_enable_irq_setting8
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING8
+#define CONF_EIC_ENABLE_IRQ_SETTING8 0
+#endif
+
+// External Interrupt 8 Filter Enable
+// Indicates whether the external interrupt 8 filter is enabled or not
+// eic_arch_filten8
+#ifndef CONF_EIC_FILTEN8
+#define CONF_EIC_FILTEN8 0
+#endif
+
+// External Interrupt 8 Event Output Enable
+// Indicates whether the external interrupt 8 event output is enabled or not
+// eic_arch_extinteo8
+#ifndef CONF_EIC_EXTINTEO8
+#define CONF_EIC_EXTINTEO8 0
+#endif
+
+// Input 8 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense8
+#ifndef CONF_EIC_SENSE8
+#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 8 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch8
+#ifndef CONF_EIC_ASYNCH8
+#define CONF_EIC_ASYNCH8 0
+#endif
+
+//
+
+// Interrupt 9 Settings
+// eic_arch_enable_irq_setting9
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING9
+#define CONF_EIC_ENABLE_IRQ_SETTING9 0
+#endif
+
+// External Interrupt 9 Filter Enable
+// Indicates whether the external interrupt 9 filter is enabled or not
+// eic_arch_filten9
+#ifndef CONF_EIC_FILTEN9
+#define CONF_EIC_FILTEN9 0
+#endif
+
+// External Interrupt 9 Event Output Enable
+// Indicates whether the external interrupt 9 event output is enabled or not
+// eic_arch_extinteo9
+#ifndef CONF_EIC_EXTINTEO9
+#define CONF_EIC_EXTINTEO9 0
+#endif
+
+// Input 9 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense9
+#ifndef CONF_EIC_SENSE9
+#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 9 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch9
+#ifndef CONF_EIC_ASYNCH9
+#define CONF_EIC_ASYNCH9 0
+#endif
+
+//
+
+// Interrupt 10 Settings
+// eic_arch_enable_irq_setting10
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING10
+#define CONF_EIC_ENABLE_IRQ_SETTING10 0
+#endif
+
+// External Interrupt 10 Filter Enable
+// Indicates whether the external interrupt 10 filter is enabled or not
+// eic_arch_filten10
+#ifndef CONF_EIC_FILTEN10
+#define CONF_EIC_FILTEN10 0
+#endif
+
+// External Interrupt 10 Event Output Enable
+// Indicates whether the external interrupt 10 event output is enabled or not
+// eic_arch_extinteo10
+#ifndef CONF_EIC_EXTINTEO10
+#define CONF_EIC_EXTINTEO10 0
+#endif
+
+// Input 10 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense10
+#ifndef CONF_EIC_SENSE10
+#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 10 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch10
+#ifndef CONF_EIC_ASYNCH10
+#define CONF_EIC_ASYNCH10 0
+#endif
+
+//
+
+// Interrupt 11 Settings
+// eic_arch_enable_irq_setting11
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING11
+#define CONF_EIC_ENABLE_IRQ_SETTING11 0
+#endif
+
+// External Interrupt 11 Filter Enable
+// Indicates whether the external interrupt 11 filter is enabled or not
+// eic_arch_filten11
+#ifndef CONF_EIC_FILTEN11
+#define CONF_EIC_FILTEN11 0
+#endif
+
+// External Interrupt 11 Event Output Enable
+// Indicates whether the external interrupt 11 event output is enabled or not
+// eic_arch_extinteo11
+#ifndef CONF_EIC_EXTINTEO11
+#define CONF_EIC_EXTINTEO11 0
+#endif
+
+// Input 11 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense11
+#ifndef CONF_EIC_SENSE11
+#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 11 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch11
+#ifndef CONF_EIC_ASYNCH11
+#define CONF_EIC_ASYNCH11 0
+#endif
+
+//
+
+// Interrupt 12 Settings
+// eic_arch_enable_irq_setting12
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING12
+#define CONF_EIC_ENABLE_IRQ_SETTING12 0
+#endif
+
+// External Interrupt 12 Filter Enable
+// Indicates whether the external interrupt 12 filter is enabled or not
+// eic_arch_filten12
+#ifndef CONF_EIC_FILTEN12
+#define CONF_EIC_FILTEN12 0
+#endif
+
+// External Interrupt 12 Event Output Enable
+// Indicates whether the external interrupt 12 event output is enabled or not
+// eic_arch_extinteo12
+#ifndef CONF_EIC_EXTINTEO12
+#define CONF_EIC_EXTINTEO12 0
+#endif
+
+// Input 12 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense12
+#ifndef CONF_EIC_SENSE12
+#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 12 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch12
+#ifndef CONF_EIC_ASYNCH12
+#define CONF_EIC_ASYNCH12 0
+#endif
+
+//
+
+// Interrupt 13 Settings
+// eic_arch_enable_irq_setting13
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING13
+#define CONF_EIC_ENABLE_IRQ_SETTING13 0
+#endif
+
+// External Interrupt 13 Filter Enable
+// Indicates whether the external interrupt 13 filter is enabled or not
+// eic_arch_filten13
+#ifndef CONF_EIC_FILTEN13
+#define CONF_EIC_FILTEN13 0
+#endif
+
+// External Interrupt 13 Event Output Enable
+// Indicates whether the external interrupt 13 event output is enabled or not
+// eic_arch_extinteo13
+#ifndef CONF_EIC_EXTINTEO13
+#define CONF_EIC_EXTINTEO13 0
+#endif
+
+// Input 13 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense13
+#ifndef CONF_EIC_SENSE13
+#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 13 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch13
+#ifndef CONF_EIC_ASYNCH13
+#define CONF_EIC_ASYNCH13 0
+#endif
+
+//
+
+// Interrupt 14 Settings
+// eic_arch_enable_irq_setting14
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING14
+#define CONF_EIC_ENABLE_IRQ_SETTING14 0
+#endif
+
+// External Interrupt 14 Filter Enable
+// Indicates whether the external interrupt 14 filter is enabled or not
+// eic_arch_filten14
+#ifndef CONF_EIC_FILTEN14
+#define CONF_EIC_FILTEN14 0
+#endif
+
+// External Interrupt 14 Event Output Enable
+// Indicates whether the external interrupt 14 event output is enabled or not
+// eic_arch_extinteo14
+#ifndef CONF_EIC_EXTINTEO14
+#define CONF_EIC_EXTINTEO14 0
+#endif
+
+// Input 14 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense14
+#ifndef CONF_EIC_SENSE14
+#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 14 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch14
+#ifndef CONF_EIC_ASYNCH14
+#define CONF_EIC_ASYNCH14 0
+#endif
+
+//
+
+// Interrupt 15 Settings
+// eic_arch_enable_irq_setting15
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING15
+#define CONF_EIC_ENABLE_IRQ_SETTING15 0
+#endif
+
+// External Interrupt 15 Filter Enable
+// Indicates whether the external interrupt 15 filter is enabled or not
+// eic_arch_filten15
+#ifndef CONF_EIC_FILTEN15
+#define CONF_EIC_FILTEN15 0
+#endif
+
+// External Interrupt 15 Event Output Enable
+// Indicates whether the external interrupt 15 event output is enabled or not
+// eic_arch_extinteo15
+#ifndef CONF_EIC_EXTINTEO15
+#define CONF_EIC_EXTINTEO15 0
+#endif
+
+// Input 15 Sense Configuration
+// No detection
+// Rising-edge detection
+// Falling-edge detection
+// Both-edges detection
+// High-level detection
+// Low-level detection
+// This defines input sense trigger
+// eic_arch_sense15
+#ifndef CONF_EIC_SENSE15
+#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// External Interrupt 15 Asynchronous Edge Detection Mode
+// Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
+// eic_arch_asynch15
+#ifndef CONF_EIC_ASYNCH15
+#define CONF_EIC_ASYNCH15 0
+#endif
+
+//
+
+#define CONFIG_EIC_EXTINT_MAP {5, PIN_PB05}, {6, PIN_PA22}, {7, PIN_PA23},
+
+// <<< end of configuration section >>>
+
+#endif // HPL_EIC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_gclk_config.h b/Smol Watch Project/My Project/Config/hpl_gclk_config.h
new file mode 100644
index 00000000..c56e2816
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_gclk_config.h
@@ -0,0 +1,383 @@
+/* Auto-generated config file hpl_gclk_config.h */
+#ifndef HPL_GCLK_CONFIG_H
+#define HPL_GCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Generic clock generator 0 configuration
+// Indicates whether generic clock 0 configuration is enabled or not
+// enable_gclk_gen_0
+#ifndef CONF_GCLK_GENERATOR_0_CONFIG
+#define CONF_GCLK_GENERATOR_0_CONFIG 1
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 0 source
+// External Crystal Oscillator 0.4-32MHz (XOSC)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// 16MHz Internal Oscillator (OSC16M)
+// Digital Frequency Locked Loop (DFLL48M)
+// Fractional Digital Phase Locked Loop (FDPLL96M)
+// This defines the clock source for generic clock generator 0
+// gclk_gen_0_oscillator
+#ifndef CONF_GCLK_GEN_0_SOURCE
+#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_0_runstdby
+#ifndef CONF_GCLK_GEN_0_RUNSTDBY
+#define CONF_GCLK_GEN_0_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_0_div_sel
+#ifndef CONF_GCLK_GEN_0_DIVSEL
+#define CONF_GCLK_GEN_0_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_0_oe
+#ifndef CONF_GCLK_GEN_0_OE
+#define CONF_GCLK_GEN_0_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_0_oov
+#ifndef CONF_GCLK_GEN_0_OOV
+#define CONF_GCLK_GEN_0_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_0_idc
+#ifndef CONF_GCLK_GEN_0_IDC
+#define CONF_GCLK_GEN_0_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_0_enable
+#ifndef CONF_GCLK_GEN_0_GENEN
+#define CONF_GCLK_GEN_0_GENEN 1
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 0 division <0x0000-0xFFFF>
+// gclk_gen_0_div
+#ifndef CONF_GCLK_GEN_0_DIV
+#define CONF_GCLK_GEN_0_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 1 configuration
+// Indicates whether generic clock 1 configuration is enabled or not
+// enable_gclk_gen_1
+#ifndef CONF_GCLK_GENERATOR_1_CONFIG
+#define CONF_GCLK_GENERATOR_1_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 1 source
+// External Crystal Oscillator 0.4-32MHz (XOSC)
+// Generic clock generator input pad
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// 16MHz Internal Oscillator (OSC16M)
+// Digital Frequency Locked Loop (DFLL48M)
+// Fractional Digital Phase Locked Loop (FDPLL96M)
+// This defines the clock source for generic clock generator 1
+// gclk_gen_1_oscillator
+#ifndef CONF_GCLK_GEN_1_SOURCE
+#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_1_runstdby
+#ifndef CONF_GCLK_GEN_1_RUNSTDBY
+#define CONF_GCLK_GEN_1_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_1_div_sel
+#ifndef CONF_GCLK_GEN_1_DIVSEL
+#define CONF_GCLK_GEN_1_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_1_oe
+#ifndef CONF_GCLK_GEN_1_OE
+#define CONF_GCLK_GEN_1_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_1_oov
+#ifndef CONF_GCLK_GEN_1_OOV
+#define CONF_GCLK_GEN_1_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_1_idc
+#ifndef CONF_GCLK_GEN_1_IDC
+#define CONF_GCLK_GEN_1_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_1_enable
+#ifndef CONF_GCLK_GEN_1_GENEN
+#define CONF_GCLK_GEN_1_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 1 division <0x0000-0xFFFF>
+// gclk_gen_1_div
+#ifndef CONF_GCLK_GEN_1_DIV
+#define CONF_GCLK_GEN_1_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 2 configuration
+// Indicates whether generic clock 2 configuration is enabled or not
+// enable_gclk_gen_2
+#ifndef CONF_GCLK_GENERATOR_2_CONFIG
+#define CONF_GCLK_GENERATOR_2_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 2 source
+// External Crystal Oscillator 0.4-32MHz (XOSC)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// 16MHz Internal Oscillator (OSC16M)
+// Digital Frequency Locked Loop (DFLL48M)
+// Fractional Digital Phase Locked Loop (FDPLL96M)
+// This defines the clock source for generic clock generator 2
+// gclk_gen_2_oscillator
+#ifndef CONF_GCLK_GEN_2_SOURCE
+#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_2_runstdby
+#ifndef CONF_GCLK_GEN_2_RUNSTDBY
+#define CONF_GCLK_GEN_2_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_2_div_sel
+#ifndef CONF_GCLK_GEN_2_DIVSEL
+#define CONF_GCLK_GEN_2_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_2_oe
+#ifndef CONF_GCLK_GEN_2_OE
+#define CONF_GCLK_GEN_2_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_2_oov
+#ifndef CONF_GCLK_GEN_2_OOV
+#define CONF_GCLK_GEN_2_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_2_idc
+#ifndef CONF_GCLK_GEN_2_IDC
+#define CONF_GCLK_GEN_2_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_2_enable
+#ifndef CONF_GCLK_GEN_2_GENEN
+#define CONF_GCLK_GEN_2_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 2 division <0x0000-0xFFFF>
+// gclk_gen_2_div
+#ifndef CONF_GCLK_GEN_2_DIV
+#define CONF_GCLK_GEN_2_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 3 configuration
+// Indicates whether generic clock 3 configuration is enabled or not
+// enable_gclk_gen_3
+#ifndef CONF_GCLK_GENERATOR_3_CONFIG
+#define CONF_GCLK_GENERATOR_3_CONFIG 1
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 3 source
+// External Crystal Oscillator 0.4-32MHz (XOSC)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// 16MHz Internal Oscillator (OSC16M)
+// Digital Frequency Locked Loop (DFLL48M)
+// Fractional Digital Phase Locked Loop (FDPLL96M)
+// This defines the clock source for generic clock generator 3
+// gclk_gen_3_oscillator
+#ifndef CONF_GCLK_GEN_3_SOURCE
+#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_3_runstdby
+#ifndef CONF_GCLK_GEN_3_RUNSTDBY
+#define CONF_GCLK_GEN_3_RUNSTDBY 1
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_3_div_sel
+#ifndef CONF_GCLK_GEN_3_DIVSEL
+#define CONF_GCLK_GEN_3_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_3_oe
+#ifndef CONF_GCLK_GEN_3_OE
+#define CONF_GCLK_GEN_3_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_3_oov
+#ifndef CONF_GCLK_GEN_3_OOV
+#define CONF_GCLK_GEN_3_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_3_idc
+#ifndef CONF_GCLK_GEN_3_IDC
+#define CONF_GCLK_GEN_3_IDC 1
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_3_enable
+#ifndef CONF_GCLK_GEN_3_GENEN
+#define CONF_GCLK_GEN_3_GENEN 1
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 3 division <0x0000-0xFFFF>
+// gclk_gen_3_div
+#ifndef CONF_GCLK_GEN_3_DIV
+#define CONF_GCLK_GEN_3_DIV 1
+#endif
+//
+//
+
+// Generic clock generator 4 configuration
+// Indicates whether generic clock 4 configuration is enabled or not
+// enable_gclk_gen_4
+#ifndef CONF_GCLK_GENERATOR_4_CONFIG
+#define CONF_GCLK_GENERATOR_4_CONFIG 0
+#endif
+
+// Generic Clock Generator Control
+// Generic clock generator 4 source
+// External Crystal Oscillator 0.4-32MHz (XOSC)
+// Generic clock generator input pad
+// Generic clock generator 1
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// 16MHz Internal Oscillator (OSC16M)
+// Digital Frequency Locked Loop (DFLL48M)
+// Fractional Digital Phase Locked Loop (FDPLL96M)
+// This defines the clock source for generic clock generator 4
+// gclk_gen_4_oscillator
+#ifndef CONF_GCLK_GEN_4_SOURCE
+#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// gclk_arch_gen_4_runstdby
+#ifndef CONF_GCLK_GEN_4_RUNSTDBY
+#define CONF_GCLK_GEN_4_RUNSTDBY 0
+#endif
+
+// Divide Selection
+// Indicates whether Divide Selection is enabled or not
+// gclk_gen_4_div_sel
+#ifndef CONF_GCLK_GEN_4_DIVSEL
+#define CONF_GCLK_GEN_4_DIVSEL 0
+#endif
+
+// Output Enable
+// Indicates whether Output Enable is enabled or not
+// gclk_arch_gen_4_oe
+#ifndef CONF_GCLK_GEN_4_OE
+#define CONF_GCLK_GEN_4_OE 0
+#endif
+
+// Output Off Value
+// Indicates whether Output Off Value is enabled or not
+// gclk_arch_gen_4_oov
+#ifndef CONF_GCLK_GEN_4_OOV
+#define CONF_GCLK_GEN_4_OOV 0
+#endif
+
+// Improve Duty Cycle
+// Indicates whether Improve Duty Cycle is enabled or not
+// gclk_arch_gen_4_idc
+#ifndef CONF_GCLK_GEN_4_IDC
+#define CONF_GCLK_GEN_4_IDC 0
+#endif
+
+// Generic Clock Generator Enable
+// Indicates whether Generic Clock Generator Enable is enabled or not
+// gclk_arch_gen_4_enable
+#ifndef CONF_GCLK_GEN_4_GENEN
+#define CONF_GCLK_GEN_4_GENEN 0
+#endif
+//
+
+// Generic Clock Generator Division
+// Generic clock generator 4 division <0x0000-0xFFFF>
+// gclk_gen_4_div
+#ifndef CONF_GCLK_GEN_4_DIV
+#define CONF_GCLK_GEN_4_DIV 1
+#endif
+//
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_GCLK_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_mclk_config.h b/Smol Watch Project/My Project/Config/hpl_mclk_config.h
new file mode 100644
index 00000000..be1cd54d
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_mclk_config.h
@@ -0,0 +1,85 @@
+/* Auto-generated config file hpl_mclk_config.h */
+#ifndef HPL_MCLK_CONFIG_H
+#define HPL_MCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include
+
+// System Configuration
+// Indicates whether configuration for system is enabled or not
+// enable_cpu_clock
+#ifndef CONF_SYSTEM_CONFIG
+#define CONF_SYSTEM_CONFIG 1
+#endif
+
+// Basic settings
+// CPU Clock source
+// Generic clock generator 0
+// This defines the clock source for the CPU
+// cpu_clock_source
+#ifndef CONF_CPU_SRC
+#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// CPU Clock Division Factor
+// 1
+// 2
+// 4
+// 8
+// 16
+// 32
+// 64
+// 128
+// Prescalar for CPU clock
+// cpu_div
+#ifndef CONF_MCLK_CPUDIV
+#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val
+#endif
+
+// Backup Clock Division
+// Divide by 1
+// Divide by 2
+// Divide by 4
+// Divide by 8
+// Divide by 16
+// Divide by 32
+// Divide by 64
+// Divide by 128
+// mclk_arch_bupdiv
+#ifndef CONF_MCLK_BUPDIV
+#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
+#endif
+//
+
+// NVM Settings
+// NVM Wait States
+// These bits select the number of wait states for a read operation.
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// nvm_wait_states
+#ifndef CONF_NVM_WAIT_STATE
+#define CONF_NVM_WAIT_STATE 0
+#endif
+
+//
+
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_MCLK_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_osc32kctrl_config.h b/Smol Watch Project/My Project/Config/hpl_osc32kctrl_config.h
new file mode 100644
index 00000000..55e297ae
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_osc32kctrl_config.h
@@ -0,0 +1,173 @@
+/* Auto-generated config file hpl_osc32kctrl_config.h */
+#ifndef HPL_OSC32KCTRL_CONFIG_H
+#define HPL_OSC32KCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// RTC Source configuration
+// enable_rtc_source
+#ifndef CONF_RTCCTRL_CONFIG
+#define CONF_RTCCTRL_CONFIG 0
+#endif
+
+// RTC source control
+// RTC Clock Source Selection
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// This defines the clock source for RTC
+// rtc_source_oscillator
+#ifndef CONF_RTCCTRL_SRC
+#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// Use 1 kHz output
+// rtc_1khz_selection
+#ifndef CONF_RTCCTRL_1KHZ
+
+#define CONF_RTCCTRL_1KHZ 1
+
+#endif
+
+#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
+#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
+#else
+#error unexpected CONF_RTCCTRL_SRC
+#endif
+
+//
+//
+// SLCD Source configuration
+// enable_slcd_source
+#ifndef CONF_SLCDCTRL_CONFIG
+#define CONF_SLCDCTRL_CONFIG 0
+#endif
+
+// SLCD source control
+// SLCD Clock Source Selection
+// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// 32kHz External Crystal Oscillator (XOSC32K)
+// This defines the clock source for SLCD
+// slcd_source_oscillator
+#ifndef CONF_SLCDCTRL_SRC
+#define CONF_SLCDCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+//
+//
+// 32kHz External Crystal Oscillator Configuration
+// Indicates whether configuration for External 32K Osc is enabled or not
+// enable_xosc32k
+#ifndef CONF_XOSC32K_CONFIG
+#define CONF_XOSC32K_CONFIG 1
+#endif
+
+// 32kHz External Crystal Oscillator Control
+// Oscillator enable
+// Indicates whether 32kHz External Crystal Oscillator is enabled or not
+// xosc32k_arch_enable
+#ifndef CONF_XOSC32K_ENABLE
+#define CONF_XOSC32K_ENABLE 1
+#endif
+
+// Start-Up Time
+// <0x0=>62592us
+// <0x1=>125092us
+// <0x2=>500092us
+// <0x3=>1000092us
+// <0x4=>2000092us
+// <0x5=>4000092us
+// <0x6=>8000092us
+// xosc32k_arch_startup
+#ifndef CONF_XOSC32K_STARTUP
+#define CONF_XOSC32K_STARTUP 0x0
+#endif
+
+// On Demand Control
+// Indicates whether On Demand Control is enabled or not
+// xosc32k_arch_ondemand
+#ifndef CONF_XOSC32K_ONDEMAND
+#define CONF_XOSC32K_ONDEMAND 1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// xosc32k_arch_runstdby
+#ifndef CONF_XOSC32K_RUNSTDBY
+#define CONF_XOSC32K_RUNSTDBY 0
+#endif
+
+// 1kHz Output Enable
+// Indicates whether 1kHz Output is enabled or not
+// xosc32k_arch_en1k
+#ifndef CONF_XOSC32K_EN1K
+#define CONF_XOSC32K_EN1K 1
+#endif
+
+// 32kHz Output Enable
+// Indicates whether 32kHz Output is enabled or not
+// xosc32k_arch_en32k
+#ifndef CONF_XOSC32K_EN32K
+#define CONF_XOSC32K_EN32K 1
+#endif
+
+// Clock Switch Back
+// Indicates whether Clock Switch Back is enabled or not
+// xosc32k_arch_swben
+#ifndef CONF_XOSC32K_SWBEN
+#define CONF_XOSC32K_SWBEN 0
+#endif
+
+// Clock Failure Detector
+// Indicates whether Clock Failure Detector is enabled or not
+// xosc32k_arch_cfden
+#ifndef CONF_XOSC32K_CFDEN
+#define CONF_XOSC32K_CFDEN 0
+#endif
+
+// Clock Failure Detector Event Out
+// Indicates whether Clock Failure Detector Event Out is enabled or not
+// xosc32k_arch_cfdeo
+#ifndef CONF_XOSC32K_CFDEO
+#define CONF_XOSC32K_CFDEO 0
+#endif
+
+// Crystal connected to XIN32/XOUT32 Enable
+// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// xosc32k_arch_xtalen
+#ifndef CONF_XOSC32K_XTALEN
+#define CONF_XOSC32K_XTALEN 1
+#endif
+
+//
+//
+
+// 32kHz Ultra Low Power Internal Oscillator Configuration
+// Indicates whether configuration for OSCULP32K is enabled or not
+// enable_osculp32k
+#ifndef CONF_OSCULP32K_CONFIG
+#define CONF_OSCULP32K_CONFIG 1
+#endif
+
+// 32kHz Ultra Low Power Internal Oscillator Control
+
+// Oscillator Calibration Control
+// Indicates whether Oscillator Calibration is enabled or not
+// osculp32k_calib_enable
+#ifndef CONF_OSCULP32K_CALIB_ENABLE
+#define CONF_OSCULP32K_CALIB_ENABLE 0
+#endif
+
+// Oscillator Calibration <0x0-0x1F>
+// osculp32k_calib
+#ifndef CONF_OSCULP32K_CALIB
+#define CONF_OSCULP32K_CALIB 0x0
+#endif
+
+//
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSC32KCTRL_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_oscctrl_config.h b/Smol Watch Project/My Project/Config/hpl_oscctrl_config.h
new file mode 100644
index 00000000..ba2d42e6
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_oscctrl_config.h
@@ -0,0 +1,483 @@
+/* Auto-generated config file hpl_oscctrl_config.h */
+#ifndef HPL_OSCCTRL_CONFIG_H
+#define HPL_OSCCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// External Multipurpose Crystal Oscillator Configuration
+// Indicates whether configuration for XOSC is enabled or not
+// enable_xosc
+#ifndef CONF_XOSC_CONFIG
+#define CONF_XOSC_CONFIG 0
+#endif
+
+// Frequency <400000-32000000>
+// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
+// xosc_frequency
+#ifndef CONF_XOSC_FREQUENCY
+#define CONF_XOSC_FREQUENCY 400000
+#endif
+
+// External Multipurpose Crystal Oscillator Control
+// Oscillator enable
+// Indicates whether External Multipurpose Crystal Oscillator is enabled or not
+// xosc_arch_enable
+#ifndef CONF_XOSC_ENABLE
+#define CONF_XOSC_ENABLE 0
+#endif
+
+// Start-Up Time
+// <0x0=>31us
+// <0x1=>61us
+// <0x2=>122us
+// <0x3=>244us
+// <0x4=>488us
+// <0x5=>977us
+// <0x6=>1953us
+// <0x7=>3906us
+// <0x8=>7813us
+// <0x9=>15625us
+// <0xA=>31250us
+// <0xB=>62500us
+// <0xC=>125000us
+// <0xD=>250000us
+// <0xE=>500000us
+// <0xF=>1000000us
+// xosc_arch_startup
+#ifndef CONF_XOSC_STARTUP
+#define CONF_XOSC_STARTUP 0x0
+#endif
+
+// Automatic Amplitude Gain Control
+// Indicates whether Automatic Amplitude Gain Control is enabled or not
+// xosc_arch_ampgc
+#ifndef CONF_XOSC_AMPGC
+#define CONF_XOSC_AMPGC 0
+#endif
+
+// External Multipurpose Crystal Oscillator Gain
+// <0x0=>2MHz
+// <0x1=>4MHz
+// <0x2=>8MHz
+// <0x3=>16MHz
+// <0x4=>30MHz
+// xosc_arch_gain
+#ifndef CONF_XOSC_GAIN
+#define CONF_XOSC_GAIN 0x0
+#endif
+
+// On Demand Control
+// Indicates whether On Demand Control is enabled or not
+// xosc_arch_ondemand
+#ifndef CONF_XOSC_ONDEMAND
+#define CONF_XOSC_ONDEMAND 1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// xosc_arch_runstdby
+#ifndef CONF_XOSC_RUNSTDBY
+#define CONF_XOSC_RUNSTDBY 0
+#endif
+
+// Clock Switch Back
+// Indicates whether Clock Switch Back is enabled or not
+// xosc_arch_swben
+#ifndef CONF_XOSC_SWBEN
+#define CONF_XOSC_SWBEN 0
+#endif
+
+// Clock Failure Detector
+// Indicates whether Clock Failure Detector is enabled or not
+// xosc_arch_cfden
+#ifndef CONF_XOSC_CFDEN
+#define CONF_XOSC_CFDEN 0
+#endif
+
+// Clock Failure Detector Event Out
+// Indicates whether Clock Failure Detector Event Out is enabled or not
+// xosc_arch_cfdeo
+#ifndef CONF_XOSC_CFDEO
+#define CONF_XOSC_CFDEO 0
+#endif
+
+// Crystal connected to XIN/XOUT Enable
+// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// xosc_arch_xtalen
+#ifndef CONF_XOSC_XTALEN
+#define CONF_XOSC_XTALEN 0
+#endif
+//
+//
+
+// 16MHz Internal Oscillator Configuration
+// Indicates whether configuration for OSC8M is enabled or not
+// enable_osc16m
+#ifndef CONF_OSC16M_CONFIG
+#define CONF_OSC16M_CONFIG 1
+#endif
+
+// 16MHz Internal Oscillator Control
+// Enable
+// Indicates whether 16MHz Internal Oscillator is enabled or not
+// osc16m_arch_enable
+#ifndef CONF_OSC16M_ENABLE
+#define CONF_OSC16M_ENABLE 1
+#endif
+
+// On Demand Control
+// Indicates whether On Demand Control is enabled or not
+// osc16m_arch_ondemand
+#ifndef CONF_OSC16M_ONDEMAND
+#define CONF_OSC16M_ONDEMAND 1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// osc16m_arch_runstdby
+#ifndef CONF_OSC16M_RUNSTDBY
+#define CONF_OSC16M_RUNSTDBY 0
+#endif
+
+// Oscillator Frequency Selection(Mhz)
+// 4
+// 8
+// 12
+// 16
+// This defines the oscillator frequency (Mhz)
+// osc16m_freq
+#ifndef CONF_OSC16M_FSEL
+#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val
+#endif
+
+// Oscillator Calibration Control
+// Indicates whether Oscillator Calibration is enabled or not
+// osc16m_arch_calib_enable
+#ifndef CONF_OSC16M_CALIB_ENABLE
+#define CONF_OSC16M_CALIB_ENABLE 0
+#endif
+
+// 4MHz Frequency Calibration <0x0-0x3F>
+// osc16m_arch_4m_fcal
+#ifndef CONF_OSC16M_FCAL
+#define CONF_OSC16M_4M_FCAL 0
+#endif
+
+// 4MHz Temperature Calibration <0x0-0x3F>
+// osc16m_arch_4m_tcal
+#ifndef CONF_OSC16M_TCAL
+#define CONF_OSC16M_4M_TCAL 0
+#endif
+
+// 8MHz Frequency Calibration <0x0-0x3F>
+// osc16m_arch_8m_fcal
+#ifndef CONF_OSC16M_FCAL
+#define CONF_OSC16M_8M_FCAL 0
+#endif
+
+// 8MHz Temperature Calibration <0x0-0x3F>
+// osc16m_arch_8m_tcal
+#ifndef CONF_OSC16M_TCAL
+#define CONF_OSC16M_8M_TCAL 0
+#endif
+
+// 12MHz Frequency Calibration <0x0-0x3F>
+// osc16m_arch_12m_fcal
+#ifndef CONF_OSC16M_FCAL
+#define CONF_OSC16M_12M_FCAL 0
+#endif
+
+// 12MHz Temperature Calibration <0x0-0x3F>
+// osc16m_arch_12m_tcal
+#ifndef CONF_OSC16M_TCAL
+#define CONF_OSC16M_12M_TCAL 0
+#endif
+
+// 16MHz Frequency Calibration <0x0-0x3F>
+// osc16m_arch_fcal
+#ifndef CONF_OSC16M_FCAL
+#define CONF_OSC16M_16M_FCAL 0
+#endif
+
+// 16MHz Temperature Calibration <0x0-0x3F>
+// osc16m_arch_16m_tcal
+#ifndef CONF_OSC16M_TCAL
+#define CONF_OSC16M_16M_TCAL 0
+#endif
+//
+//
+
+// DFLL Configuration
+// Indicates whether configuration for DFLL is enabled or not
+// enable_dfll48m
+#ifndef CONF_DFLL_CONFIG
+#define CONF_DFLL_CONFIG 0
+#endif
+
+// Reference Clock Source
+// Generic clock generator 0
+// Generic clock generator 1
+// Generic clock generator 2
+// Generic clock generator 3
+// Generic clock generator 4
+// Generic clock generator 5
+// Generic clock generator 6
+// Generic clock generator 7
+// Select the clock source.
+// dfll48m_ref_clock
+#ifndef CONF_DFLL_GCLK
+#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+// Digital Frequency Locked Loop Control
+// DFLL Enable
+// Indicates whether DFLL is enabled or not
+// dfll48m_arch_enable
+#ifndef CONF_DFLL_ENABLE
+#define CONF_DFLL_ENABLE 0
+#endif
+
+// Wait Lock
+// Indicates whether Wait Lock is enabled or not
+// dfll_arch_waitlock
+#ifndef CONF_DFLL_WAITLOCK
+#define CONF_DFLL_WAITLOCK 0
+#endif
+
+// Bypass Coarse Lock
+// Indicates whether Bypass Coarse Lock is enabled or not
+// dfll_arch_bplckc
+#ifndef CONF_DFLL_BPLCKC
+#define CONF_DFLL_BPLCKC 0
+#endif
+
+// Quick Lock Disable
+// Indicates whether Quick Lock Disable is enabled or not
+// dfll_arch_qldis
+#ifndef CONF_DFLL_QLDIS
+#define CONF_DFLL_QLDIS 0
+#endif
+
+// Chill Cycle Disable
+// Indicates whether Chill Cycle Disable is enabled or not
+// dfll_arch_ccdis
+#ifndef CONF_DFLL_CCDIS
+#define CONF_DFLL_CCDIS 0
+#endif
+
+// On Demand Control
+// Indicates whether On Demand Control is enabled or not
+// dfll_arch_ondemand
+#ifndef CONF_DFLL_ONDEMAND
+#define CONF_DFLL_ONDEMAND 1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// dfll_arch_runstdby
+#ifndef CONF_DFLL_RUNSTDBY
+#define CONF_DFLL_RUNSTDBY 0
+#endif
+
+// USB Clock Recovery Mode
+// Indicates whether USB Clock Recovery Mode is enabled or not
+// dfll_arch_usbcrm
+#ifndef CONF_DFLL_USBCRM
+#define CONF_DFLL_USBCRM 0
+#endif
+
+// Lose Lock After Wake
+// Indicates whether Lose Lock After Wake is enabled or not
+// dfll_arch_llaw
+#ifndef CONF_DFLL_LLAW
+#define CONF_DFLL_LLAW 0
+#endif
+
+// Stable DFLL Frequency
+// Indicates whether Stable DFLL Frequency is enabled or not
+// dfll_arch_stable
+#ifndef CONF_DFLL_STABLE
+#define CONF_DFLL_STABLE 0
+#endif
+
+// Operating Mode Selection
+// <0=>Open Loop Mode
+// <1=>Closed Loop Mode
+// dfll48m_mode
+#ifndef CONF_DFLL_MODE
+#define CONF_DFLL_MODE 0
+#endif
+
+// Coarse Maximum Step <0x0-0x1F>
+// dfll_arch_cstep
+#ifndef CONF_DFLL_CSTEP
+#define CONF_DFLL_CSTEP 1
+#endif
+
+// Fine Maximum Step <0x0-0x3FF>
+// dfll_arch_fstep
+#ifndef CONF_DFLL_FSTEP
+#define CONF_DFLL_FSTEP 1
+#endif
+
+// DFLL Multiply Factor <0x0-0xFFFF>
+// dfll48m_mul
+#ifndef CONF_DFLL_MUL
+#define CONF_DFLL_MUL 0
+#endif
+
+// DFLL Calibration Overwrite
+// Indicates whether Overwrite Calibration value of DFLL
+// dfll_arch_calibration
+#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
+#define CONF_DFLL_OVERWRITE_CALIBRATION 0
+#endif
+
+// Coarse Value <0x0-0x3F>
+// dfll_arch_coarse
+#ifndef CONF_DFLL_COARSE
+#define CONF_DFLL_COARSE (0x1f / 4)
+#endif
+
+// Fine Value <0x0-0x3FF>
+// dfll_arch_fine
+#ifndef CONF_DFLL_FINE
+#define CONF_DFLL_FINE (0x200)
+#endif
+
+//
+
+//
+
+//
+
+// DPLL Configuration
+// Indicates whether configuration for DPLL is enabled or not
+// enable_fdpll96m
+#ifndef CONF_DPLL_CONFIG
+#define CONF_DPLL_CONFIG 0
+#endif
+
+// Reference Clock Source
+// 32kHz External Crystal Oscillator (XOSC32K)
+// External Crystal Oscillator 0.4-32MHz (XOSC)
+// Generic clock generator 0
+// Generic clock generator 1
+// Generic clock generator 2
+// Generic clock generator 3
+// Generic clock generator 4
+// Generic clock generator 5
+// Generic clock generator 6
+// Generic clock generator 7
+// Select the clock source.
+// fdpll96m_ref_clock
+#ifndef CONF_DPLL_GCLK
+#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K
+
+#endif
+
+// Digital Phase Locked Loop Control
+// Enable
+// Indicates whether Digital Phase Locked Loop is enabled or not
+// fdpll96m_arch_enable
+#ifndef CONF_DPLL_ENABLE
+#define CONF_DPLL_ENABLE 0
+#endif
+
+// On Demand Control
+// Indicates whether On Demand Control is enabled or not
+// fdpll96m_arch_ondemand
+#ifndef CONF_DPLL_ONDEMAND
+#define CONF_DPLL_ONDEMAND 1
+#endif
+
+// Run in Standby
+// Indicates whether Run in Standby is enabled or not
+// fdpll96m_arch_runstdby
+#ifndef CONF_DPLL_RUNSTDBY
+#define CONF_DPLL_RUNSTDBY 0
+#endif
+
+// Loop Divider Ratio Fractional Part <0x0-0xF>
+// fdpll96m_ldrfrac
+#ifndef CONF_DPLL_LDRFRAC
+#define CONF_DPLL_LDRFRAC 0xd
+#endif
+
+// Loop Divider Ratio Integer Part <0x0-0xFFF>
+// fdpll96m_ldr
+#ifndef CONF_DPLL_LDR
+#define CONF_DPLL_LDR 0x5b7
+#endif
+
+// Clock Divider <0x0-0x3FF>
+// fdpll96m_clock_div
+#ifndef CONF_DPLL_DIV
+#define CONF_DPLL_DIV 0
+#endif
+
+// Lock Bypass
+// Indicates whether Lock Bypass is enabled or not
+// fdpll96m_arch_lbypass
+#ifndef CONF_DPLL_LBYPASS
+#define CONF_DPLL_LBYPASS 0
+#endif
+
+// Lock Time
+// <0=>No time-out, automatic lock
+// <4=>The Time-out if no lock within 8 ms
+// <5=>The Time-out if no lock within 9 ms
+// <6=>The Time-out if no lock within 10 ms
+// <7=>The Time-out if no lock within 11 ms
+// fdpll96m_arch_ltime
+#ifndef CONF_DPLL_LTIME
+#define CONF_DPLL_LTIME 0
+#endif
+
+// Reference Clock Selection
+// <0=>XOSC32K clock reference
+// <1=>XOSC clock reference
+// <2=>GCLK clock reference
+// fdpll96m_arch_refclk
+#ifndef CONF_DPLL_REFCLK
+#define CONF_DPLL_REFCLK 0
+#endif
+
+// Wake Up Fast
+// Indicates whether Wake Up Fast is enabled or not
+// fdpll96m_arch_wuf
+#ifndef CONF_DPLL_WUF
+#define CONF_DPLL_WUF 0
+#endif
+
+// Low-Power Enable
+// Indicates whether Low-Power Enable is enabled or not
+// fdpll96m_arch_lpen
+#ifndef CONF_DPLL_LPEN
+#define CONF_DPLL_LPEN 0
+#endif
+
+// Reference Clock Selection
+// <0=>Default filter mode
+// <1=>Low bandwidth filter
+// <2=>High bandwidth filter
+// <3=>High damping filter
+// fdpll96m_arch_filter
+#ifndef CONF_DPLL_FILTER
+#define CONF_DPLL_FILTER 0
+#endif
+
+// Output Clock Prescaler
+// 1
+// 2
+// 4
+// fdpll96m_presc
+#ifndef CONF_DPLL_PRESC
+#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val
+#endif
+//
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSCCTRL_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_port_config.h b/Smol Watch Project/My Project/Config/hpl_port_config.h
new file mode 100644
index 00000000..1efce33e
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_port_config.h
@@ -0,0 +1,284 @@
+/* Auto-generated config file hpl_port_config.h */
+#ifndef HPL_PORT_CONFIG_H
+#define HPL_PORT_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// PORT Input Event 0 configuration
+// enable_port_input_event_0
+#ifndef CONF_PORT_EVCTRL_PORT_0
+#define CONF_PORT_EVCTRL_PORT_0 0
+#endif
+
+// PORT Input Event 0 configuration on PORT A
+
+// PORTA Input Event 0 Enable
+// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
+// porta_input_event_enable_0
+#ifndef CONF_PORTA_EVCTRL_PORTEI_0
+#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
+#endif
+
+// PORTA Event 0 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port A on which the event action will be performed
+// porta_event_pin_identifier_0
+#ifndef CONF_PORTA_EVCTRL_PID_0
+#define CONF_PORTA_EVCTRL_PID_0 0x0
+#endif
+
+// PORTA Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT A will perform on event input 0
+// porta_event_action_0
+#ifndef CONF_PORTA_EVCTRL_EVACT_0
+#define CONF_PORTA_EVCTRL_EVACT_0 0
+#endif
+
+//
+// PORT Input Event 0 configuration on PORT B
+
+// PORTB Input Event 0 Enable
+// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
+// portb_input_event_enable_0
+#ifndef CONF_PORTB_EVCTRL_PORTEI_0
+#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
+#endif
+
+// PORTB Event 0 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port B on which the event action will be performed
+// portb_event_pin_identifier_0
+#ifndef CONF_PORTB_EVCTRL_PID_0
+#define CONF_PORTB_EVCTRL_PID_0 0x0
+#endif
+
+// PORTB Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT B will perform on event input 0
+// portb_event_action_0
+#ifndef CONF_PORTB_EVCTRL_EVACT_0
+#define CONF_PORTB_EVCTRL_EVACT_0 0
+#endif
+
+//
+
+//
+
+// PORT Input Event 1 configuration
+// enable_port_input_event_1
+#ifndef CONF_PORT_EVCTRL_PORT_1
+#define CONF_PORT_EVCTRL_PORT_1 0
+#endif
+
+// PORT Input Event 1 configuration on PORT A
+
+// PORTA Input Event 1 Enable
+// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
+// porta_input_event_enable_1
+#ifndef CONF_PORTA_EVCTRL_PORTEI_1
+#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
+#endif
+
+// PORTA Event 1 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port A on which the event action will be performed
+// porta_event_pin_identifier_1
+#ifndef CONF_PORTA_EVCTRL_PID_1
+#define CONF_PORTA_EVCTRL_PID_1 0x0
+#endif
+
+// PORTA Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT A will perform on event input 1
+// porta_event_action_1
+#ifndef CONF_PORTA_EVCTRL_EVACT_1
+#define CONF_PORTA_EVCTRL_EVACT_1 0
+#endif
+
+//
+// PORT Input Event 1 configuration on PORT B
+
+// PORTB Input Event 1 Enable
+// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
+// portb_input_event_enable_1
+#ifndef CONF_PORTB_EVCTRL_PORTEI_1
+#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
+#endif
+
+// PORTB Event 1 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port B on which the event action will be performed
+// portb_event_pin_identifier_1
+#ifndef CONF_PORTB_EVCTRL_PID_1
+#define CONF_PORTB_EVCTRL_PID_1 0x0
+#endif
+
+// PORTB Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT B will perform on event input 1
+// portb_event_action_1
+#ifndef CONF_PORTB_EVCTRL_EVACT_1
+#define CONF_PORTB_EVCTRL_EVACT_1 0
+#endif
+
+//
+
+//
+
+// PORT Input Event 2 configuration
+// enable_port_input_event_2
+#ifndef CONF_PORT_EVCTRL_PORT_2
+#define CONF_PORT_EVCTRL_PORT_2 0
+#endif
+
+// PORT Input Event 2 configuration on PORT A
+
+// PORTA Input Event 2 Enable
+// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
+// porta_input_event_enable_2
+#ifndef CONF_PORTA_EVCTRL_PORTEI_2
+#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
+#endif
+
+// PORTA Event 2 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port A on which the event action will be performed
+// porta_event_pin_identifier_2
+#ifndef CONF_PORTA_EVCTRL_PID_2
+#define CONF_PORTA_EVCTRL_PID_2 0x0
+#endif
+
+// PORTA Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT A will perform on event input 2
+// porta_event_action_2
+#ifndef CONF_PORTA_EVCTRL_EVACT_2
+#define CONF_PORTA_EVCTRL_EVACT_2 0
+#endif
+
+//
+// PORT Input Event 2 configuration on PORT B
+
+// PORTB Input Event 2 Enable
+// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
+// portb_input_event_enable_2
+#ifndef CONF_PORTB_EVCTRL_PORTEI_2
+#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
+#endif
+
+// PORTB Event 2 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port B on which the event action will be performed
+// portb_event_pin_identifier_2
+#ifndef CONF_PORTB_EVCTRL_PID_2
+#define CONF_PORTB_EVCTRL_PID_2 0x0
+#endif
+
+// PORTB Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT B will perform on event input 2
+// portb_event_action_2
+#ifndef CONF_PORTB_EVCTRL_EVACT_2
+#define CONF_PORTB_EVCTRL_EVACT_2 0
+#endif
+
+//
+
+//
+
+// PORT Input Event 3 configuration
+// enable_port_input_event_3
+#ifndef CONF_PORT_EVCTRL_PORT_3
+#define CONF_PORT_EVCTRL_PORT_3 0
+#endif
+
+// PORT Input Event 3 configuration on PORT A
+
+// PORTA Input Event 3 Enable
+// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
+// porta_input_event_enable_3
+#ifndef CONF_PORTA_EVCTRL_PORTEI_3
+#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
+#endif
+
+// PORTA Event 3 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port A on which the event action will be performed
+// porta_event_pin_identifier_3
+#ifndef CONF_PORTA_EVCTRL_PID_3
+#define CONF_PORTA_EVCTRL_PID_3 0x0
+#endif
+
+// PORTA Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT A will perform on event input 3
+// porta_event_action_3
+#ifndef CONF_PORTA_EVCTRL_EVACT_3
+#define CONF_PORTA_EVCTRL_EVACT_3 0
+#endif
+
+//
+// PORT Input Event 3 configuration on PORT B
+
+// PORTB Input Event 3 Enable
+// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
+// portb_input_event_enable_3
+#ifndef CONF_PORTB_EVCTRL_PORTEI_3
+#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
+#endif
+
+// PORTB Event 3 Pin Identifier <0x00-0x1F>
+// These bits define the I/O pin from port B on which the event action will be performed
+// portb_event_pin_identifier_3
+#ifndef CONF_PORTB_EVCTRL_PID_3
+#define CONF_PORTB_EVCTRL_PID_3 0x0
+#endif
+
+// PORTB Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// These bits define the event action the PORT B will perform on event input 3
+// portb_event_action_3
+#ifndef CONF_PORTB_EVCTRL_EVACT_3
+#define CONF_PORTB_EVCTRL_EVACT_3 0
+#endif
+
+//
+
+//
+
+#define CONF_PORTA_EVCTRL \
+ (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
+ | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
+ | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
+ | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
+ | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
+ | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
+#define CONF_PORTB_EVCTRL \
+ (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
+ | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
+ | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
+ | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
+ | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
+ | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
+
+// <<< end of configuration section >>>
+
+#endif // HPL_PORT_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_rtc_config.h b/Smol Watch Project/My Project/Config/hpl_rtc_config.h
new file mode 100644
index 00000000..174f77a9
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_rtc_config.h
@@ -0,0 +1,318 @@
+/* Auto-generated config file hpl_rtc_config.h */
+#ifndef HPL_RTC_CONFIG_H
+#define HPL_RTC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Basic settings
+
+#ifndef CONF_RTC_ENABLE
+#define CONF_RTC_ENABLE 1
+#endif
+
+// Force reset RTC on initialization
+// Force RTC to reset on initialization.
+// Note that the previous power down data in RTC is lost if it's enabled.
+// rtc_arch_init_reset
+#ifndef CONF_RTC_INIT_RESET
+#define CONF_RTC_INIT_RESET 1
+#endif
+
+// Prescaler configuration
+// <0x0=>OFF(Peripheral clock divided by 1)
+// <0x1=>Peripheral clock divided by 1
+// <0x2=>Peripheral clock divided by 2
+// <0x3=>Peripheral clock divided by 4
+// <0x4=>Peripheral clock divided by 8
+// <0x5=>Peripheral clock divided by 16
+// <0x6=>Peripheral clock divided by 32
+// <0x7=>Peripheral clock divided by 64
+// <0x8=>Peripheral clock divided by 128
+// <0x9=>Peripheral clock divided by 256
+// <0xA=>Peripheral clock divided by 512
+// <0xB=>Peripheral clock divided by 1024
+// These bits define the RTC clock relative to the peripheral clock
+// rtc_arch_prescaler
+#ifndef CONF_RTC_PRESCALER
+
+#define CONF_RTC_PRESCALER 0xb
+
+#endif
+
+#ifndef CONF_RTC_COMP_VAL
+
+#define CONF_RTC_COMP_VAL 0
+
+#endif
+
+// RTC Tamper Input 0 settings
+// tamper_input_0_settings
+#ifndef CONF_TAMPER_INPUT_0_SETTINGS
+#define CONF_TAMPER_INPUT_0_SETTINGS 0
+#endif
+
+// Tamper Level Settings
+// Indicates Tamper input 0 level
+// tamper_level_0
+#ifndef CONF_RTC_TAMP_LVL_0
+#define CONF_RTC_TAMP_LVL_0 0
+#endif
+
+// RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// These bits define the RTC Tamper Input Action to be performed
+// rtc_tamper_input_action_0
+#ifndef CONF_RTC_TAMPER_INACT_0
+#define CONF_RTC_TAMPER_INACT_0 0
+#endif
+
+// Debounce Enable for Tamper Input
+// Indicates Debounce should be enabled for Tamper input 0
+// tamper_debounce_enable_0
+#ifndef CONF_RTC_TAMP_DEBNC_0
+#define CONF_RTC_TAMP_DEBNC_0 0
+#endif
+
+//
+
+// RTC Tamper Input 1 settings
+// tamper_input_1_settings
+#ifndef CONF_TAMPER_INPUT_1_SETTINGS
+#define CONF_TAMPER_INPUT_1_SETTINGS 0
+#endif
+
+// Tamper Level Settings
+// Indicates Tamper input 1 level
+// tamper_level_1
+#ifndef CONF_RTC_TAMP_LVL_1
+#define CONF_RTC_TAMP_LVL_1 0
+#endif
+
+// RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// These bits define the RTC Tamper Input Action to be performed
+// rtc_tamper_input_action_1
+#ifndef CONF_RTC_TAMPER_INACT_1
+#define CONF_RTC_TAMPER_INACT_1 0
+#endif
+
+// Debounce Enable for Tamper Input
+// Indicates Debounce should be enabled for Tamper input 1
+// tamper_debounce_enable_1
+#ifndef CONF_RTC_TAMP_DEBNC_1
+#define CONF_RTC_TAMP_DEBNC_1 0
+#endif
+
+//
+
+// RTC Tamper Input 2 settings
+// tamper_input_2_settings
+#ifndef CONF_TAMPER_INPUT_2_SETTINGS
+#define CONF_TAMPER_INPUT_2_SETTINGS 0
+#endif
+
+// Tamper Level Settings
+// Indicates Tamper input 2 level
+// tamper_level_2
+#ifndef CONF_RTC_TAMP_LVL_2
+#define CONF_RTC_TAMP_LVL_2 0
+#endif
+
+// RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// These bits define the RTC Tamper Input Action to be performed
+// rtc_tamper_input_action_2
+#ifndef CONF_RTC_TAMPER_INACT_2
+#define CONF_RTC_TAMPER_INACT_2 0
+#endif
+
+// Debounce Enable for Tamper Input
+// Indicates Debounce should be enabled for Tamper input 2
+// tamper_debounce_enable_2
+#ifndef CONF_RTC_TAMP_DEBNC_2
+#define CONF_RTC_TAMP_DEBNC_2 0
+#endif
+
+//
+
+// RTC Tamper Input 3 settings
+// tamper_input_3_settings
+#ifndef CONF_TAMPER_INPUT_3_SETTINGS
+#define CONF_TAMPER_INPUT_3_SETTINGS 0
+#endif
+
+// Tamper Level Settings
+// Indicates Tamper input 3 level
+// tamper_level_3
+#ifndef CONF_RTC_TAMP_LVL_3
+#define CONF_RTC_TAMP_LVL_3 0
+#endif
+
+// RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// These bits define the RTC Tamper Input Action to be performed
+// rtc_tamper_input_action_3
+#ifndef CONF_RTC_TAMPER_INACT_3
+#define CONF_RTC_TAMPER_INACT_3 0
+#endif
+
+// Debounce Enable for Tamper Input
+// Indicates Debounce should be enabled for Tamper input 3
+// tamper_debounce_enable_3
+#ifndef CONF_RTC_TAMP_DEBNC_3
+#define CONF_RTC_TAMP_DEBNC_3 0
+#endif
+
+//
+
+// RTC Tamper Input 4 settings
+// tamper_input_4_settings
+#ifndef CONF_TAMPER_INPUT_4_SETTINGS
+#define CONF_TAMPER_INPUT_4_SETTINGS 0
+#endif
+
+// Tamper Level Settings
+// Indicates Tamper input 4 level
+// tamper_level_4
+#ifndef CONF_RTC_TAMP_LVL_4
+#define CONF_RTC_TAMP_LVL_4 0
+#endif
+
+// RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// These bits define the RTC Tamper Input Action to be performed
+// rtc_tamper_input_action_4
+#ifndef CONF_RTC_TAMPER_INACT_4
+#define CONF_RTC_TAMPER_INACT_4 0
+#endif
+
+// Debounce Enable for Tamper Input
+// Indicates Debounce should be enabled for Tamper input 4
+// tamper_debounce_enable_4
+#ifndef CONF_RTC_TAMP_DEBNC_4
+#define CONF_RTC_TAMP_DEBNC_4 0
+#endif
+
+//
+
+// RTC Tamper Active Layer Frequency Prescalar
+// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2
+// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4
+// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8
+// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16
+// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32
+// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64
+// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128
+// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256
+// These bits define the RTC Tamper Active Layer Frequecny Prescalar
+// rtc_tamper_active_layer_frequency_prescalar
+#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES
+#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0
+#endif
+
+// RTC Tamper Debounce Frequency Prescalar
+// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2
+// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4
+// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8
+// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16
+// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32
+// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64
+// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128
+// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256
+// These bits define the RTC Debounce Frequency Prescalar
+// rtc_tamper_debounce_frequency_prescalar
+#ifndef CONF_RTC_TAMP_DEBF_PRES
+#define CONF_RTC_TAMP_DEBF_PRES 0
+#endif
+
+// Event control
+// rtc_event_control
+#ifndef CONF_RTC_EVENT_CONTROL_ENABLE
+#define CONF_RTC_EVENT_CONTROL_ENABLE 0
+#endif
+
+// Periodic Interval 0 Event Output
+// This bit indicates whether Periodic interval 0 event is enabled and will be generated
+// rtc_pereo0
+#ifndef CONF_RTC_PEREO0
+#define CONF_RTC_PEREO0 0
+#endif
+// Periodic Interval 1 Event Output
+// This bit indicates whether Periodic interval 1 event is enabled and will be generated
+// rtc_pereo1
+#ifndef CONF_RTC_PEREO1
+#define CONF_RTC_PEREO1 0
+#endif
+// Periodic Interval 2 Event Output
+// This bit indicates whether Periodic interval 2 event is enabled and will be generated
+// rtc_pereo2
+#ifndef CONF_RTC_PEREO2
+#define CONF_RTC_PEREO2 0
+#endif
+// Periodic Interval 3 Event Output
+// This bit indicates whether Periodic interval 3 event is enabled and will be generated
+// rtc_pereo3
+#ifndef CONF_RTC_PEREO3
+#define CONF_RTC_PEREO3 0
+#endif
+// Periodic Interval 4 Event Output
+// This bit indicates whether Periodic interval 4 event is enabled and will be generated
+// rtc_pereo4
+#ifndef CONF_RTC_PEREO4
+#define CONF_RTC_PEREO4 0
+#endif
+// Periodic Interval 5 Event Output
+// This bit indicates whether Periodic interval 5 event is enabled and will be generated
+// rtc_pereo5
+#ifndef CONF_RTC_PEREO5
+#define CONF_RTC_PEREO5 0
+#endif
+// Periodic Interval 6 Event Output
+// This bit indicates whether Periodic interval 6 event is enabled and will be generated
+// rtc_pereo6
+#ifndef CONF_RTC_PEREO6
+#define CONF_RTC_PEREO6 0
+#endif
+// Periodic Interval 7 Event Output
+// This bit indicates whether Periodic interval 7 event is enabled and will be generated
+// rtc_pereo7
+#ifndef CONF_RTC_PEREO7
+#define CONF_RTC_PEREO7 0
+#endif
+
+// Compare 0 Event Output
+// This bit indicates whether Compare O event is enabled and will be generated
+// rtc_cmpeo0
+#ifndef CONF_RTC_COMPE0
+#define CONF_RTC_COMPE0 0
+#endif
+
+// Overflow Event Output
+// This bit indicates whether Overflow event is enabled and will be generated
+// rtc_ovfeo
+#ifndef CONF_RTC_OVFEO
+#define CONF_RTC_OVFEO 0
+#endif
+
+//
+
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_RTC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_sercom_config.h b/Smol Watch Project/My Project/Config/hpl_sercom_config.h
new file mode 100644
index 00000000..ad16e642
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_sercom_config.h
@@ -0,0 +1,144 @@
+/* Auto-generated config file hpl_sercom_config.h */
+#ifndef HPL_SERCOM_CONFIG_H
+#define HPL_SERCOM_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include
+
+#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+#endif
+
+#ifndef CONF_SERCOM_1_I2CM_ENABLE
+#define CONF_SERCOM_1_I2CM_ENABLE 1
+#endif
+
+// Basic
+
+// I2C Bus clock speed (Hz) <1-400000>
+// I2C Bus clock (SCL) speed measured in Hz
+// i2c_master_baud_rate
+#ifndef CONF_SERCOM_1_I2CM_BAUD
+#define CONF_SERCOM_1_I2CM_BAUD 100000
+#endif
+
+//
+
+// Advanced
+// i2c_master_advanced
+#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG
+#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0
+#endif
+
+// TRise (ns) <0-300>
+// Determined by the bus impedance, check electric characteristics in the datasheet
+// Standard Fast Mode: typical 215ns, max 300ns
+// Fast Mode +: typical 60ns, max 100ns
+// High Speed Mode: typical 20ns, max 40ns
+// i2c_master_arch_trise
+
+#ifndef CONF_SERCOM_1_I2CM_TRISE
+#define CONF_SERCOM_1_I2CM_TRISE 215
+#endif
+
+// Master SCL Low Extended Time-Out (MEXTTOEN)
+// This enables the master SCL low extend time-out
+// i2c_master_arch_mexttoen
+#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN
+#define CONF_SERCOM_1_I2CM_MEXTTOEN 0
+#endif
+
+// Slave SCL Low Extend Time-Out (SEXTTOEN)
+// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
+// i2c_master_arch_sexttoen
+#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN
+#define CONF_SERCOM_1_I2CM_SEXTTOEN 0
+#endif
+
+// SCL Low Time-Out (LOWTOUT)
+// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
+// i2c_master_arch_lowtout
+#ifndef CONF_SERCOM_1_I2CM_LOWTOUT
+#define CONF_SERCOM_1_I2CM_LOWTOUT 0
+#endif
+
+// Inactive Time-Out (INACTOUT)
+// <0x0=>Disabled
+// <0x1=>5-6 SCL cycle time-out(50-60us)
+// <0x2=>10-11 SCL cycle time-out(100-110us)
+// <0x3=>20-21 SCL cycle time-out(200-210us)
+// Defines if inactivity time-out should be enabled, and how long the time-out should be
+// i2c_master_arch_inactout
+#ifndef CONF_SERCOM_1_I2CM_INACTOUT
+#define CONF_SERCOM_1_I2CM_INACTOUT 0x0
+#endif
+
+// SDA Hold Time (SDAHOLD)
+// <0=>Disabled
+// <1=>50-100ns hold time
+// <2=>300-600ns hold time
+// <3=>400-800ns hold time
+// Defines the SDA hold time with respect to the negative edge of SCL
+// i2c_master_arch_sdahold
+#ifndef CONF_SERCOM_1_I2CM_SDAHOLD
+#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2
+#endif
+
+// Run in stand-by
+// Determine if the module shall run in standby sleep mode
+// i2c_master_arch_runstdby
+#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY
+#define CONF_SERCOM_1_I2CM_RUNSTDBY 0
+#endif
+
+// Debug Stop Mode
+// Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// i2c_master_arch_dbgstop
+#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE
+#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0
+#endif
+
+//
+
+#ifndef CONF_SERCOM_1_I2CM_SPEED
+#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
+#endif
+#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300
+#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
+#undef CONF_SERCOM_1_I2CM_TRISE
+#define CONF_SERCOM_1_I2CM_TRISE 215U
+#endif
+
+// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
+// BAUD + BAUDLOW = --------------------------------------------------------------------
+// i2c_scl_freq
+// BAUD: register value low [7:0]
+// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
+#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \
+ (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \
+ - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \
+ / 1000U)) \
+ * 10U \
+ + 5U) \
+ / (CONF_SERCOM_1_I2CM_BAUD * 10U))
+#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE
+#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2)
+#warning Requested I2C baudrate too low, please check
+#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF
+#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1
+#warning Requested I2C baudrate too high, please check
+#define CONF_SERCOM_1_I2CM_BAUD_RATE 1
+#else
+#define CONF_SERCOM_1_I2CM_BAUD_RATE \
+ ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \
+ ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
+ : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2))
+#endif
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SERCOM_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_slcd_config.h b/Smol Watch Project/My Project/Config/hpl_slcd_config.h
new file mode 100644
index 00000000..e3bb1bd5
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_slcd_config.h
@@ -0,0 +1,2744 @@
+/* Auto-generated config file hpl_slcd_config.h */
+#ifndef HPL_SLCD_CONFIG_H
+#define HPL_SLCD_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include
+#include
+
+// Standard configuration
+
+// Number of COM Lines
+// Number of COM Lines
+// <0=>1
+// <1=>2
+// <2=>3
+// <3=>4
+// <4=>6
+// <5=>8
+// slcd_arch_com_num
+#ifndef CONF_SLCD_COM_NUM
+#define CONF_SLCD_COM_NUM 2
+#endif
+
+// Number of Segment Lines <1-44>
+// Number of Segment Lines
+// slcd_arch_seg_num
+#ifndef CONF_SLCD_SEG_NUM
+#define CONF_SLCD_SEG_NUM 24
+#endif
+
+#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_SIXTH_Val && CONF_SLCD_SEG_NUM > 42
+#warning Segment number should less than or equals to 42
+#endif
+#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_EIGHT_Val && CONF_SLCD_SEG_NUM > 40
+#warning Segment number should less than or equals to 40
+#endif
+
+// Bias
+// Bias Settting
+// <0=>STATIC
+// <1=>HALF
+// <2=>THIRD
+// <3=>FOURTH
+// slcd_arch_bias
+#ifndef CONF_SLCD_BIAS
+#define CONF_SLCD_BIAS 2
+#endif
+
+#if CONF_SLCD_COM_NUM == 0 && CONF_SLCD_BIAS != 0
+#warning Recommended Bias for 1 common terminal is STATIC
+#elif CONF_SLCD_COM_NUM == 1 && CONF_SLCD_BIAS != 1
+#warning Recommended Bias for 2 Common Terminals is HALF
+#elif CONF_SLCD_COM_NUM <= 4 && CONF_SLCD_BIAS != 2
+#warning Recommended Bias for 3/4/6 Common Terminals is THIRD
+#elif CONF_SLCD_COM_NUM == 5 && CONF_SLCD_BIAS != 3
+#warning Recommended Bias for 8 Common Terminals is FOURTH
+#endif
+
+// Bias Buffer Enable
+// Enable Bias Buffer
+// slcd_arch_bben
+#ifndef CONF_SLCD_BBEN
+#define CONF_SLCD_BBEN 1
+#endif
+
+// Bias Buffer Enable Duration <1-16>
+// Configure the enable duration of the bias buffer, unit is cycle of SLCD OSC clock source
+// slcd_arch_bbd
+#ifndef CONF_SLCD_BBD
+#define CONF_SLCD_BBD 2
+#endif
+
+// Clock Prescaler
+// Setting for LCD frame frequency
+// <0=>16
+// <1=>32
+// <2=>64
+// <3=>128
+// slcd_arch_presc
+#ifndef CONF_SLCD_PRESC
+#define CONF_SLCD_PRESC 2
+#endif
+
+// Clock Divider
+// Setting for LCD frame frequency
+// <0=>1
+// <1=>2
+// <2=>3
+// <3=>4
+// <4=>5
+// <5=>6
+// <6=>7
+// <7=>8
+// slcd_arch_ckdiv
+#ifndef CONF_SLCD_CKDIV
+#define CONF_SLCD_CKDIV 3
+#endif
+
+/* TODO add frame frequency check */
+
+// Reference Refresh Frequency
+// Setting for Reference Refresh Frequency
+// <0=>2kHz
+// <1=>1kHz
+// <2=>500Hz
+// <3=>250Hz
+// <4=>125Hz
+// <5=>62.5Hz
+// slcd_arch_rrf
+#ifndef CONF_SLCD_RRF
+#define CONF_SLCD_RRF 0
+#endif
+
+// Power Refresh Frequency
+// Setting for Charge pump Refresh Frequency
+// <0=>2kHz
+// <1=>1kHz
+// <2=>500Hz
+// <3=>250Hz
+// slcd_arch_prf
+#ifndef CONF_SLCD_PRF
+#define CONF_SLCD_PRF 3
+#endif
+
+// External VLCD
+// Setting for how VLCD is generated
+// slcd_arch_xvlcd
+#ifndef CONF_SLCD_XVLCD
+#define CONF_SLCD_XVLCD 0
+#endif
+
+// Waveform Mode
+// Setting for Waveform Mode
+// <0=>Low Power Waveform(frame-inversion)
+// <1=>Standard Waveform Mode(bit-inversion)
+// slcd_arch_wmod
+#ifndef CONF_SLCD_WMOD
+#define CONF_SLCD_WMOD 0
+#endif
+
+// Contrast Adjustment
+// The contrast of the LCD is determined by the value of VLCD voltage.
+// The higher the VLCD voltage, the higher is the contrast.
+// The software contrast adjustment is only possible in internal supply mode.
+// <0=>2.5056V
+// <1=>2.5731V
+// <2=>2.6379V
+// <3=>2.7054V
+// <4=>2.7729V
+// <5=>2.8404V
+// <6=>2.9052V
+// <7=>2.9727V
+// <8=>3.0402V
+// <9=>3.1077V
+// <10=>3.1725V
+// <11=>3.24V
+// <12=>3.3075V
+// <13=>3.375V
+// <14=>3.4398V
+// <15=>3.5073V
+// slcd_arch_contrast_adjust
+#ifndef CONF_SLCD_CONTRAST_ADJUST
+#define CONF_SLCD_CONTRAST_ADJUST 14
+#endif
+
+//
+
+// Advanced configuration
+// slcd_arch_advanced_settings
+#ifndef CONF_SLCD_ADVANCED_SETTINGS
+#define CONF_SLCD_ADVANCED_SETTINGS 0
+#endif
+
+// Run in standby
+// Indicates whether the SLCD will continue running in standby sleep mode or not
+// slcd_arch_runstdby
+#ifndef CONF_SLCD_RUNSTDBY
+#define CONF_SLCD_RUNSTDBY 0
+#endif
+
+//
+
+#if SLCD_FRAME_FREQUENCY < 30 || SLCD_FRAME_FREQUENCY > 100
+#warning The optimal frame frequency should be in range from 30Hz up to 100Hz to avoid flickering and ghosting effect.
+#endif
+
+#define SLCD_FC_MAX_MS (((0x1F + 1) * 8) * (1000 / SLCD_FRAME_FREQUENCY))
+#define SLCD_FC_MIN_MS (1000 / SLCD_FRAME_FREQUENCY)
+#define SLCD_FC_BYPASS_MAX_MS ((0x1F + 1) * (1000 / SLCD_FRAME_FREQUENCY))
+
+// Character Mapping Setting
+// slcd_arch_cm_setting
+#ifndef CONF_SLCD_CM_ENABLE
+#define CONF_SLCD_CM_ENABLE 0
+#endif
+
+// 7 Segment Character Mapping Setting
+// slcd_arch_cm_7segs_setting
+#ifndef CONF_SLCD_CM_7SEGS_SETTING
+#define CONF_SLCD_CM_7SEGS_SETTING 0
+#endif
+
+// Segment 0 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_7segs_0_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_0_SETTING
+#define CONF_SLCD_CM_7SEGS_0_SETTING 0
+#endif
+// Segment 1 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_7segs_1_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_1_SETTING
+#define CONF_SLCD_CM_7SEGS_1_SETTING 1
+#endif
+// Segment 2 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_7segs_2_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_2_SETTING
+#define CONF_SLCD_CM_7SEGS_2_SETTING 2
+#endif
+// Segment 3 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_7segs_3_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_3_SETTING
+#define CONF_SLCD_CM_7SEGS_3_SETTING 3
+#endif
+// Segment 4 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_7segs_4_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_4_SETTING
+#define CONF_SLCD_CM_7SEGS_4_SETTING 4
+#endif
+// Segment 5 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_7segs_5_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_5_SETTING
+#define CONF_SLCD_CM_7SEGS_5_SETTING 5
+#endif
+// Segment 6 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_7segs_6_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_6_SETTING
+#define CONF_SLCD_CM_7SEGS_6_SETTING 6
+#endif
+
+//
+
+// 14 Segment Character Mapping Setting
+// slcd_arch_cm_14segs_enable
+#ifndef CONF_SLCD_CM_14SEGS_ENABLE
+#define CONF_SLCD_CM_14SEGS_ENABLE 0
+#endif
+
+// Segments 0 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_0_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_0_SETTING
+#define CONF_SLCD_CM_14SEGS_0_SETTING 0
+#endif
+
+// Segments 1 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_1_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_1_SETTING
+#define CONF_SLCD_CM_14SEGS_1_SETTING 1
+#endif
+
+// Segments 2 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_2_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_2_SETTING
+#define CONF_SLCD_CM_14SEGS_2_SETTING 2
+#endif
+
+// Segments 3 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_3_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_3_SETTING
+#define CONF_SLCD_CM_14SEGS_3_SETTING 3
+#endif
+
+// Segments 4 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_4_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_4_SETTING
+#define CONF_SLCD_CM_14SEGS_4_SETTING 4
+#endif
+
+// Segments 5 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_5_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_5_SETTING
+#define CONF_SLCD_CM_14SEGS_5_SETTING 5
+#endif
+
+// Segments 6 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_6_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_6_SETTING
+#define CONF_SLCD_CM_14SEGS_6_SETTING 6
+#endif
+
+// Segments 7 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_7_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_7_SETTING
+#define CONF_SLCD_CM_14SEGS_7_SETTING 7
+#endif
+
+// Segments 8 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_8_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_8_SETTING
+#define CONF_SLCD_CM_14SEGS_8_SETTING 8
+#endif
+
+// Segments 9 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_9_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_9_SETTING
+#define CONF_SLCD_CM_14SEGS_9_SETTING 9
+#endif
+
+// Segments 10 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_10_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_10_SETTING
+#define CONF_SLCD_CM_14SEGS_10_SETTING 10
+#endif
+
+// Segments 11 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_11_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_11_SETTING
+#define CONF_SLCD_CM_14SEGS_11_SETTING 11
+#endif
+
+// Segments 12 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_12_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_12_SETTING
+#define CONF_SLCD_CM_14SEGS_12_SETTING 12
+#endif
+
+// Segments 13 Setting
+// Segment index for the character mapping area
+// Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// slcd_arch_cm_14segs_13_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_13_SETTING
+#define CONF_SLCD_CM_14SEGS_13_SETTING 13
+#endif
+
+//
+
+// Character 0 Mapping Setting
+// slcd_arch_char0_setting
+#ifndef CONF_SLCD_CHAR0_ENABLE_SETTING
+#define CONF_SLCD_CHAR0_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character0 COM begin index
+// slcd_arch_char0_com_idx
+#ifndef CONF_SLCD_CHAR0_COM_IDX
+#define CONF_SLCD_CHAR0_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character0 Segment begin index
+// slcd_arch_char0_seg_idx
+#ifndef CONF_SLCD_CHAR0_SEG_IDX
+#define CONF_SLCD_CHAR0_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character0 mapping
+// slcd_arch_char0_seg_num
+#ifndef CONF_SLCD_CHAR0_SEG_NUM
+#define CONF_SLCD_CHAR0_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character0
+// slcd_arch_char0_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR0_MAPPING_TABLE
+#define CONF_SLCD_CHAR0_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 1 Mapping Setting
+// slcd_arch_char1_setting
+#ifndef CONF_SLCD_CHAR1_ENABLE_SETTING
+#define CONF_SLCD_CHAR1_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character1 COM begin index
+// slcd_arch_char1_com_idx
+#ifndef CONF_SLCD_CHAR1_COM_IDX
+#define CONF_SLCD_CHAR1_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character1 Segment begin index
+// slcd_arch_char1_seg_idx
+#ifndef CONF_SLCD_CHAR1_SEG_IDX
+#define CONF_SLCD_CHAR1_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character1 mapping
+// slcd_arch_char1_seg_num
+#ifndef CONF_SLCD_CHAR1_SEG_NUM
+#define CONF_SLCD_CHAR1_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character1
+// slcd_arch_char1_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR1_MAPPING_TABLE
+#define CONF_SLCD_CHAR1_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 2 Mapping Setting
+// slcd_arch_char2_setting
+#ifndef CONF_SLCD_CHAR2_ENABLE_SETTING
+#define CONF_SLCD_CHAR2_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character2 COM begin index
+// slcd_arch_char2_com_idx
+#ifndef CONF_SLCD_CHAR2_COM_IDX
+#define CONF_SLCD_CHAR2_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character2 Segment begin index
+// slcd_arch_char2_seg_idx
+#ifndef CONF_SLCD_CHAR2_SEG_IDX
+#define CONF_SLCD_CHAR2_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character2 mapping
+// slcd_arch_char2_seg_num
+#ifndef CONF_SLCD_CHAR2_SEG_NUM
+#define CONF_SLCD_CHAR2_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character2
+// slcd_arch_char2_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR2_MAPPING_TABLE
+#define CONF_SLCD_CHAR2_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 3 Mapping Setting
+// slcd_arch_char3_setting
+#ifndef CONF_SLCD_CHAR3_ENABLE_SETTING
+#define CONF_SLCD_CHAR3_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character3 COM begin index
+// slcd_arch_char3_com_idx
+#ifndef CONF_SLCD_CHAR3_COM_IDX
+#define CONF_SLCD_CHAR3_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character3 Segment begin index
+// slcd_arch_char3_seg_idx
+#ifndef CONF_SLCD_CHAR3_SEG_IDX
+#define CONF_SLCD_CHAR3_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character3 mapping
+// slcd_arch_char3_seg_num
+#ifndef CONF_SLCD_CHAR3_SEG_NUM
+#define CONF_SLCD_CHAR3_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character3
+// slcd_arch_char3_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR3_MAPPING_TABLE
+#define CONF_SLCD_CHAR3_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 4 Mapping Setting
+// slcd_arch_char4_setting
+#ifndef CONF_SLCD_CHAR4_ENABLE_SETTING
+#define CONF_SLCD_CHAR4_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character4 COM begin index
+// slcd_arch_char4_com_idx
+#ifndef CONF_SLCD_CHAR4_COM_IDX
+#define CONF_SLCD_CHAR4_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character4 Segment begin index
+// slcd_arch_char4_seg_idx
+#ifndef CONF_SLCD_CHAR4_SEG_IDX
+#define CONF_SLCD_CHAR4_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character4 mapping
+// slcd_arch_char4_seg_num
+#ifndef CONF_SLCD_CHAR4_SEG_NUM
+#define CONF_SLCD_CHAR4_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character4
+// slcd_arch_char4_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR4_MAPPING_TABLE
+#define CONF_SLCD_CHAR4_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 5 Mapping Setting
+// slcd_arch_char5_setting
+#ifndef CONF_SLCD_CHAR5_ENABLE_SETTING
+#define CONF_SLCD_CHAR5_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character5 COM begin index
+// slcd_arch_char5_com_idx
+#ifndef CONF_SLCD_CHAR5_COM_IDX
+#define CONF_SLCD_CHAR5_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character5 Segment begin index
+// slcd_arch_char5_seg_idx
+#ifndef CONF_SLCD_CHAR5_SEG_IDX
+#define CONF_SLCD_CHAR5_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character5 mapping
+// slcd_arch_char5_seg_num
+#ifndef CONF_SLCD_CHAR5_SEG_NUM
+#define CONF_SLCD_CHAR5_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character5
+// slcd_arch_char5_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR5_MAPPING_TABLE
+#define CONF_SLCD_CHAR5_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 6 Mapping Setting
+// slcd_arch_char6_setting
+#ifndef CONF_SLCD_CHAR6_ENABLE_SETTING
+#define CONF_SLCD_CHAR6_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character6 COM begin index
+// slcd_arch_char6_com_idx
+#ifndef CONF_SLCD_CHAR6_COM_IDX
+#define CONF_SLCD_CHAR6_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character6 Segment begin index
+// slcd_arch_char6_seg_idx
+#ifndef CONF_SLCD_CHAR6_SEG_IDX
+#define CONF_SLCD_CHAR6_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character6 mapping
+// slcd_arch_char6_seg_num
+#ifndef CONF_SLCD_CHAR6_SEG_NUM
+#define CONF_SLCD_CHAR6_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character6
+// slcd_arch_char6_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR6_MAPPING_TABLE
+#define CONF_SLCD_CHAR6_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 7 Mapping Setting
+// slcd_arch_char7_setting
+#ifndef CONF_SLCD_CHAR7_ENABLE_SETTING
+#define CONF_SLCD_CHAR7_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character7 COM begin index
+// slcd_arch_char7_com_idx
+#ifndef CONF_SLCD_CHAR7_COM_IDX
+#define CONF_SLCD_CHAR7_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character7 Segment begin index
+// slcd_arch_char7_seg_idx
+#ifndef CONF_SLCD_CHAR7_SEG_IDX
+#define CONF_SLCD_CHAR7_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character7 mapping
+// slcd_arch_char7_seg_num
+#ifndef CONF_SLCD_CHAR7_SEG_NUM
+#define CONF_SLCD_CHAR7_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character7
+// slcd_arch_char7_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR7_MAPPING_TABLE
+#define CONF_SLCD_CHAR7_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 8 Mapping Setting
+// slcd_arch_char8_setting
+#ifndef CONF_SLCD_CHAR8_ENABLE_SETTING
+#define CONF_SLCD_CHAR8_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character8 COM begin index
+// slcd_arch_char8_com_idx
+#ifndef CONF_SLCD_CHAR8_COM_IDX
+#define CONF_SLCD_CHAR8_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character8 Segment begin index
+// slcd_arch_char8_seg_idx
+#ifndef CONF_SLCD_CHAR8_SEG_IDX
+#define CONF_SLCD_CHAR8_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character8 mapping
+// slcd_arch_char8_seg_num
+#ifndef CONF_SLCD_CHAR8_SEG_NUM
+#define CONF_SLCD_CHAR8_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character8
+// slcd_arch_char8_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR8_MAPPING_TABLE
+#define CONF_SLCD_CHAR8_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 9 Mapping Setting
+// slcd_arch_char9_setting
+#ifndef CONF_SLCD_CHAR9_ENABLE_SETTING
+#define CONF_SLCD_CHAR9_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character9 COM begin index
+// slcd_arch_char9_com_idx
+#ifndef CONF_SLCD_CHAR9_COM_IDX
+#define CONF_SLCD_CHAR9_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character9 Segment begin index
+// slcd_arch_char9_seg_idx
+#ifndef CONF_SLCD_CHAR9_SEG_IDX
+#define CONF_SLCD_CHAR9_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character9 mapping
+// slcd_arch_char9_seg_num
+#ifndef CONF_SLCD_CHAR9_SEG_NUM
+#define CONF_SLCD_CHAR9_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character9
+// slcd_arch_char9_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR9_MAPPING_TABLE
+#define CONF_SLCD_CHAR9_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 10 Mapping Setting
+// slcd_arch_char10_setting
+#ifndef CONF_SLCD_CHAR10_ENABLE_SETTING
+#define CONF_SLCD_CHAR10_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character10 COM begin index
+// slcd_arch_char10_com_idx
+#ifndef CONF_SLCD_CHAR10_COM_IDX
+#define CONF_SLCD_CHAR10_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character10 Segment begin index
+// slcd_arch_char10_seg_idx
+#ifndef CONF_SLCD_CHAR10_SEG_IDX
+#define CONF_SLCD_CHAR10_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character10 mapping
+// slcd_arch_char10_seg_num
+#ifndef CONF_SLCD_CHAR10_SEG_NUM
+#define CONF_SLCD_CHAR10_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character10
+// slcd_arch_char10_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR10_MAPPING_TABLE
+#define CONF_SLCD_CHAR10_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 11 Mapping Setting
+// slcd_arch_char11_setting
+#ifndef CONF_SLCD_CHAR11_ENABLE_SETTING
+#define CONF_SLCD_CHAR11_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character11 COM begin index
+// slcd_arch_char11_com_idx
+#ifndef CONF_SLCD_CHAR11_COM_IDX
+#define CONF_SLCD_CHAR11_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character11 Segment begin index
+// slcd_arch_char11_seg_idx
+#ifndef CONF_SLCD_CHAR11_SEG_IDX
+#define CONF_SLCD_CHAR11_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character11 mapping
+// slcd_arch_char11_seg_num
+#ifndef CONF_SLCD_CHAR11_SEG_NUM
+#define CONF_SLCD_CHAR11_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character11
+// slcd_arch_char11_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR11_MAPPING_TABLE
+#define CONF_SLCD_CHAR11_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 12 Mapping Setting
+// slcd_arch_char12_setting
+#ifndef CONF_SLCD_CHAR12_ENABLE_SETTING
+#define CONF_SLCD_CHAR12_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character12 COM begin index
+// slcd_arch_char12_com_idx
+#ifndef CONF_SLCD_CHAR12_COM_IDX
+#define CONF_SLCD_CHAR12_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character12 Segment begin index
+// slcd_arch_char12_seg_idx
+#ifndef CONF_SLCD_CHAR12_SEG_IDX
+#define CONF_SLCD_CHAR12_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character12 mapping
+// slcd_arch_char12_seg_num
+#ifndef CONF_SLCD_CHAR12_SEG_NUM
+#define CONF_SLCD_CHAR12_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character12
+// slcd_arch_char12_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR12_MAPPING_TABLE
+#define CONF_SLCD_CHAR12_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 13 Mapping Setting
+// slcd_arch_char13_setting
+#ifndef CONF_SLCD_CHAR13_ENABLE_SETTING
+#define CONF_SLCD_CHAR13_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character13 COM begin index
+// slcd_arch_char13_com_idx
+#ifndef CONF_SLCD_CHAR13_COM_IDX
+#define CONF_SLCD_CHAR13_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character13 Segment begin index
+// slcd_arch_char13_seg_idx
+#ifndef CONF_SLCD_CHAR13_SEG_IDX
+#define CONF_SLCD_CHAR13_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character13 mapping
+// slcd_arch_char13_seg_num
+#ifndef CONF_SLCD_CHAR13_SEG_NUM
+#define CONF_SLCD_CHAR13_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character13
+// slcd_arch_char13_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR13_MAPPING_TABLE
+#define CONF_SLCD_CHAR13_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 14 Mapping Setting
+// slcd_arch_char14_setting
+#ifndef CONF_SLCD_CHAR14_ENABLE_SETTING
+#define CONF_SLCD_CHAR14_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character14 COM begin index
+// slcd_arch_char14_com_idx
+#ifndef CONF_SLCD_CHAR14_COM_IDX
+#define CONF_SLCD_CHAR14_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character14 Segment begin index
+// slcd_arch_char14_seg_idx
+#ifndef CONF_SLCD_CHAR14_SEG_IDX
+#define CONF_SLCD_CHAR14_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character14 mapping
+// slcd_arch_char14_seg_num
+#ifndef CONF_SLCD_CHAR14_SEG_NUM
+#define CONF_SLCD_CHAR14_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character14
+// slcd_arch_char14_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR14_MAPPING_TABLE
+#define CONF_SLCD_CHAR14_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 15 Mapping Setting
+// slcd_arch_char15_setting
+#ifndef CONF_SLCD_CHAR15_ENABLE_SETTING
+#define CONF_SLCD_CHAR15_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character15 COM begin index
+// slcd_arch_char15_com_idx
+#ifndef CONF_SLCD_CHAR15_COM_IDX
+#define CONF_SLCD_CHAR15_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character15 Segment begin index
+// slcd_arch_char15_seg_idx
+#ifndef CONF_SLCD_CHAR15_SEG_IDX
+#define CONF_SLCD_CHAR15_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character15 mapping
+// slcd_arch_char15_seg_num
+#ifndef CONF_SLCD_CHAR15_SEG_NUM
+#define CONF_SLCD_CHAR15_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character15
+// slcd_arch_char15_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR15_MAPPING_TABLE
+#define CONF_SLCD_CHAR15_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 16 Mapping Setting
+// slcd_arch_char16_setting
+#ifndef CONF_SLCD_CHAR16_ENABLE_SETTING
+#define CONF_SLCD_CHAR16_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character16 COM begin index
+// slcd_arch_char16_com_idx
+#ifndef CONF_SLCD_CHAR16_COM_IDX
+#define CONF_SLCD_CHAR16_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character16 Segment begin index
+// slcd_arch_char16_seg_idx
+#ifndef CONF_SLCD_CHAR16_SEG_IDX
+#define CONF_SLCD_CHAR16_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character16 mapping
+// slcd_arch_char16_seg_num
+#ifndef CONF_SLCD_CHAR16_SEG_NUM
+#define CONF_SLCD_CHAR16_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character16
+// slcd_arch_char16_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR16_MAPPING_TABLE
+#define CONF_SLCD_CHAR16_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 17 Mapping Setting
+// slcd_arch_char17_setting
+#ifndef CONF_SLCD_CHAR17_ENABLE_SETTING
+#define CONF_SLCD_CHAR17_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character17 COM begin index
+// slcd_arch_char17_com_idx
+#ifndef CONF_SLCD_CHAR17_COM_IDX
+#define CONF_SLCD_CHAR17_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character17 Segment begin index
+// slcd_arch_char17_seg_idx
+#ifndef CONF_SLCD_CHAR17_SEG_IDX
+#define CONF_SLCD_CHAR17_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character17 mapping
+// slcd_arch_char17_seg_num
+#ifndef CONF_SLCD_CHAR17_SEG_NUM
+#define CONF_SLCD_CHAR17_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character17
+// slcd_arch_char17_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR17_MAPPING_TABLE
+#define CONF_SLCD_CHAR17_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 18 Mapping Setting
+// slcd_arch_char18_setting
+#ifndef CONF_SLCD_CHAR18_ENABLE_SETTING
+#define CONF_SLCD_CHAR18_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character18 COM begin index
+// slcd_arch_char18_com_idx
+#ifndef CONF_SLCD_CHAR18_COM_IDX
+#define CONF_SLCD_CHAR18_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character18 Segment begin index
+// slcd_arch_char18_seg_idx
+#ifndef CONF_SLCD_CHAR18_SEG_IDX
+#define CONF_SLCD_CHAR18_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character18 mapping
+// slcd_arch_char18_seg_num
+#ifndef CONF_SLCD_CHAR18_SEG_NUM
+#define CONF_SLCD_CHAR18_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character18
+// slcd_arch_char18_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR18_MAPPING_TABLE
+#define CONF_SLCD_CHAR18_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 19 Mapping Setting
+// slcd_arch_char19_setting
+#ifndef CONF_SLCD_CHAR19_ENABLE_SETTING
+#define CONF_SLCD_CHAR19_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character19 COM begin index
+// slcd_arch_char19_com_idx
+#ifndef CONF_SLCD_CHAR19_COM_IDX
+#define CONF_SLCD_CHAR19_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character19 Segment begin index
+// slcd_arch_char19_seg_idx
+#ifndef CONF_SLCD_CHAR19_SEG_IDX
+#define CONF_SLCD_CHAR19_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character19 mapping
+// slcd_arch_char19_seg_num
+#ifndef CONF_SLCD_CHAR19_SEG_NUM
+#define CONF_SLCD_CHAR19_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character19
+// slcd_arch_char19_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR19_MAPPING_TABLE
+#define CONF_SLCD_CHAR19_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 20 Mapping Setting
+// slcd_arch_char20_setting
+#ifndef CONF_SLCD_CHAR20_ENABLE_SETTING
+#define CONF_SLCD_CHAR20_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character20 COM begin index
+// slcd_arch_char20_com_idx
+#ifndef CONF_SLCD_CHAR20_COM_IDX
+#define CONF_SLCD_CHAR20_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character20 Segment begin index
+// slcd_arch_char20_seg_idx
+#ifndef CONF_SLCD_CHAR20_SEG_IDX
+#define CONF_SLCD_CHAR20_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character20 mapping
+// slcd_arch_char20_seg_num
+#ifndef CONF_SLCD_CHAR20_SEG_NUM
+#define CONF_SLCD_CHAR20_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character20
+// slcd_arch_char20_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR20_MAPPING_TABLE
+#define CONF_SLCD_CHAR20_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 21 Mapping Setting
+// slcd_arch_char21_setting
+#ifndef CONF_SLCD_CHAR21_ENABLE_SETTING
+#define CONF_SLCD_CHAR21_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character21 COM begin index
+// slcd_arch_char21_com_idx
+#ifndef CONF_SLCD_CHAR21_COM_IDX
+#define CONF_SLCD_CHAR21_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character21 Segment begin index
+// slcd_arch_char21_seg_idx
+#ifndef CONF_SLCD_CHAR21_SEG_IDX
+#define CONF_SLCD_CHAR21_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character21 mapping
+// slcd_arch_char21_seg_num
+#ifndef CONF_SLCD_CHAR21_SEG_NUM
+#define CONF_SLCD_CHAR21_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character21
+// slcd_arch_char21_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR21_MAPPING_TABLE
+#define CONF_SLCD_CHAR21_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 22 Mapping Setting
+// slcd_arch_char22_setting
+#ifndef CONF_SLCD_CHAR22_ENABLE_SETTING
+#define CONF_SLCD_CHAR22_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character22 COM begin index
+// slcd_arch_char22_com_idx
+#ifndef CONF_SLCD_CHAR22_COM_IDX
+#define CONF_SLCD_CHAR22_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character22 Segment begin index
+// slcd_arch_char22_seg_idx
+#ifndef CONF_SLCD_CHAR22_SEG_IDX
+#define CONF_SLCD_CHAR22_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character22 mapping
+// slcd_arch_char22_seg_num
+#ifndef CONF_SLCD_CHAR22_SEG_NUM
+#define CONF_SLCD_CHAR22_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character22
+// slcd_arch_char22_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR22_MAPPING_TABLE
+#define CONF_SLCD_CHAR22_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 23 Mapping Setting
+// slcd_arch_char23_setting
+#ifndef CONF_SLCD_CHAR23_ENABLE_SETTING
+#define CONF_SLCD_CHAR23_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character23 COM begin index
+// slcd_arch_char23_com_idx
+#ifndef CONF_SLCD_CHAR23_COM_IDX
+#define CONF_SLCD_CHAR23_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character23 Segment begin index
+// slcd_arch_char23_seg_idx
+#ifndef CONF_SLCD_CHAR23_SEG_IDX
+#define CONF_SLCD_CHAR23_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character23 mapping
+// slcd_arch_char23_seg_num
+#ifndef CONF_SLCD_CHAR23_SEG_NUM
+#define CONF_SLCD_CHAR23_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character23
+// slcd_arch_char23_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR23_MAPPING_TABLE
+#define CONF_SLCD_CHAR23_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 24 Mapping Setting
+// slcd_arch_char24_setting
+#ifndef CONF_SLCD_CHAR24_ENABLE_SETTING
+#define CONF_SLCD_CHAR24_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character24 COM begin index
+// slcd_arch_char24_com_idx
+#ifndef CONF_SLCD_CHAR24_COM_IDX
+#define CONF_SLCD_CHAR24_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character24 Segment begin index
+// slcd_arch_char24_seg_idx
+#ifndef CONF_SLCD_CHAR24_SEG_IDX
+#define CONF_SLCD_CHAR24_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character24 mapping
+// slcd_arch_char24_seg_num
+#ifndef CONF_SLCD_CHAR24_SEG_NUM
+#define CONF_SLCD_CHAR24_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character24
+// slcd_arch_char24_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR24_MAPPING_TABLE
+#define CONF_SLCD_CHAR24_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 25 Mapping Setting
+// slcd_arch_char25_setting
+#ifndef CONF_SLCD_CHAR25_ENABLE_SETTING
+#define CONF_SLCD_CHAR25_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character25 COM begin index
+// slcd_arch_char25_com_idx
+#ifndef CONF_SLCD_CHAR25_COM_IDX
+#define CONF_SLCD_CHAR25_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character25 Segment begin index
+// slcd_arch_char25_seg_idx
+#ifndef CONF_SLCD_CHAR25_SEG_IDX
+#define CONF_SLCD_CHAR25_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character25 mapping
+// slcd_arch_char25_seg_num
+#ifndef CONF_SLCD_CHAR25_SEG_NUM
+#define CONF_SLCD_CHAR25_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character25
+// slcd_arch_char25_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR25_MAPPING_TABLE
+#define CONF_SLCD_CHAR25_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 26 Mapping Setting
+// slcd_arch_char26_setting
+#ifndef CONF_SLCD_CHAR26_ENABLE_SETTING
+#define CONF_SLCD_CHAR26_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character26 COM begin index
+// slcd_arch_char26_com_idx
+#ifndef CONF_SLCD_CHAR26_COM_IDX
+#define CONF_SLCD_CHAR26_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character26 Segment begin index
+// slcd_arch_char26_seg_idx
+#ifndef CONF_SLCD_CHAR26_SEG_IDX
+#define CONF_SLCD_CHAR26_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character26 mapping
+// slcd_arch_char26_seg_num
+#ifndef CONF_SLCD_CHAR26_SEG_NUM
+#define CONF_SLCD_CHAR26_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character26
+// slcd_arch_char26_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR26_MAPPING_TABLE
+#define CONF_SLCD_CHAR26_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 27 Mapping Setting
+// slcd_arch_char27_setting
+#ifndef CONF_SLCD_CHAR27_ENABLE_SETTING
+#define CONF_SLCD_CHAR27_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character27 COM begin index
+// slcd_arch_char27_com_idx
+#ifndef CONF_SLCD_CHAR27_COM_IDX
+#define CONF_SLCD_CHAR27_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character27 Segment begin index
+// slcd_arch_char27_seg_idx
+#ifndef CONF_SLCD_CHAR27_SEG_IDX
+#define CONF_SLCD_CHAR27_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character27 mapping
+// slcd_arch_char27_seg_num
+#ifndef CONF_SLCD_CHAR27_SEG_NUM
+#define CONF_SLCD_CHAR27_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character27
+// slcd_arch_char27_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR27_MAPPING_TABLE
+#define CONF_SLCD_CHAR27_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 28 Mapping Setting
+// slcd_arch_char28_setting
+#ifndef CONF_SLCD_CHAR28_ENABLE_SETTING
+#define CONF_SLCD_CHAR28_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character28 COM begin index
+// slcd_arch_char28_com_idx
+#ifndef CONF_SLCD_CHAR28_COM_IDX
+#define CONF_SLCD_CHAR28_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character28 Segment begin index
+// slcd_arch_char28_seg_idx
+#ifndef CONF_SLCD_CHAR28_SEG_IDX
+#define CONF_SLCD_CHAR28_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character28 mapping
+// slcd_arch_char28_seg_num
+#ifndef CONF_SLCD_CHAR28_SEG_NUM
+#define CONF_SLCD_CHAR28_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character28
+// slcd_arch_char28_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR28_MAPPING_TABLE
+#define CONF_SLCD_CHAR28_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 29 Mapping Setting
+// slcd_arch_char29_setting
+#ifndef CONF_SLCD_CHAR29_ENABLE_SETTING
+#define CONF_SLCD_CHAR29_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character29 COM begin index
+// slcd_arch_char29_com_idx
+#ifndef CONF_SLCD_CHAR29_COM_IDX
+#define CONF_SLCD_CHAR29_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character29 Segment begin index
+// slcd_arch_char29_seg_idx
+#ifndef CONF_SLCD_CHAR29_SEG_IDX
+#define CONF_SLCD_CHAR29_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character29 mapping
+// slcd_arch_char29_seg_num
+#ifndef CONF_SLCD_CHAR29_SEG_NUM
+#define CONF_SLCD_CHAR29_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character29
+// slcd_arch_char29_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR29_MAPPING_TABLE
+#define CONF_SLCD_CHAR29_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 30 Mapping Setting
+// slcd_arch_char30_setting
+#ifndef CONF_SLCD_CHAR30_ENABLE_SETTING
+#define CONF_SLCD_CHAR30_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character30 COM begin index
+// slcd_arch_char30_com_idx
+#ifndef CONF_SLCD_CHAR30_COM_IDX
+#define CONF_SLCD_CHAR30_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character30 Segment begin index
+// slcd_arch_char30_seg_idx
+#ifndef CONF_SLCD_CHAR30_SEG_IDX
+#define CONF_SLCD_CHAR30_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character30 mapping
+// slcd_arch_char30_seg_num
+#ifndef CONF_SLCD_CHAR30_SEG_NUM
+#define CONF_SLCD_CHAR30_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character30
+// slcd_arch_char30_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR30_MAPPING_TABLE
+#define CONF_SLCD_CHAR30_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 31 Mapping Setting
+// slcd_arch_char31_setting
+#ifndef CONF_SLCD_CHAR31_ENABLE_SETTING
+#define CONF_SLCD_CHAR31_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character31 COM begin index
+// slcd_arch_char31_com_idx
+#ifndef CONF_SLCD_CHAR31_COM_IDX
+#define CONF_SLCD_CHAR31_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character31 Segment begin index
+// slcd_arch_char31_seg_idx
+#ifndef CONF_SLCD_CHAR31_SEG_IDX
+#define CONF_SLCD_CHAR31_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character31 mapping
+// slcd_arch_char31_seg_num
+#ifndef CONF_SLCD_CHAR31_SEG_NUM
+#define CONF_SLCD_CHAR31_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character31
+// slcd_arch_char31_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR31_MAPPING_TABLE
+#define CONF_SLCD_CHAR31_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 32 Mapping Setting
+// slcd_arch_char32_setting
+#ifndef CONF_SLCD_CHAR32_ENABLE_SETTING
+#define CONF_SLCD_CHAR32_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character32 COM begin index
+// slcd_arch_char32_com_idx
+#ifndef CONF_SLCD_CHAR32_COM_IDX
+#define CONF_SLCD_CHAR32_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character32 Segment begin index
+// slcd_arch_char32_seg_idx
+#ifndef CONF_SLCD_CHAR32_SEG_IDX
+#define CONF_SLCD_CHAR32_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character32 mapping
+// slcd_arch_char32_seg_num
+#ifndef CONF_SLCD_CHAR32_SEG_NUM
+#define CONF_SLCD_CHAR32_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character32
+// slcd_arch_char32_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR32_MAPPING_TABLE
+#define CONF_SLCD_CHAR32_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 33 Mapping Setting
+// slcd_arch_char33_setting
+#ifndef CONF_SLCD_CHAR33_ENABLE_SETTING
+#define CONF_SLCD_CHAR33_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character33 COM begin index
+// slcd_arch_char33_com_idx
+#ifndef CONF_SLCD_CHAR33_COM_IDX
+#define CONF_SLCD_CHAR33_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character33 Segment begin index
+// slcd_arch_char33_seg_idx
+#ifndef CONF_SLCD_CHAR33_SEG_IDX
+#define CONF_SLCD_CHAR33_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character33 mapping
+// slcd_arch_char33_seg_num
+#ifndef CONF_SLCD_CHAR33_SEG_NUM
+#define CONF_SLCD_CHAR33_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character33
+// slcd_arch_char33_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR33_MAPPING_TABLE
+#define CONF_SLCD_CHAR33_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 34 Mapping Setting
+// slcd_arch_char34_setting
+#ifndef CONF_SLCD_CHAR34_ENABLE_SETTING
+#define CONF_SLCD_CHAR34_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character34 COM begin index
+// slcd_arch_char34_com_idx
+#ifndef CONF_SLCD_CHAR34_COM_IDX
+#define CONF_SLCD_CHAR34_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character34 Segment begin index
+// slcd_arch_char34_seg_idx
+#ifndef CONF_SLCD_CHAR34_SEG_IDX
+#define CONF_SLCD_CHAR34_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character34 mapping
+// slcd_arch_char34_seg_num
+#ifndef CONF_SLCD_CHAR34_SEG_NUM
+#define CONF_SLCD_CHAR34_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character34
+// slcd_arch_char34_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR34_MAPPING_TABLE
+#define CONF_SLCD_CHAR34_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 35 Mapping Setting
+// slcd_arch_char35_setting
+#ifndef CONF_SLCD_CHAR35_ENABLE_SETTING
+#define CONF_SLCD_CHAR35_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character35 COM begin index
+// slcd_arch_char35_com_idx
+#ifndef CONF_SLCD_CHAR35_COM_IDX
+#define CONF_SLCD_CHAR35_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character35 Segment begin index
+// slcd_arch_char35_seg_idx
+#ifndef CONF_SLCD_CHAR35_SEG_IDX
+#define CONF_SLCD_CHAR35_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character35 mapping
+// slcd_arch_char35_seg_num
+#ifndef CONF_SLCD_CHAR35_SEG_NUM
+#define CONF_SLCD_CHAR35_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character35
+// slcd_arch_char35_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR35_MAPPING_TABLE
+#define CONF_SLCD_CHAR35_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 36 Mapping Setting
+// slcd_arch_char36_setting
+#ifndef CONF_SLCD_CHAR36_ENABLE_SETTING
+#define CONF_SLCD_CHAR36_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character36 COM begin index
+// slcd_arch_char36_com_idx
+#ifndef CONF_SLCD_CHAR36_COM_IDX
+#define CONF_SLCD_CHAR36_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character36 Segment begin index
+// slcd_arch_char36_seg_idx
+#ifndef CONF_SLCD_CHAR36_SEG_IDX
+#define CONF_SLCD_CHAR36_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character36 mapping
+// slcd_arch_char36_seg_num
+#ifndef CONF_SLCD_CHAR36_SEG_NUM
+#define CONF_SLCD_CHAR36_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character36
+// slcd_arch_char36_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR36_MAPPING_TABLE
+#define CONF_SLCD_CHAR36_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 37 Mapping Setting
+// slcd_arch_char37_setting
+#ifndef CONF_SLCD_CHAR37_ENABLE_SETTING
+#define CONF_SLCD_CHAR37_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character37 COM begin index
+// slcd_arch_char37_com_idx
+#ifndef CONF_SLCD_CHAR37_COM_IDX
+#define CONF_SLCD_CHAR37_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character37 Segment begin index
+// slcd_arch_char37_seg_idx
+#ifndef CONF_SLCD_CHAR37_SEG_IDX
+#define CONF_SLCD_CHAR37_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character37 mapping
+// slcd_arch_char37_seg_num
+#ifndef CONF_SLCD_CHAR37_SEG_NUM
+#define CONF_SLCD_CHAR37_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character37
+// slcd_arch_char37_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR37_MAPPING_TABLE
+#define CONF_SLCD_CHAR37_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 38 Mapping Setting
+// slcd_arch_char38_setting
+#ifndef CONF_SLCD_CHAR38_ENABLE_SETTING
+#define CONF_SLCD_CHAR38_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character38 COM begin index
+// slcd_arch_char38_com_idx
+#ifndef CONF_SLCD_CHAR38_COM_IDX
+#define CONF_SLCD_CHAR38_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character38 Segment begin index
+// slcd_arch_char38_seg_idx
+#ifndef CONF_SLCD_CHAR38_SEG_IDX
+#define CONF_SLCD_CHAR38_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character38 mapping
+// slcd_arch_char38_seg_num
+#ifndef CONF_SLCD_CHAR38_SEG_NUM
+#define CONF_SLCD_CHAR38_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character38
+// slcd_arch_char38_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR38_MAPPING_TABLE
+#define CONF_SLCD_CHAR38_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 39 Mapping Setting
+// slcd_arch_char39_setting
+#ifndef CONF_SLCD_CHAR39_ENABLE_SETTING
+#define CONF_SLCD_CHAR39_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character39 COM begin index
+// slcd_arch_char39_com_idx
+#ifndef CONF_SLCD_CHAR39_COM_IDX
+#define CONF_SLCD_CHAR39_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character39 Segment begin index
+// slcd_arch_char39_seg_idx
+#ifndef CONF_SLCD_CHAR39_SEG_IDX
+#define CONF_SLCD_CHAR39_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character39 mapping
+// slcd_arch_char39_seg_num
+#ifndef CONF_SLCD_CHAR39_SEG_NUM
+#define CONF_SLCD_CHAR39_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character39
+// slcd_arch_char39_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR39_MAPPING_TABLE
+#define CONF_SLCD_CHAR39_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 40 Mapping Setting
+// slcd_arch_char40_setting
+#ifndef CONF_SLCD_CHAR40_ENABLE_SETTING
+#define CONF_SLCD_CHAR40_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character40 COM begin index
+// slcd_arch_char40_com_idx
+#ifndef CONF_SLCD_CHAR40_COM_IDX
+#define CONF_SLCD_CHAR40_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character40 Segment begin index
+// slcd_arch_char40_seg_idx
+#ifndef CONF_SLCD_CHAR40_SEG_IDX
+#define CONF_SLCD_CHAR40_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character40 mapping
+// slcd_arch_char40_seg_num
+#ifndef CONF_SLCD_CHAR40_SEG_NUM
+#define CONF_SLCD_CHAR40_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character40
+// slcd_arch_char40_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR40_MAPPING_TABLE
+#define CONF_SLCD_CHAR40_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 41 Mapping Setting
+// slcd_arch_char41_setting
+#ifndef CONF_SLCD_CHAR41_ENABLE_SETTING
+#define CONF_SLCD_CHAR41_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character41 COM begin index
+// slcd_arch_char41_com_idx
+#ifndef CONF_SLCD_CHAR41_COM_IDX
+#define CONF_SLCD_CHAR41_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character41 Segment begin index
+// slcd_arch_char41_seg_idx
+#ifndef CONF_SLCD_CHAR41_SEG_IDX
+#define CONF_SLCD_CHAR41_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character41 mapping
+// slcd_arch_char41_seg_num
+#ifndef CONF_SLCD_CHAR41_SEG_NUM
+#define CONF_SLCD_CHAR41_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character41
+// slcd_arch_char41_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR41_MAPPING_TABLE
+#define CONF_SLCD_CHAR41_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 42 Mapping Setting
+// slcd_arch_char42_setting
+#ifndef CONF_SLCD_CHAR42_ENABLE_SETTING
+#define CONF_SLCD_CHAR42_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character42 COM begin index
+// slcd_arch_char42_com_idx
+#ifndef CONF_SLCD_CHAR42_COM_IDX
+#define CONF_SLCD_CHAR42_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character42 Segment begin index
+// slcd_arch_char42_seg_idx
+#ifndef CONF_SLCD_CHAR42_SEG_IDX
+#define CONF_SLCD_CHAR42_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character42 mapping
+// slcd_arch_char42_seg_num
+#ifndef CONF_SLCD_CHAR42_SEG_NUM
+#define CONF_SLCD_CHAR42_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character42
+// slcd_arch_char42_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR42_MAPPING_TABLE
+#define CONF_SLCD_CHAR42_MAPPING_SIZE 7
+#endif
+
+//
+
+// Character 43 Mapping Setting
+// slcd_arch_char43_setting
+#ifndef CONF_SLCD_CHAR43_ENABLE_SETTING
+#define CONF_SLCD_CHAR43_ENABLE_SETTING 0
+#endif
+
+// COM index <0-7>
+// Character43 COM begin index
+// slcd_arch_char43_com_idx
+#ifndef CONF_SLCD_CHAR43_COM_IDX
+#define CONF_SLCD_CHAR43_COM_IDX 0
+#endif
+
+// Segment index <0-44>
+// Character43 Segment begin index
+// slcd_arch_char43_seg_idx
+#ifndef CONF_SLCD_CHAR43_SEG_IDX
+#define CONF_SLCD_CHAR43_SEG_IDX 1
+#endif
+
+// Number of Segment <1-24>
+// Number of Segment used for Character43 mapping
+// slcd_arch_char43_seg_num
+#ifndef CONF_SLCD_CHAR43_SEG_NUM
+#define CONF_SLCD_CHAR43_SEG_NUM 1
+#endif
+
+// Mapping Table
+// Select the char mapping table for Character43
+// slcd_arch_char43_mapping_table
+// <7=>7 Segments Mapping Table
+// <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR43_MAPPING_TABLE
+#define CONF_SLCD_CHAR43_MAPPING_SIZE 7
+#endif
+
+//
+
+/**
+ * character lookup table
+ */
+#define SLCD_CHAR_SETTING_TABLE \
+ { \
+ {CONF_SLCD_CHAR0_COM_IDX, CONF_SLCD_CHAR0_SEG_IDX, CONF_SLCD_CHAR0_SEG_NUM - 1, CONF_SLCD_CHAR0_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR1_COM_IDX, \
+ CONF_SLCD_CHAR1_SEG_IDX, \
+ CONF_SLCD_CHAR1_SEG_NUM - 1, \
+ CONF_SLCD_CHAR1_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR2_COM_IDX, \
+ CONF_SLCD_CHAR2_SEG_IDX, \
+ CONF_SLCD_CHAR2_SEG_NUM - 1, \
+ CONF_SLCD_CHAR2_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR3_COM_IDX, \
+ CONF_SLCD_CHAR3_SEG_IDX, \
+ CONF_SLCD_CHAR3_SEG_NUM - 1, \
+ CONF_SLCD_CHAR3_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR4_COM_IDX, \
+ CONF_SLCD_CHAR4_SEG_IDX, \
+ CONF_SLCD_CHAR4_SEG_NUM - 1, \
+ CONF_SLCD_CHAR4_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR5_COM_IDX, \
+ CONF_SLCD_CHAR5_SEG_IDX, \
+ CONF_SLCD_CHAR5_SEG_NUM - 1, \
+ CONF_SLCD_CHAR5_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR6_COM_IDX, \
+ CONF_SLCD_CHAR6_SEG_IDX, \
+ CONF_SLCD_CHAR6_SEG_NUM - 1, \
+ CONF_SLCD_CHAR6_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR7_COM_IDX, \
+ CONF_SLCD_CHAR7_SEG_IDX, \
+ CONF_SLCD_CHAR7_SEG_NUM - 1, \
+ CONF_SLCD_CHAR7_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR8_COM_IDX, \
+ CONF_SLCD_CHAR8_SEG_IDX, \
+ CONF_SLCD_CHAR8_SEG_NUM - 1, \
+ CONF_SLCD_CHAR8_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR9_COM_IDX, \
+ CONF_SLCD_CHAR9_SEG_IDX, \
+ CONF_SLCD_CHAR9_SEG_NUM - 1, \
+ CONF_SLCD_CHAR9_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR10_COM_IDX, \
+ CONF_SLCD_CHAR10_SEG_IDX, \
+ CONF_SLCD_CHAR10_SEG_NUM - 1, \
+ CONF_SLCD_CHAR10_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR11_COM_IDX, \
+ CONF_SLCD_CHAR11_SEG_IDX, \
+ CONF_SLCD_CHAR11_SEG_NUM - 1, \
+ CONF_SLCD_CHAR11_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR12_COM_IDX, \
+ CONF_SLCD_CHAR12_SEG_IDX, \
+ CONF_SLCD_CHAR12_SEG_NUM - 1, \
+ CONF_SLCD_CHAR12_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR13_COM_IDX, \
+ CONF_SLCD_CHAR13_SEG_IDX, \
+ CONF_SLCD_CHAR13_SEG_NUM - 1, \
+ CONF_SLCD_CHAR13_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR14_COM_IDX, \
+ CONF_SLCD_CHAR14_SEG_IDX, \
+ CONF_SLCD_CHAR14_SEG_NUM - 1, \
+ CONF_SLCD_CHAR14_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR15_COM_IDX, \
+ CONF_SLCD_CHAR15_SEG_IDX, \
+ CONF_SLCD_CHAR15_SEG_NUM - 1, \
+ CONF_SLCD_CHAR15_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR16_COM_IDX, \
+ CONF_SLCD_CHAR16_SEG_IDX, \
+ CONF_SLCD_CHAR16_SEG_NUM - 1, \
+ CONF_SLCD_CHAR16_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR17_COM_IDX, \
+ CONF_SLCD_CHAR17_SEG_IDX, \
+ CONF_SLCD_CHAR17_SEG_NUM - 1, \
+ CONF_SLCD_CHAR17_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR18_COM_IDX, \
+ CONF_SLCD_CHAR18_SEG_IDX, \
+ CONF_SLCD_CHAR18_SEG_NUM - 1, \
+ CONF_SLCD_CHAR18_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR19_COM_IDX, \
+ CONF_SLCD_CHAR19_SEG_IDX, \
+ CONF_SLCD_CHAR19_SEG_NUM - 1, \
+ CONF_SLCD_CHAR19_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR20_COM_IDX, \
+ CONF_SLCD_CHAR20_SEG_IDX, \
+ CONF_SLCD_CHAR20_SEG_NUM - 1, \
+ CONF_SLCD_CHAR20_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR21_COM_IDX, \
+ CONF_SLCD_CHAR21_SEG_IDX, \
+ CONF_SLCD_CHAR21_SEG_NUM - 1, \
+ CONF_SLCD_CHAR21_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR22_COM_IDX, \
+ CONF_SLCD_CHAR22_SEG_IDX, \
+ CONF_SLCD_CHAR22_SEG_NUM - 1, \
+ CONF_SLCD_CHAR22_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR23_COM_IDX, \
+ CONF_SLCD_CHAR23_SEG_IDX, \
+ CONF_SLCD_CHAR23_SEG_NUM - 1, \
+ CONF_SLCD_CHAR23_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR24_COM_IDX, \
+ CONF_SLCD_CHAR24_SEG_IDX, \
+ CONF_SLCD_CHAR24_SEG_NUM - 1, \
+ CONF_SLCD_CHAR24_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR25_COM_IDX, \
+ CONF_SLCD_CHAR25_SEG_IDX, \
+ CONF_SLCD_CHAR25_SEG_NUM - 1, \
+ CONF_SLCD_CHAR25_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR26_COM_IDX, \
+ CONF_SLCD_CHAR26_SEG_IDX, \
+ CONF_SLCD_CHAR26_SEG_NUM - 1, \
+ CONF_SLCD_CHAR26_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR27_COM_IDX, \
+ CONF_SLCD_CHAR27_SEG_IDX, \
+ CONF_SLCD_CHAR27_SEG_NUM - 1, \
+ CONF_SLCD_CHAR27_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR28_COM_IDX, \
+ CONF_SLCD_CHAR28_SEG_IDX, \
+ CONF_SLCD_CHAR28_SEG_NUM - 1, \
+ CONF_SLCD_CHAR28_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR29_COM_IDX, \
+ CONF_SLCD_CHAR29_SEG_IDX, \
+ CONF_SLCD_CHAR29_SEG_NUM - 1, \
+ CONF_SLCD_CHAR29_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR30_COM_IDX, \
+ CONF_SLCD_CHAR30_SEG_IDX, \
+ CONF_SLCD_CHAR30_SEG_NUM - 1, \
+ CONF_SLCD_CHAR30_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR31_COM_IDX, \
+ CONF_SLCD_CHAR31_SEG_IDX, \
+ CONF_SLCD_CHAR31_SEG_NUM - 1, \
+ CONF_SLCD_CHAR31_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR32_COM_IDX, \
+ CONF_SLCD_CHAR32_SEG_IDX, \
+ CONF_SLCD_CHAR32_SEG_NUM - 1, \
+ CONF_SLCD_CHAR32_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR33_COM_IDX, \
+ CONF_SLCD_CHAR33_SEG_IDX, \
+ CONF_SLCD_CHAR33_SEG_NUM - 1, \
+ CONF_SLCD_CHAR33_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR34_COM_IDX, \
+ CONF_SLCD_CHAR34_SEG_IDX, \
+ CONF_SLCD_CHAR34_SEG_NUM - 1, \
+ CONF_SLCD_CHAR34_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR35_COM_IDX, \
+ CONF_SLCD_CHAR35_SEG_IDX, \
+ CONF_SLCD_CHAR35_SEG_NUM - 1, \
+ CONF_SLCD_CHAR35_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR36_COM_IDX, \
+ CONF_SLCD_CHAR36_SEG_IDX, \
+ CONF_SLCD_CHAR36_SEG_NUM - 1, \
+ CONF_SLCD_CHAR36_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR37_COM_IDX, \
+ CONF_SLCD_CHAR37_SEG_IDX, \
+ CONF_SLCD_CHAR37_SEG_NUM - 1, \
+ CONF_SLCD_CHAR37_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR38_COM_IDX, \
+ CONF_SLCD_CHAR38_SEG_IDX, \
+ CONF_SLCD_CHAR38_SEG_NUM - 1, \
+ CONF_SLCD_CHAR38_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR39_COM_IDX, \
+ CONF_SLCD_CHAR39_SEG_IDX, \
+ CONF_SLCD_CHAR39_SEG_NUM - 1, \
+ CONF_SLCD_CHAR39_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR40_COM_IDX, \
+ CONF_SLCD_CHAR40_SEG_IDX, \
+ CONF_SLCD_CHAR40_SEG_NUM - 1, \
+ CONF_SLCD_CHAR40_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR41_COM_IDX, \
+ CONF_SLCD_CHAR41_SEG_IDX, \
+ CONF_SLCD_CHAR41_SEG_NUM - 1, \
+ CONF_SLCD_CHAR41_MAPPING_SIZE}, \
+ {CONF_SLCD_CHAR42_COM_IDX, \
+ CONF_SLCD_CHAR42_SEG_IDX, \
+ CONF_SLCD_CHAR42_SEG_NUM - 1, \
+ CONF_SLCD_CHAR42_MAPPING_SIZE}, \
+ { \
+ CONF_SLCD_CHAR43_COM_IDX, CONF_SLCD_CHAR43_SEG_IDX, CONF_SLCD_CHAR43_SEG_NUM - 1, \
+ CONF_SLCD_CHAR43_MAPPING_SIZE \
+ } \
+ }
+
+#define CONF_SLCD_LPENL \
+ ((uint32_t)1 << 0 | (uint32_t)1 << 1 | (uint32_t)1 << 2 | (uint32_t)1 << 3 | (uint32_t)1 << 4 | (uint32_t)1 << 5 \
+ | (uint32_t)1 << 6 | (uint32_t)1 << 7 | (uint32_t)1 << 11 | (uint32_t)1 << 12 | (uint32_t)1 << 13 \
+ | (uint32_t)1 << 14 | (uint32_t)1 << 21 | (uint32_t)1 << 22 | (uint32_t)1 << 23 | (uint32_t)1 << 24 \
+ | (uint32_t)1 << 25 | (uint32_t)1 << 28 | (uint32_t)1 << 29 | (uint32_t)1 << 30 | (uint32_t)1 << 31 | 0)
+
+#define CONF_SLCD_LPENH \
+ ((uint32_t)1 << 0 | (uint32_t)1 << 1 | (uint32_t)1 << 2 | (uint32_t)1 << 3 | (uint32_t)1 << 10 | (uint32_t)1 << 11 \
+ | 0) //
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SLCD_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_systick_config.h b/Smol Watch Project/My Project/Config/hpl_systick_config.h
new file mode 100644
index 00000000..a7f2f362
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_systick_config.h
@@ -0,0 +1,18 @@
+/* Auto-generated config file hpl_systick_config.h */
+#ifndef HPL_SYSTICK_CONFIG_H
+#define HPL_SYSTICK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Advanced settings
+// SysTick exception request
+// Indicates whether the generation of SysTick exception is enabled or not
+// systick_arch_tickint
+#ifndef CONF_SYSTICK_TICKINT
+#define CONF_SYSTICK_TICKINT 0
+#endif
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SYSTICK_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_tc_config.h b/Smol Watch Project/My Project/Config/hpl_tc_config.h
new file mode 100644
index 00000000..61e5b1b6
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_tc_config.h
@@ -0,0 +1,206 @@
+/* Auto-generated config file hpl_tc_config.h */
+#ifndef HPL_TC_CONFIG_H
+#define HPL_TC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include
+
+#ifndef CONF_TC3_ENABLE
+#define CONF_TC3_ENABLE 1
+#endif
+
+// Basic settings
+// Prescaler
+// <0=> No division
+// <1=> Divide by 2
+// <2=> Divide by 4
+// <3=> Divide by 8
+// <4=> Divide by 16
+// <5=> Divide by 64
+// <6=> Divide by 256
+// <7=> Divide by 1024
+// This defines the prescaler value
+// tc_prescaler
+#ifndef CONF_TC3_PRESCALER
+#define CONF_TC3_PRESCALER 0
+#endif
+//
+
+// PWM Waveform Output settings
+// Waveform Period Value (uS) <0x00-0xFFFFFFFF>
+// The unit of this value is us.
+// tc_arch_wave_per_val
+#ifndef CONF_TC3_WAVE_PER_VAL
+#define CONF_TC3_WAVE_PER_VAL 0x3e8
+#endif
+
+// Waveform Duty Value (0.1%) <0x00-0x03E8>
+// The unit of this value is 1/1000.
+// tc_arch_wave_duty_val
+#ifndef CONF_TC3_WAVE_DUTY_VAL
+#define CONF_TC3_WAVE_DUTY_VAL 0x1f4
+#endif
+
+/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
+#if CONF_TC3_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TC3_CC0 \
+ ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1000000 / (1 << CONF_TC3_PRESCALER) - 1))
+#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
+
+#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 64000000 - 1))
+#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
+
+#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val
+#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 256000000 - 1))
+#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
+
+#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val
+#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1024000000 - 1))
+#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
+#endif
+
+//
+
+// Advanced settings
+// Mode
+// Counter in 16-bit mode
+// Counter in 32-bit mode
+// These bits mode
+// tc_mode
+#ifndef CONF_TC3_MODE
+#define CONF_TC3_MODE TC_CTRLA_MODE_COUNT16_Val
+#endif
+
+/* Unused in 16/32 bit PWM mode */
+#ifndef CONF_TC3_PER
+#define CONF_TC3_PER 0x32
+#endif
+
+// Prescaler and Counter Synchronization Selection
+// Reload or reset counter on next GCLK
+// Reload or reset counter on next prescaler clock
+// Reload or reset counter on next GCLK and reset prescaler counter
+// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
+// tc_arch_presync
+#ifndef CONF_TC3_PRESCSYNC
+#define CONF_TC3_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
+#endif
+
+// Run in standby
+// Indicates whether the will continue running in standby sleep mode or not
+// tc_arch_runstdby
+#ifndef CONF_TC3_RUNSTDBY
+#define CONF_TC3_RUNSTDBY 0
+#endif
+
+// On-Demand
+// Indicates whether the TC3's on-demand mode is on or not
+// tc_arch_ondemand
+#ifndef CONF_TC3_ONDEMAND
+#define CONF_TC3_ONDEMAND 0
+#endif
+
+// Auto Lock
+// <0x0=>The Lock Update bit is not affected on overflow/underflow and re-trigger event
+// <0x1=>The Lock Update bit is set on each overflow/underflow or re-trigger event
+// tc_arch_alock
+#ifndef CONF_TC3_ALOCK
+#define CONF_TC3_ALOCK 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_CAPTEN0 0
+//#define CONF_TC3_CAPTEN1 0
+//#define CONF_TC3_COPEN0 0
+//#define CONF_TC3_COPEN1 0
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_DIR 0
+//#define CONF_TC3_ONESHOT 0
+//#define CONF_TC3_LUPD 0
+
+// Debug Running Mode
+// Indicates whether the Debug Running Mode is enabled or not
+// tc_arch_dbgrun
+#ifndef CONF_TC3_DBGRUN
+#define CONF_TC3_DBGRUN 0
+#endif
+
+// Event control
+// timer_event_control
+#ifndef CONF_TC3_EVENT_CONTROL_ENABLE
+#define CONF_TC3_EVENT_CONTROL_ENABLE 0
+#endif
+
+// Output Event On Match or Capture on Channel 0
+// Enable output of event on timer tick
+// tc_arch_mceo0
+#ifndef CONF_TC3_MCEO0
+#define CONF_TC3_MCEO0 0
+#endif
+
+// Output Event On Match or Capture on Channel 1
+// Enable output of event on timer tick
+// tc_arch_mceo1
+#ifndef CONF_TC3_MCEO1
+#define CONF_TC3_MCEO1 0
+#endif
+
+// Output Event On Timer Tick
+// Enable output of event on timer tick
+// tc_arch_ovfeo
+#ifndef CONF_TC3_OVFEO
+#define CONF_TC3_OVFEO 0
+#endif
+
+// Event Input
+// Enable asynchronous input events
+// tc_arch_tcei
+#ifndef CONF_TC3_TCEI
+#define CONF_TC3_TCEI 0
+#endif
+
+// Inverted Event Input
+// Invert the asynchronous input events
+// tc_arch_tcinv
+#ifndef CONF_TC3_TCINV
+#define CONF_TC3_TCINV 0
+#endif
+
+// Event action
+// <0=> Event action disabled
+// <1=> Start, restart or re-trigger TC on event
+// <2=> Count on event
+// <3=> Start on event
+// <4=> Time stamp capture
+// <5=> Period captured in CC0, pulse width in CC1
+// <6=> Period captured in CC1, pulse width in CC0
+// <7=> Pulse width capture
+// Event which will be performed on an event
+// tc_arch_evact
+#ifndef CONF_TC3_EVACT
+#define CONF_TC3_EVACT 0
+#endif
+//
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_INVEN0 0
+//#define CONF_TC3_INVEN1 0
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_PERBUF 0
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_CCBUF0 0
+//#define CONF_TC3_CCBUF1 0
+
+//
+
+// <<< end of configuration section >>>
+
+#endif // HPL_TC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_tcc_config.h b/Smol Watch Project/My Project/Config/hpl_tcc_config.h
new file mode 100644
index 00000000..a8d45f5d
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_tcc_config.h
@@ -0,0 +1,547 @@
+/* Auto-generated config file hpl_tcc_config.h */
+#ifndef HPL_TCC_CONFIG_H
+#define HPL_TCC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include
+#ifndef CONF_TCC0_ENABLE
+#define CONF_TCC0_ENABLE 1
+#endif
+
+#ifndef CONF_TCC0_PWM_ENABLE
+#define CONF_TCC0_PWM_ENABLE 1
+#endif
+
+// Basic settings
+// TCC0 Prescaler
+// No division
+// Divide by 2
+// Divide by 4
+// Divide by 8
+// Divide by 16
+// Divide by 64
+// Divide by 256
+// Divide by 1024
+// This defines the TCC0 prescaler value
+// tcc_prescaler
+#ifndef CONF_TCC0_PRESCALER
+#define CONF_TCC0_PRESCALER TCC_CTRLA_PRESCALER_DIV8_Val
+#endif
+
+//
+// TCC0 Period Value <0x000000-0xFFFFFF>
+// tcc_per
+#ifndef CONF_TCC0_PER
+#define CONF_TCC0_PER 0x2710
+#endif
+//
+
+//
+
+// PWM Waveform Output settings
+// TCC0 Waveform Period Value (uS) <0x00-0xFFFFFFFF>
+// The unit of this value is us.
+// tcc_arch_wave_per_val
+#ifndef CONF_TCC0_WAVE_PER_VAL
+#define CONF_TCC0_WAVE_PER_VAL 0x3e8
+#endif
+
+// TCC0 Waveform Duty Value (0.1%) <0x00-0x03E8>
+// The unit of this value is 1/1000.
+// tcc_arch_wave_duty_val
+#ifndef CONF_TCC0_WAVE_DUTY_VAL
+#define CONF_TCC0_WAVE_DUTY_VAL 0x1f4
+#endif
+
+// TCC0 Waveform Channel Select <0x00-0x03>
+// Index of the Compare Channel register, into which the Waveform Duty Value is written.
+// Give index of the Compare Channel register here in 0x00-0x03 range.
+// tcc_arch_sel_ch
+#ifndef CONF_TCC0_SEL_CH
+#define CONF_TCC0_SEL_CH 0x1
+#endif
+
+/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
+#if CONF_TCC0_PRESCALER < TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC0_PER_REG \
+ ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1000000 / (1 << CONF_TCC0_PRESCALER) - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)(double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 64000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV256_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 256000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV1024_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1024000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+#endif
+//
+
+// Advanced settings
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL A register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_RESOLUTION TCC_CTRLA_RESOLUTION_NONE_Val
+// Run in standby
+// Indicates whether the TCC0 will continue running in standby sleep mode or not
+// tcc_arch_runstdby
+#ifndef CONF_TCC0_RUNSTDBY
+#define CONF_TCC0_RUNSTDBY 0
+#endif
+
+// TCC0 Prescaler and Counter Synchronization Selection
+// Reload or reset counter on next GCLK
+// Reload or reset counter on next prescaler clock
+// Reload or reset counter on next GCLK and reset prescaler counter
+// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock.
+// tcc_arch_prescsync
+#ifndef CONF_TCC0_PRESCSYNC
+#define CONF_TCC0_PRESCSYNC TCC_CTRLA_PRESCSYNC_GCLK_Val
+#endif
+
+// TCC0 Waveform Generation Selection
+// Single-slope PWM
+// Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
+// Dual-slope, interrupt/event at ZERO (DSBOTTOM)
+// Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
+// Dual-slope, interrupt/event at Top (DSTOP)
+// tcc_arch_wavegen
+#ifndef CONF_TCC0_WAVEGEN
+#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_NPWM_Val
+#endif
+// TCC0 Auto Lock
+// Indicates whether the TCC0 Auto Lock is enabled or not
+// tcc_arch_alock
+#ifndef CONF_TCC0_ALOCK
+#define CONF_TCC0_ALOCK 0
+#endif
+
+// TCC0 Capture Channel 0 Enable
+// Indicates whether the TCC0 Capture Channel 0 is enabled or not
+// tcc_arch_cpten0
+#ifndef CONF_TCC0_CPTEN0
+#define CONF_TCC0_CPTEN0 0
+#endif
+
+// TCC0 Capture Channel 1 Enable
+// Indicates whether the TCC0 Capture Channel 1 is enabled or not
+// tcc_arch_cpten1
+#ifndef CONF_TCC0_CPTEN1
+#define CONF_TCC0_CPTEN1 0
+#endif
+
+// TCC0 Capture Channel 2 Enable
+// Indicates whether the TCC0 Capture Channel 2 is enabled or not
+// tcc_arch_cpten2
+#ifndef CONF_TCC0_CPTEN2
+#define CONF_TCC0_CPTEN2 0
+#endif
+
+// TCC0 Capture Channel 3 Enable
+// Indicates whether the TCC0 Capture Channel 3 is enabled or not
+// tcc_arch_cpten3
+#ifndef CONF_TCC0_CPTEN3
+#define CONF_TCC0_CPTEN3 0
+#endif
+
+//
+// TCC0 Capture Channel 4 Enable
+// Indicates whether the TCC0 Capture Channel 4 is enabled or not
+// tcc_arch_cpten4
+#ifndef CONF_TCC0_CPTEN4
+#define CONF_TCC0_CPTEN4 0
+#endif
+//
+//
+// TCC0 Capture Channel 5 Enable
+// Indicates whether the TCC0 Capture Channel 5 is enabled or not
+// tcc_arch_cpten5
+#ifndef CONF_TCC0_CPTEN5
+#define CONF_TCC0_CPTEN5 0
+#endif
+//
+//
+// TCC0 Capture Channel 6 Enable
+// Indicates whether the TCC0 Capture Channel 6 is enabled or not
+// tcc_arch_cpten6
+#ifndef CONF_TCC0_CPTEN6
+#define CONF_TCC0_CPTEN6 0
+#endif
+//
+//
+// TCC0 Capture Channel 7 Enable
+// Indicates whether the TCC0 Capture Channel 7 is enabled or not
+// tcc_arch_cpten7
+#ifndef CONF_TCC0_CPTEN7
+#define CONF_TCC0_CPTEN7 0
+#endif
+//
+
+// TCC0 Lock update
+// Indicates whether the TCC0 Lock update is enabled or not
+// tcc_arch_lupd
+#ifndef CONF_TCC0_LUPD
+#define CONF_TCC0_LUPD 1
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_DIR 0
+//#define CONF_TCC0_ONESHOT 0
+
+/* Commented intentionally. No fault control for timers. */
+/*#define CONF_TCC0_FAULT_A_SRC TCC_FCTRLA_SRC_DISABLE_Val
+#define CONF_TCC0_FAULT_A_KEEP 0
+#define CONF_TCC0_FAULT_A_QUAL 0
+#define CONF_TCC0_FAULT_A_BLANK TCC_FCTRLA_BLANK_DISABLE_Val
+#define CONF_TCC0_FAULT_A_RESTART 0
+#define CONF_TCC0_FAULT_A_HALT TCC_FCTRLA_HALT_DISABLE_Val
+#define CONF_TCC0_FAULT_A_CHSEL TCC_FCTRLA_CHSEL_CC0_Val
+#define CONF_TCC0_FAULT_A_CAPTURE TCC_FCTRLA_CAPTURE_DISABLE_Val
+#define CONF_TCC0_FAULT_A_BLACNKPRESC 0
+#define CONF_TCC0_FAULT_A_BLANKVAL 0
+#define CONF_TCC0_FAULT_A_FILTERVAL 0
+
+#define CONF_TCC0_FAULT_B_SRC TCC_FCTRLB_SRC_DISABLE_Val
+#define CONF_TCC0_FAULT_B_KEEP 0
+#define CONF_TCC0_FAULT_B_QUAL 0
+#define CONF_TCC0_FAULT_B_BLANK TCC_FCTRLB_BLANK_DISABLE_Val
+#define CONF_TCC0_FAULT_B_RESTART 0
+#define CONF_TCC0_FAULT_B_HALT TCC_FCTRLB_HALT_DISABLE_Val
+#define CONF_TCC0_FAULT_B_CHSEL TCC_FCTRLB_CHSEL_CC0_Val
+#define CONF_TCC0_FAULT_B_CAPTURE TCC_FCTRLB_CAPTURE_DISABLE_Val
+#define CONF_TCC0_FAULT_B_BLACNKPRESC 0
+#define CONF_TCC0_FAULT_B_BLANKVAL 0
+#define CONF_TCC0_FAULT_B_FILTERVAL 0*/
+
+/* Commented intentionally. No dead-time control for timers. */
+/*#define CONF_TCC0_OTMX 0
+#define CONF_TCC0_DTIEN0 0
+#define CONF_TCC0_DTIEN1 0
+#define CONF_TCC0_DTIEN2 0
+#define CONF_TCC0_DTIEN3 0
+#define CONF_TCC0_DTHS 0*/
+
+/* Commented intentionally. No driver control for timers. */
+/*#define CONF_TCC0_NRE0 0
+#define CONF_TCC0_NRE1 0
+#define CONF_TCC0_NRE2 0
+#define CONF_TCC0_NRE3 0
+#define CONF_TCC0_NRE4 0
+#define CONF_TCC0_NRE5 0
+#define CONF_TCC0_NRE6 0
+#define CONF_TCC0_NRE7 0
+#define CONF_TCC0_NVR0 0
+#define CONF_TCC0_NVR1 0
+#define CONF_TCC0_NVR2 0
+#define CONF_TCC0_NVR3 0
+#define CONF_TCC0_NVR4 0
+#define CONF_TCC0_NVR5 0
+#define CONF_TCC0_NVR6 0
+#define CONF_TCC0_NVR7 0
+#define CONF_TCC0_INVEN0 0
+#define CONF_TCC0_INVEN1 0
+#define CONF_TCC0_INVEN2 0
+#define CONF_TCC0_INVEN3 0
+#define CONF_TCC0_INVEN4 0
+#define CONF_TCC0_INVEN5 0
+#define CONF_TCC0_INVEN6 0
+#define CONF_TCC0_INVEN7 0
+#define CONF_TCC0_FILTERVAL0 0
+#define CONF_TCC0_FILTERVAL1 0*/
+
+// TCC0 Debug Running Mode
+// Indicates whether the TCC0 Debug Running Mode is enabled or not
+// tcc_arch_dbgrun
+#ifndef CONF_TCC0_DBGRUN
+#define CONF_TCC0_DBGRUN 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of Debug Control register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_FDDBD 0
+
+// Event control
+// timer_event_control
+#ifndef CONF_TCC0_EVENT_CONTROL_ENABLE
+#define CONF_TCC0_EVENT_CONTROL_ENABLE 0
+#endif
+
+// Match or Capture Channel 0 Event Output
+// This bit indicates whether match/capture event on channel 0 is enabled and will be generated
+// tcc_arch_mceo0
+#ifndef CONF_TCC0_MCEO0
+#define CONF_TCC0_MCEO0 0
+#endif
+
+// Match or Capture Channel 0 Event Input
+// This bit indicates whether match/capture 0 incoming event is enabled
+// tcc_arch_mcei0
+#ifndef CONF_TCC0_MCEI0
+#define CONF_TCC0_MCEI0 0
+#endif
+// Match or Capture Channel 1 Event Output
+// This bit indicates whether match/capture event on channel 1 is enabled and will be generated
+// tcc_arch_mceo1
+#ifndef CONF_TCC0_MCEO1
+#define CONF_TCC0_MCEO1 0
+#endif
+
+// Match or Capture Channel 1 Event Input
+// This bit indicates whether match/capture 1 incoming event is enabled
+// tcc_arch_mcei1
+#ifndef CONF_TCC0_MCEI1
+#define CONF_TCC0_MCEI1 0
+#endif
+// Match or Capture Channel 2 Event Output
+// This bit indicates whether match/capture event on channel 2 is enabled and will be generated
+// tcc_arch_mceo2
+#ifndef CONF_TCC0_MCEO2
+#define CONF_TCC0_MCEO2 0
+#endif
+
+// Match or Capture Channel 2 Event Input
+// This bit indicates whether match/capture 2 incoming event is enabled
+// tcc_arch_mcei2
+#ifndef CONF_TCC0_MCEI2
+#define CONF_TCC0_MCEI2 0
+#endif
+// Match or Capture Channel 3 Event Output
+// This bit indicates whether match/capture event on channel 3 is enabled and will be generated
+// tcc_arch_mceo3
+#ifndef CONF_TCC0_MCEO3
+#define CONF_TCC0_MCEO3 0
+#endif
+
+// Match or Capture Channel 3 Event Input
+// This bit indicates whether match/capture 3 incoming event is enabled
+// tcc_arch_mcei3
+#ifndef CONF_TCC0_MCEI3
+#define CONF_TCC0_MCEI3 0
+#endif
+
+// Timer/Counter Event Input 0
+// This bit is used to enable input event 0 to the TCC
+// tcc_arch_tcei0
+#ifndef CONF_TCC0_TCEI0
+#define CONF_TCC0_TCEI0 0
+#endif
+
+// Timer/Counter Event Input 0 Invert
+// This bit inverts the event 0 input
+// tcc_arch_tceinv0
+#ifndef CONF_TCC0_TCINV0
+#define CONF_TCC0_TCINV0 0
+#endif
+// Timer/Counter Event Input 1
+// This bit is used to enable input event 1 to the TCC
+// tcc_arch_tcei1
+#ifndef CONF_TCC0_TCEI1
+#define CONF_TCC0_TCEI1 0
+#endif
+
+// Timer/Counter Event Input 1 Invert
+// This bit inverts the event 1 input
+// tcc_arch_tceinv1
+#ifndef CONF_TCC0_TCINV1
+#define CONF_TCC0_TCINV1 0
+#endif
+
+// Timer/Counter Event Output
+// This bit is used to enable the counter cycle event.
+// tcc_arch_cnteo
+#ifndef CONF_TCC0_CNTEO
+#define CONF_TCC0_CNTEO 0
+#endif
+
+// Re-trigger Event Output
+// This bit is used to enable the counter re-trigger event.
+// tcc_arch_trgeo
+#ifndef CONF_TCC0_TRGEO
+#define CONF_TCC0_TRGEO 0
+#endif
+
+// Overflow/Underflow Event Output
+// This bit is used to enable enable event on overflow/underflow.
+// tcc_arch_ovfeo
+#ifndef CONF_TCC0_OVFEO
+#define CONF_TCC0_OVFEO 0
+#endif
+
+// Timer/Counter Interrupt and Event Output Selection
+// <0=> An interrupt/event is generated when a new counter cycle starts
+// <1=> An interrupt/event is generated when a counter cycle ends
+// <2=> An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
+// <3=> An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
+// These bits define on which part of the counter cycle the counter event output is generated
+// tcc_arch_cntsel
+#ifndef CONF_TCC0_CNTSEL
+#define CONF_TCC0_CNTSEL 0
+#endif
+
+// Timer/Counter Event Input 0 Action
+// <0=>Event action disabled
+// <1=>Start restart or re-trigger on event
+// <2=>Count on event
+// <3=>Start on event
+// <4=>Increment on event
+// <5=>Count on active state of asynchronous event
+// <6=>Capture overflow times (Max value)
+// <7=>Non-recoverable fault
+// These bits define the action the TCC performs on TCE0 event input 0
+// tcc_arch_evact0
+#ifndef CONF_TCC0_EVACT0
+#define CONF_TCC0_EVACT0 0
+#endif
+
+// Timer/Counter Event Input 1 Action
+// <0=>Event action disabled
+// <1=>Re-trigger counter on event
+// <2=>Direction control
+// <3=>Stop counter on event
+// <4=>Decrement counter on event
+// <5=>Period capture value in CC0 register, pulse width capture value in CC1 register
+// <6=>Period capture value in CC1 register, pulse width capture value in CC0 register
+// <7=>Non-recoverable fault
+// These bits define the action the TCC performs on TCE0 event input 0
+// tcc_arch_evact1
+#ifndef CONF_TCC0_EVACT1
+#define CONF_TCC0_EVACT1 0
+#endif
+//
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC0_PGE0 0
+#define CONF_TCC0_PGE1 0
+#define CONF_TCC0_PGE2 0
+#define CONF_TCC0_PGE3 0
+#define CONF_TCC0_PGE4 0
+#define CONF_TCC0_PGE5 0
+#define CONF_TCC0_PGE6 0
+#define CONF_TCC0_PGE7 0
+#define CONF_TCC0_PGV0 0
+#define CONF_TCC0_PGV1 0
+#define CONF_TCC0_PGV2 0
+#define CONF_TCC0_PGV3 0
+#define CONF_TCC0_PGV4 0
+#define CONF_TCC0_PGV5 0
+#define CONF_TCC0_PGV6 0
+#define CONF_TCC0_PGV7 0*/
+
+/* Commented intentionally. No pattern waveform control for timers. */
+/*#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_MFRQ_Val
+#define CONF_TCC0_RAMP TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC0_CIPEREN 0
+#define CONF_TCC0_CICCEN0 0
+#define CONF_TCC0_CICCEN1 0
+#define CONF_TCC0_CICCEN2 0
+#define CONF_TCC0_CICCEN3 0
+#define CONF_TCC0_POL0 0
+#define CONF_TCC0_POL1 0
+#define CONF_TCC0_POL2 0
+#define CONF_TCC0_POL3 0
+#define CONF_TCC0_POL4 0
+#define CONF_TCC0_POL5 0
+#define CONF_TCC0_POL6 0
+#define CONF_TCC0_POL7 0
+#define CONF_TCC0_SWAP0 0
+#define CONF_TCC0_SWAP1 0
+#define CONF_TCC0_SWAP2 0
+#define CONF_TCC0_SWAP3 0*/
+
+// TCC0 Compare and Capture value 0 <0x00-0xFFFFFF>
+// tcc_arch_cc0
+#ifndef CONF_TCC0_CC0
+#define CONF_TCC0_CC0 0x0
+#endif
+
+// TCC0 Compare and Capture value 1 <0x00-0xFFFFFF>
+// tcc_arch_cc1
+#ifndef CONF_TCC0_CC1
+#define CONF_TCC0_CC1 0x0
+#endif
+
+// TCC0 Compare and Capture value 2 <0x00-0xFFFFFF>
+// tcc_arch_cc2
+#ifndef CONF_TCC0_CC2
+#define CONF_TCC0_CC2 0x0
+#endif
+
+// TCC0 Compare and Capture value 3 <0x00-0xFFFFFF>
+// tcc_arch_cc3
+#ifndef CONF_TCC0_CC3
+#define CONF_TCC0_CC3 0x0
+#endif
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC0_PATTB_PGEB0 0
+#define CONF_TCC0_PATTB_PGEB1 0
+#define CONF_TCC0_PATTB_PGEB2 0
+#define CONF_TCC0_PATTB_PGEB3 0
+#define CONF_TCC0_PATTB_PGEB4 0
+#define CONF_TCC0_PATTB_PGEB5 0
+#define CONF_TCC0_PATTB_PGEB6 0
+#define CONF_TCC0_PATTB_PGEB7 0
+#define CONF_TCC0_PATTB_PGVB0 0
+#define CONF_TCC0_PATTB_PGVB1 0
+#define CONF_TCC0_PATTB_PGVB2 0
+#define CONF_TCC0_PATTB_PGVB3 0
+#define CONF_TCC0_PATTB_PGVB4 0
+#define CONF_TCC0_PATTB_PGVB5 0
+#define CONF_TCC0_PATTB_PGVB6 0
+#define CONF_TCC0_PATTB_PGVB7 0*/
+
+/* Commented intentionally. No waveform control for timers. */
+/*#define CONF_TCC0_WAVEGENB TCC_WAVEB_WAVEGENB_MFRQ_Val
+#define CONF_TCC0_RAMPB TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC0_CIPERENB 0
+#define CONF_TCC0_CICCEN0B 0
+#define CONF_TCC0_CICCEN1B 0
+#define CONF_TCC0_CICCEN2B 0
+#define CONF_TCC0_CICCEN3B 0
+#define CONF_TCC0_POL0B 0
+#define CONF_TCC0_POL1B 0
+#define CONF_TCC0_POL2B 0
+#define CONF_TCC0_POL3B 0
+#define CONF_TCC0_POL4B 0
+#define CONF_TCC0_POL5B 0
+#define CONF_TCC0_POL6B 0
+#define CONF_TCC0_POL7B 0
+#define CONF_TCC0_SWAP0B 0
+#define CONF_TCC0_SWAP1B 0
+#define CONF_TCC0_SWAP2B 0
+#define CONF_TCC0_SWAP3B 0*/
+
+/* Commented intentionally. No buffering for timers. */
+/*#define CONF_TCC0_PERB 0
+#define CONF_TCC0_CCB0 0
+#define CONF_TCC0_CCB1 0
+#define CONF_TCC0_CCB2 0
+#define CONF_TCC0_CCB3 0*/
+//
+
+#define CONF_TCC0_CTRLA \
+ TCC_CTRLA_PRESCALER(CONF_TCC0_PRESCALER) | (CONF_TCC0_RUNSTDBY << TCC_CTRLA_RUNSTDBY_Pos) \
+ | TCC_CTRLA_PRESCSYNC(CONF_TCC0_PRESCSYNC) | (CONF_TCC0_CPTEN0 << TCC_CTRLA_CPTEN0_Pos) \
+ | (CONF_TCC0_CPTEN1 << TCC_CTRLA_CPTEN1_Pos) | (CONF_TCC0_CPTEN2 << TCC_CTRLA_CPTEN2_Pos) \
+ | (CONF_TCC0_CPTEN3 << TCC_CTRLA_CPTEN3_Pos) | (CONF_TCC0_ALOCK << TCC_CTRLA_ALOCK_Pos)
+#define CONF_TCC0_CTRLB (CONF_TCC0_LUPD << TCC_CTRLBSET_LUPD_Pos)
+#define CONF_TCC0_DBGCTRL (CONF_TCC0_DBGRUN << TCC_DBGCTRL_DBGRUN_Pos)
+#define CONF_TCC0_EVCTRL \
+ TCC_EVCTRL_CNTSEL(CONF_TCC0_CNTSEL) | (CONF_TCC0_OVFEO << TCC_EVCTRL_OVFEO_Pos) \
+ | (CONF_TCC0_TRGEO << TCC_EVCTRL_TRGEO_Pos) | (CONF_TCC0_CNTEO << TCC_EVCTRL_CNTEO_Pos) \
+ | (CONF_TCC0_MCEO0 << TCC_EVCTRL_MCEO0_Pos) | (CONF_TCC0_MCEI0 << TCC_EVCTRL_MCEI0_Pos) \
+ | (CONF_TCC0_MCEO1 << TCC_EVCTRL_MCEO1_Pos) | (CONF_TCC0_MCEI1 << TCC_EVCTRL_MCEI1_Pos) \
+ | (CONF_TCC0_MCEO2 << TCC_EVCTRL_MCEO2_Pos) | (CONF_TCC0_MCEI2 << TCC_EVCTRL_MCEI2_Pos) \
+ | (CONF_TCC0_MCEO3 << TCC_EVCTRL_MCEO3_Pos) | (CONF_TCC0_MCEI3 << TCC_EVCTRL_MCEI3_Pos) \
+ | (CONF_TCC0_TCEI0 << TCC_EVCTRL_TCEI0_Pos) | (CONF_TCC0_TCEI1 << TCC_EVCTRL_TCEI1_Pos) \
+ | (CONF_TCC0_TCINV0 << TCC_EVCTRL_TCINV0_Pos) | (CONF_TCC0_TCINV1 << TCC_EVCTRL_TCINV1_Pos) \
+ | TCC_EVCTRL_EVACT1(CONF_TCC0_EVACT1) | TCC_EVCTRL_EVACT0(CONF_TCC0_EVACT0)
+
+// <<< end of configuration section >>>
+
+#endif // HPL_TCC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/peripheral_clk_config.h b/Smol Watch Project/My Project/Config/peripheral_clk_config.h
new file mode 100644
index 00000000..9050e808
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/peripheral_clk_config.h
@@ -0,0 +1,214 @@
+/* Auto-generated config file peripheral_clk_config.h */
+#ifndef PERIPHERAL_CLK_CONFIG_H
+#define PERIPHERAL_CLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// ADC Clock Source
+// adc_gclk_selection
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Select the clock source for ADC.
+#ifndef CONF_GCLK_ADC_SRC
+#define CONF_GCLK_ADC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_ADC_FREQUENCY
+ * \brief ADC's Clock frequency
+ */
+#ifndef CONF_GCLK_ADC_FREQUENCY
+#define CONF_GCLK_ADC_FREQUENCY 4000000
+#endif
+
+// EIC Clock Source
+// eic_gclk_selection
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Select the clock source for EIC.
+#ifndef CONF_GCLK_EIC_SRC
+#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EIC_FREQUENCY
+ * \brief EIC's Clock frequency
+ */
+#ifndef CONF_GCLK_EIC_FREQUENCY
+#define CONF_GCLK_EIC_FREQUENCY 32768
+#endif
+
+/**
+ * \def CONF_CPU_FREQUENCY
+ * \brief CPU's Clock frequency
+ */
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 4000000
+#endif
+
+// RTC Clock Source
+// rtc_clk_selection
+// RTC source
+// Select the clock source for RTC.
+#ifndef CONF_GCLK_RTC_SRC
+#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
+#endif
+
+/**
+ * \def CONF_GCLK_RTC_FREQUENCY
+ * \brief RTC's Clock frequency
+ */
+#ifndef CONF_GCLK_RTC_FREQUENCY
+#define CONF_GCLK_RTC_FREQUENCY 1024
+#endif
+
+// Core Clock Source
+// core_gclk_selection
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM1_CORE_SRC
+#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// Slow Clock Source
+// slow_gclk_selection
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
+#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
+ * \brief SERCOM1's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 4000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+ * \brief SERCOM1's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
+#endif
+
+// TC Clock Source
+// tc_gclk_selection
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Select the clock source for TC.
+#ifndef CONF_GCLK_TC3_SRC
+#define CONF_GCLK_TC3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TC3_FREQUENCY
+ * \brief TC3's Clock frequency
+ */
+#ifndef CONF_GCLK_TC3_FREQUENCY
+#define CONF_GCLK_TC3_FREQUENCY 4000000
+#endif
+
+// TCC Clock Source
+// tcc_gclk_selection
+
+// Generic clock generator 0
+
+// Generic clock generator 1
+
+// Generic clock generator 2
+
+// Generic clock generator 3
+
+// Generic clock generator 4
+
+// Select the clock source for TCC.
+#ifndef CONF_GCLK_TCC0_SRC
+#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TCC0_FREQUENCY
+ * \brief TCC0's Clock frequency
+ */
+#ifndef CONF_GCLK_TCC0_FREQUENCY
+#define CONF_GCLK_TCC0_FREQUENCY 4000000
+#endif
+
+#include
+
+// SLCD Clock Source
+// slcd_clk_selection
+// SLCD source
+// Select the clock source for SLCD.
+#ifndef CONF_GCLK_SLCD_SRC
+#define CONF_GCLK_SLCD_SRC SLCD_CLOCK_SOURCE
+#endif
+
+/**
+ * \def CONF_GCLK_SLCD_FREQUENCY
+ * \brief SLCD's Clock frequency
+ */
+#ifndef CONF_GCLK_SLCD_FREQUENCY
+#define CONF_GCLK_SLCD_FREQUENCY 32768
+#endif
+
+#ifndef SLCD_FRAME_FREQUENCY
+#define SLCD_FRAME_FREQUENCY \
+ (CONF_GCLK_SLCD_FREQUENCY \
+ / (((CONF_SLCD_PRESC + 1) * 16) * (CONF_SLCD_CKDIV + 1) \
+ * ((CONF_SLCD_COM_NUM == 4) ? 6 : ((CONF_SLCD_COM_NUM == 5) ? 8 : (CONF_SLCD_COM_NUM + 1)))))
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/sleep_manager_config.h b/Smol Watch Project/My Project/Config/sleep_manager_config.h
new file mode 100644
index 00000000..ae673eaf
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/sleep_manager_config.h
@@ -0,0 +1,9 @@
+/* Auto-generated config file sleep_manager_config.h */
+#ifndef SLEEP_MANAGER_CONFIG_H
+#define SLEEP_MANAGER_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <<< end of configuration section >>>
+
+#endif // SLEEP_MANAGER_CONFIG_H
diff --git a/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.d b/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.d
new file mode 100644
index 00000000..6faec5ea
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.d
@@ -0,0 +1,239 @@
+Device_Startup/startup_saml22.d Device_Startup/startup_saml22.o: \
+ ../Device_Startup/startup_saml22.c \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
diff --git a/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.o b/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.o
new file mode 100644
index 00000000..3f44c5a8
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.o differ
diff --git a/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.d b/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.d
new file mode 100644
index 00000000..32952d2c
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.d
@@ -0,0 +1,239 @@
+Device_Startup/system_saml22.d Device_Startup/system_saml22.o: \
+ ../Device_Startup/system_saml22.c \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
diff --git a/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.o b/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.o
new file mode 100644
index 00000000..b295d06e
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.o differ
diff --git a/Smol Watch Project/My Project/Debug/Makefile b/Smol Watch Project/My Project/Debug/Makefile
new file mode 100644
index 00000000..43608ce1
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/Makefile
@@ -0,0 +1,641 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+SHELL := cmd.exe
+RM := rm -rf
+
+USER_OBJS :=
+
+LIBS :=
+PROJ :=
+
+O_SRCS :=
+C_SRCS :=
+S_SRCS :=
+S_UPPER_SRCS :=
+OBJ_SRCS :=
+ASM_SRCS :=
+PREPROCESSING_SRCS :=
+OBJS :=
+OBJS_AS_ARGS :=
+C_DEPS :=
+C_DEPS_AS_ARGS :=
+EXECUTABLES :=
+OUTPUT_FILE_PATH :=
+OUTPUT_FILE_PATH_AS_ARGS :=
+AVR_APP_PATH :=$$$AVR_APP_PATH$$$
+QUOTE := "
+ADDITIONAL_DEPENDENCIES:=
+OUTPUT_FILE_DEP:=
+LIB_DEP:=
+LINKER_SCRIPT_DEP:=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+../Config/ \
+../Device_Startup/ \
+../documentation/ \
+../examples/ \
+../hal/ \
+../hal/documentation/ \
+../hal/include/ \
+../hal/src/ \
+../hal/utils/ \
+../hal/utils/include/ \
+../hal/utils/src/ \
+../hpl/ \
+../hpl/adc/ \
+../hpl/core/ \
+../hpl/dmac/ \
+../hpl/eic/ \
+../hpl/gclk/ \
+../hpl/mclk/ \
+../hpl/osc32kctrl/ \
+../hpl/oscctrl/ \
+../hpl/pm/ \
+../hpl/port/ \
+../hpl/rtc/ \
+../hpl/sercom/ \
+../hpl/slcd/ \
+../hpl/systick/ \
+../hpl/tcc/ \
+../hpl/tc/ \
+../hri/ \
+../sleep_manager/ \
+../watch-library
+
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../atmel_start.c \
+../Device_Startup/startup_saml22.c \
+../Device_Startup/system_saml22.c \
+../driver_init.c \
+../examples/driver_examples.c \
+../hal/src/hal_adc_sync.c \
+../hal/src/hal_atomic.c \
+../hal/src/hal_calendar.c \
+../hal/src/hal_delay.c \
+../hal/src/hal_ext_irq.c \
+../hal/src/hal_gpio.c \
+../hal/src/hal_i2c_m_sync.c \
+../hal/src/hal_init.c \
+../hal/src/hal_io.c \
+../hal/src/hal_pwm.c \
+../hal/src/hal_slcd_sync.c \
+../hal/src/hal_sleep.c \
+../hal/utils/src/utils_assert.c \
+../hal/utils/src/utils_event.c \
+../hal/utils/src/utils_list.c \
+../hal/utils/src/utils_syscalls.c \
+../hpl/adc/hpl_adc.c \
+../hpl/core/hpl_core_m0plus_base.c \
+../hpl/core/hpl_init.c \
+../hpl/dmac/hpl_dmac.c \
+../hpl/eic/hpl_eic.c \
+../hpl/gclk/hpl_gclk.c \
+../hpl/mclk/hpl_mclk.c \
+../hpl/osc32kctrl/hpl_osc32kctrl.c \
+../hpl/oscctrl/hpl_oscctrl.c \
+../hpl/pm/hpl_pm.c \
+../hpl/rtc/hpl_rtc.c \
+../hpl/sercom/hpl_sercom.c \
+../hpl/slcd/hpl_slcd.c \
+../hpl/systick/hpl_systick.c \
+../hpl/tcc/hpl_tcc.c \
+../hpl/tc/hpl_tc.c \
+../main.c \
+../sleep_manager/sleep_manager.c \
+../sleep_manager_main.c \
+../watch-library/watch.c
+
+
+PREPROCESSING_SRCS +=
+
+
+ASM_SRCS +=
+
+
+OBJS += \
+atmel_start.o \
+Device_Startup/startup_saml22.o \
+Device_Startup/system_saml22.o \
+driver_init.o \
+examples/driver_examples.o \
+hal/src/hal_adc_sync.o \
+hal/src/hal_atomic.o \
+hal/src/hal_calendar.o \
+hal/src/hal_delay.o \
+hal/src/hal_ext_irq.o \
+hal/src/hal_gpio.o \
+hal/src/hal_i2c_m_sync.o \
+hal/src/hal_init.o \
+hal/src/hal_io.o \
+hal/src/hal_pwm.o \
+hal/src/hal_slcd_sync.o \
+hal/src/hal_sleep.o \
+hal/utils/src/utils_assert.o \
+hal/utils/src/utils_event.o \
+hal/utils/src/utils_list.o \
+hal/utils/src/utils_syscalls.o \
+hpl/adc/hpl_adc.o \
+hpl/core/hpl_core_m0plus_base.o \
+hpl/core/hpl_init.o \
+hpl/dmac/hpl_dmac.o \
+hpl/eic/hpl_eic.o \
+hpl/gclk/hpl_gclk.o \
+hpl/mclk/hpl_mclk.o \
+hpl/osc32kctrl/hpl_osc32kctrl.o \
+hpl/oscctrl/hpl_oscctrl.o \
+hpl/pm/hpl_pm.o \
+hpl/rtc/hpl_rtc.o \
+hpl/sercom/hpl_sercom.o \
+hpl/slcd/hpl_slcd.o \
+hpl/systick/hpl_systick.o \
+hpl/tcc/hpl_tcc.o \
+hpl/tc/hpl_tc.o \
+main.o \
+sleep_manager/sleep_manager.o \
+sleep_manager_main.o \
+watch-library/watch.o
+
+OBJS_AS_ARGS += \
+atmel_start.o \
+Device_Startup/startup_saml22.o \
+Device_Startup/system_saml22.o \
+driver_init.o \
+examples/driver_examples.o \
+hal/src/hal_adc_sync.o \
+hal/src/hal_atomic.o \
+hal/src/hal_calendar.o \
+hal/src/hal_delay.o \
+hal/src/hal_ext_irq.o \
+hal/src/hal_gpio.o \
+hal/src/hal_i2c_m_sync.o \
+hal/src/hal_init.o \
+hal/src/hal_io.o \
+hal/src/hal_pwm.o \
+hal/src/hal_slcd_sync.o \
+hal/src/hal_sleep.o \
+hal/utils/src/utils_assert.o \
+hal/utils/src/utils_event.o \
+hal/utils/src/utils_list.o \
+hal/utils/src/utils_syscalls.o \
+hpl/adc/hpl_adc.o \
+hpl/core/hpl_core_m0plus_base.o \
+hpl/core/hpl_init.o \
+hpl/dmac/hpl_dmac.o \
+hpl/eic/hpl_eic.o \
+hpl/gclk/hpl_gclk.o \
+hpl/mclk/hpl_mclk.o \
+hpl/osc32kctrl/hpl_osc32kctrl.o \
+hpl/oscctrl/hpl_oscctrl.o \
+hpl/pm/hpl_pm.o \
+hpl/rtc/hpl_rtc.o \
+hpl/sercom/hpl_sercom.o \
+hpl/slcd/hpl_slcd.o \
+hpl/systick/hpl_systick.o \
+hpl/tcc/hpl_tcc.o \
+hpl/tc/hpl_tc.o \
+main.o \
+sleep_manager/sleep_manager.o \
+sleep_manager_main.o \
+watch-library/watch.o
+
+C_DEPS += \
+atmel_start.d \
+Device_Startup/startup_saml22.d \
+Device_Startup/system_saml22.d \
+driver_init.d \
+examples/driver_examples.d \
+hal/src/hal_adc_sync.d \
+hal/src/hal_atomic.d \
+hal/src/hal_calendar.d \
+hal/src/hal_delay.d \
+hal/src/hal_ext_irq.d \
+hal/src/hal_gpio.d \
+hal/src/hal_i2c_m_sync.d \
+hal/src/hal_init.d \
+hal/src/hal_io.d \
+hal/src/hal_pwm.d \
+hal/src/hal_slcd_sync.d \
+hal/src/hal_sleep.d \
+hal/utils/src/utils_assert.d \
+hal/utils/src/utils_event.d \
+hal/utils/src/utils_list.d \
+hal/utils/src/utils_syscalls.d \
+hpl/adc/hpl_adc.d \
+hpl/core/hpl_core_m0plus_base.d \
+hpl/core/hpl_init.d \
+hpl/dmac/hpl_dmac.d \
+hpl/eic/hpl_eic.d \
+hpl/gclk/hpl_gclk.d \
+hpl/mclk/hpl_mclk.d \
+hpl/osc32kctrl/hpl_osc32kctrl.d \
+hpl/oscctrl/hpl_oscctrl.d \
+hpl/pm/hpl_pm.d \
+hpl/rtc/hpl_rtc.d \
+hpl/sercom/hpl_sercom.d \
+hpl/slcd/hpl_slcd.d \
+hpl/systick/hpl_systick.d \
+hpl/tcc/hpl_tcc.d \
+hpl/tc/hpl_tc.d \
+main.d \
+sleep_manager/sleep_manager.d \
+sleep_manager_main.d \
+watch-library/watch.d
+
+C_DEPS_AS_ARGS += \
+atmel_start.d \
+Device_Startup/startup_saml22.d \
+Device_Startup/system_saml22.d \
+driver_init.d \
+examples/driver_examples.d \
+hal/src/hal_adc_sync.d \
+hal/src/hal_atomic.d \
+hal/src/hal_calendar.d \
+hal/src/hal_delay.d \
+hal/src/hal_ext_irq.d \
+hal/src/hal_gpio.d \
+hal/src/hal_i2c_m_sync.d \
+hal/src/hal_init.d \
+hal/src/hal_io.d \
+hal/src/hal_pwm.d \
+hal/src/hal_slcd_sync.d \
+hal/src/hal_sleep.d \
+hal/utils/src/utils_assert.d \
+hal/utils/src/utils_event.d \
+hal/utils/src/utils_list.d \
+hal/utils/src/utils_syscalls.d \
+hpl/adc/hpl_adc.d \
+hpl/core/hpl_core_m0plus_base.d \
+hpl/core/hpl_init.d \
+hpl/dmac/hpl_dmac.d \
+hpl/eic/hpl_eic.d \
+hpl/gclk/hpl_gclk.d \
+hpl/mclk/hpl_mclk.d \
+hpl/osc32kctrl/hpl_osc32kctrl.d \
+hpl/oscctrl/hpl_oscctrl.d \
+hpl/pm/hpl_pm.d \
+hpl/rtc/hpl_rtc.d \
+hpl/sercom/hpl_sercom.d \
+hpl/slcd/hpl_slcd.d \
+hpl/systick/hpl_systick.d \
+hpl/tcc/hpl_tcc.d \
+hpl/tc/hpl_tc.d \
+main.d \
+sleep_manager/sleep_manager.d \
+sleep_manager_main.d \
+watch-library/watch.d
+
+OUTPUT_FILE_PATH +=My\ Project.elf
+
+OUTPUT_FILE_PATH_AS_ARGS +="My Project.elf"
+
+ADDITIONAL_DEPENDENCIES:=
+
+OUTPUT_FILE_DEP:= ./makedep.mk
+
+LIB_DEP+=
+
+LINKER_SCRIPT_DEP+= \
+../Device_Startup/saml22j18a_flash.ld \
+../Device_Startup/saml22j18a_sram.ld
+
+
+# AVR32/GNU C Compiler
+./atmel_start.o: .././atmel_start.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+Device_Startup/startup_saml22.o: ../Device_Startup/startup_saml22.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+Device_Startup/system_saml22.o: ../Device_Startup/system_saml22.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+./driver_init.o: .././driver_init.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+examples/driver_examples.o: ../examples/driver_examples.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_adc_sync.o: ../hal/src/hal_adc_sync.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_atomic.o: ../hal/src/hal_atomic.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_calendar.o: ../hal/src/hal_calendar.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_delay.o: ../hal/src/hal_delay.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_ext_irq.o: ../hal/src/hal_ext_irq.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_gpio.o: ../hal/src/hal_gpio.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_i2c_m_sync.o: ../hal/src/hal_i2c_m_sync.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_init.o: ../hal/src/hal_init.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_io.o: ../hal/src/hal_io.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_pwm.o: ../hal/src/hal_pwm.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_slcd_sync.o: ../hal/src/hal_slcd_sync.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/src/hal_sleep.o: ../hal/src/hal_sleep.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/utils/src/utils_assert.o: ../hal/utils/src/utils_assert.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/utils/src/utils_event.o: ../hal/utils/src/utils_event.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/utils/src/utils_list.o: ../hal/utils/src/utils_list.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hal/utils/src/utils_syscalls.o: ../hal/utils/src/utils_syscalls.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/adc/hpl_adc.o: ../hpl/adc/hpl_adc.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/core/hpl_core_m0plus_base.o: ../hpl/core/hpl_core_m0plus_base.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/core/hpl_init.o: ../hpl/core/hpl_init.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/dmac/hpl_dmac.o: ../hpl/dmac/hpl_dmac.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/eic/hpl_eic.o: ../hpl/eic/hpl_eic.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/gclk/hpl_gclk.o: ../hpl/gclk/hpl_gclk.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/mclk/hpl_mclk.o: ../hpl/mclk/hpl_mclk.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/osc32kctrl/hpl_osc32kctrl.o: ../hpl/osc32kctrl/hpl_osc32kctrl.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/oscctrl/hpl_oscctrl.o: ../hpl/oscctrl/hpl_oscctrl.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/pm/hpl_pm.o: ../hpl/pm/hpl_pm.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/rtc/hpl_rtc.o: ../hpl/rtc/hpl_rtc.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/sercom/hpl_sercom.o: ../hpl/sercom/hpl_sercom.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/slcd/hpl_slcd.o: ../hpl/slcd/hpl_slcd.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/systick/hpl_systick.o: ../hpl/systick/hpl_systick.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/tcc/hpl_tcc.o: ../hpl/tcc/hpl_tcc.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+hpl/tc/hpl_tc.o: ../hpl/tc/hpl_tc.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+./main.o: .././main.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+sleep_manager/sleep_manager.o: ../sleep_manager/sleep_manager.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+./sleep_manager_main.o: .././sleep_manager_main.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+watch-library/watch.o: ../watch-library/watch.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+
+
+
+# AVR32/GNU Preprocessing Assembler
+
+
+
+# AVR32/GNU Assembler
+
+
+
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+# All Target
+all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
+
+$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
+ @echo Building target: $@
+ @echo Invoking: ARM/GNU Linker : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="My Project.map" --specs=nano.specs -Wl,--start-group -lm -Wl,--end-group -L"..\\Device_Startup" -Wl,--gc-sections -mcpu=cortex-m0plus -Tsaml22j18a_flash.ld
+ @echo Finished building target: $@
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O binary "My Project.elf" "My Project.bin"
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature "My Project.elf" "My Project.hex"
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O binary "My Project.elf" "My Project.eep" || exit 0
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objdump.exe" -h -S "My Project.elf" > "My Project.lss"
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature "My Project.elf" "My Project.srec"
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-size.exe" "My Project.elf"
+
+
+
+
+
+
+
+# Other Targets
+clean:
+ -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)
+ -$(RM) $(C_DEPS_AS_ARGS)
+ rm -rf "My Project.elf" "My Project.a" "My Project.hex" "My Project.bin" "My Project.lss" "My Project.eep" "My Project.map" "My Project.srec"
+
\ No newline at end of file
diff --git a/Smol Watch Project/My Project/Debug/My Project.bin b/Smol Watch Project/My Project/Debug/My Project.bin
new file mode 100644
index 00000000..bbfb5682
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/My Project.bin differ
diff --git a/Smol Watch Project/My Project/Debug/My Project.eep b/Smol Watch Project/My Project/Debug/My Project.eep
new file mode 100644
index 00000000..e69de29b
diff --git a/Smol Watch Project/My Project/Debug/My Project.elf b/Smol Watch Project/My Project/Debug/My Project.elf
new file mode 100644
index 00000000..14870a6f
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/My Project.elf differ
diff --git a/Smol Watch Project/My Project/Debug/My Project.hex b/Smol Watch Project/My Project/Debug/My Project.hex
new file mode 100644
index 00000000..06e00b46
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/My Project.hex
@@ -0,0 +1,537 @@
+:1000000020210020210100001D0100001D01000031
+:1000100000000000000000000000000000000000E0
+:100020000000000000000000000000001D010000B2
+:1000300000000000000000001D0100001D01000084
+:100040001D0100001D010000890E0000350C00009C
+:100050001D0100001D0100001D0100001D01000028
+:100060001D0100001D0100001D0100001D01000018
+:100070001D0100000000000000000000AD150000A0
+:100080001D0100001D0100001D010000E519000018
+:100090001D0100001D0100001D0100001D010000E8
+:1000A0001D0100001D01000010B5064C2378002B37
+:1000B00007D1054B002B02D0044800E000BF01230C
+:1000C000237010BD38000020000000004021000017
+:1000D000084B10B5002B03D00749084800E000BFCB
+:1000E00007480368002B00D110BD064B002BFBD046
+:1000F0009847F9E7000000003C0000204021000084
+:10010000402100000000000010B5024B9847024B50
+:10011000984710BD090300008D1B0000FEE700009A
+:1001200010B5104A104B9A4209D00F4B0D4A03E00C
+:1001300011681960043304320C498B42F8D30C4B1C
+:1001400002E000221A6004330A4A9342F9D30A4AB1
+:10015000FF210A4B8B439360094B9847094B984703
+:10016000FEE7C046402100000000002038000020CB
+:10017000380000201C01002000ED00E0000000001D
+:10018000B11E0000F9190000034A516980239B0049
+:100190000B4353617047C0460008004010B5034B45
+:1001A000984703490348044B984710BD8901000054
+:1001B00000240040B4000020B506000070B5134BC9
+:1001C000DE20195C042291431954195C0125A943CE
+:1001D00001242143C9B219541F38195C0F26B143B9
+:1001E00002263143C9B21954DF215E5C96435E5446
+:1001F0005A5CAA432243D2B25A541A5CD0390A40FC
+:1002000020210A43D2B21A5470BDC046006000419A
+:10021000064B4021C42299500331083A9950044AB0
+:10022000D3693F390B43D3617047C046001C00407F
+:100230000008004010B5044B984704490448054B9A
+:100240009847054B984710BD110200000008004276
+:10025000F8000020A9080000BD01000010B5024808
+:10026000024B984710BDC04610E000E02D0800008A
+:1002700030B50F4B5422995C0125A9430124214339
+:10028000C9B299543A20195C453A9143042211436A
+:10029000C9B2195455215A5CAA432243D2B25A54C6
+:1002A0001A5C46390A4040210A43D2B21A5430BD82
+:1002B00000600041054AD16980231B010B43D361D3
+:1002C0004021E023024AD1507047C0460008004058
+:1002D000001C004010B5064B9847064B9847064B4C
+:1002E0009847020005490648064B984710BDC0468E
+:1002F000B502000071020000D9190000002C004274
+:100300009000002099090000F0B5C64600B51C4BCE
+:100310009847C022D205042454601A4B1A499962A6
+:100320001A49996254604220195C04252943C9B2D4
+:10033000195454611C5C01218C431C549427D151E5
+:10034000882691516630124C1C50C0242406A046C9
+:100350001C50C024A4461C5D8C4365465C55082493
+:10036000D45194510B4A1A5042461A501B301A5C11
+:100370008A431A54084B984704BC9046F0BDC046C7
+:100380003D0B00000060004104000240000002C07C
+:1003900001000040080000405D020000830701D119
+:1003A000012070470020FCE710B50C0080B2104B14
+:1003B000984700280BD00C2C03D8A4000D4B1B59D8
+:1003C0009F46002010E00C480EE00C480CE00C2C7E
+:1003D00003D8A4000A4B1B599F46002004E009489B
+:1003E00002E0064800E0084810BD0748FCE7C046A8
+:1003F0009D030000F81E0000803B2600008D2700B2
+:100400002C1F000000EA240080DE2800F0B5C6465C
+:1004100000B50C009046866904E01F4B9C4209D34E
+:10042000E41A0136B7B238001C4B98470028F4D0C4
+:100430001B4BF3E70125290030001A4B98478442F3
+:1004400003D3241A0135EDB2F5E70121164B9C4286
+:1004500005D9164B9C4664440131C9B2F6E7002227
+:10046000134B9C4205D9134B9C4664440132D2B2D3
+:10047000F6E700233B2C03D93C3C0133DBB2F9E720
+:100480004046C7804571017182704370047000203E
+:1004900004BC9046F0BDC0468033E1019D030000DE
+:1004A0000085E201A90300007F51010080AEFEFF3C
+:1004B0000F0E0000F0F1FFFFF0B5DE4657464E4646
+:1004C0004546E0B583B0CB880093DEB28369994698
+:1004D0006A4613711379F61AF6B24F790B799A4678
+:1004E0008B7898464B789B460B7801930025002427
+:1004F00003E01A4B9C4664440135B5420AD24B4690
+:10050000581980B2164B98470028F2D0154B9C46DC
+:100510006444F1E7012505E0E9B20098124B9847E1
+:1005200024180135BD42F7D35346013B0F485843C9
+:100530002418E12000014346584320185B461B0164
+:100540005A469B1A9C000019019B9C46604403B0CC
+:100550003CBC90469946A246AB46F0BD8033E101D3
+:100560009D0300000085E201A90300008051010005
+:1005700070B50C00D068CD680B7C052B06D89B00AD
+:100580001549CB589F46A84200D33C35E56070BD65
+:10059000A842FBD3E1231B019C466544F6E7A84231
+:1005A000F4D30E4B9C466544F0E7A842EED3508945
+:1005B000517A0B4B98472D18E8E7A842E6D35089AB
+:1005C000084B9847002803D1074B9C466544DDE75C
+:1005D000064B9C466544D9E7601F0000805101002E
+:1005E000A90300009D0300008033E1010085E201C2
+:1005F00070B586B005000C00294B9847060001AA8B
+:1006000001002800274B98470396237C052B12D81E
+:100610009B00254AD3589F466B465B8963816B4696
+:100620005B7A63726B461B7A23726B469B79A3716C
+:100630006B465B796371261D310028001B4B984780
+:10064000E0606A4621002800194B9847E1683200B3
+:100650002800144B984706B070BD6B465B896381D8
+:100660006B465B7A63726B461B7A23726B469B798F
+:10067000A371E0E76B465B8963816B465B7A6372CB
+:100680006B461B7A2372D6E76B465B8963816B46A8
+:100690005B7A6372CFE76B465B896381CBE7C046C9
+:1006A000550E00000D040000781F0000B904000082
+:1006B0007105000070B504000D00431E9841C0B2E2
+:1006C000E022520009490A4B98472368AB4208D000
+:1006D000002B08D125602000064B9847064BA361EC
+:1006E00070BD0020FCE712204042F9E7901F000097
+:1006F000690A0000490D0000B207000010B50400AF
+:10070000431E9841C0B2E622FF320449044B984789
+:100710002000044B9847002010BDC046901F0000E9
+:10072000690A0000D90D000030B583B004000D0047
+:10073000431E9841C0B2832292000E490E4B984747
+:1007400020000E4B984701006A4620000C4B98474A
+:100750002B786A4613706B785370AB789370694648
+:100760002000084B984701002000074B98470020C5
+:1007700003B030BD901F0000690A0000550E000054
+:100780000D040000B90400001D0E000030B583B058
+:1007900004000D00431E9841C0B2892292000E4908
+:1007A0000E4B984720000E4B984701006A462000E8
+:1007B0000C4B98472B786A4613716B7853716B8892
+:1007C000D38069462000084B984701002000074B62
+:1007D0009847002003B030BD901F0000690A000058
+:1007E000550E00000D040000B90400001D0E0000AD
+:1007F00070B504000D00431E9841C0B2064A074977
+:10080000074B98472000074B984701002A0020001B
+:10081000054B9847002070BD3B020000901F000070
+:10082000690A0000550E00000D04000010B5024BCF
+:100830001860024B984710BD54000020711500004D
+:1008400010B584B01438848B01AB1C801400029264
+:10085000064A5A8003911900054B9847002802D197
+:10086000200004B010BD0400FAE7C0460080FFFF7E
+:10087000E112000010B584B01438848B01AB1C80E9
+:1008800014000292064A5A8003911900054B9847BA
+:10089000002802D1200004B010BD0400FAE7C046D1
+:1008A0000180FFFFE112000070B504000D00431E3F
+:1008B0009841C0B25E220749074B984729002000A3
+:1008C000064B9847002803D1054BA361054B636194
+:1008D00070BDC046AC1F0000690A00003112000064
+:1008E000750800004108000010B5014B984710BD85
+:1008F000611200008905890D8023DB001A400A433C
+:100900008283100070471430086000207047000098
+:1009100070B504000D00160000280ED000290AD082
+:10092000012034220649074B9847236832002900EA
+:100930002000984770BD0020F3E70020F1E7C04693
+:10094000C81F0000690A000070B504000D00160001
+:1009500000280ED000290AD001203D220649074B6D
+:1009600098476368320029002000984770BD002036
+:10097000F3E70020F1E7C046C81F0000690A000045
+:1009800010B54369002B00D0984710BD10B583699E
+:10099000002B00D0984710BD70B504000D00160064
+:1009A000002815D0002915D0002A0FD001203322AD
+:1009B00009490A4B9847E6613368290020009847A7
+:1009C000074B2360074B6360002070BD0020EEE7FB
+:1009D0000020ECE70020EAE7DC1F0000690A0000C5
+:1009E000810900008D09000010B5041E15D0C369EF
+:1009F000002B10D001204B220A490B4B9847E3698A
+:100A00005B6920009847002809D1E3699B682000B2
+:100A10009847002010BD0020EDE70020EBE71120F3
+:100A20004042F7E7DC1F0000690A000070B50400CF
+:100A30000D001600002811D0C369002B0CD0012036
+:100A40007D220749074B9847E3691B69320029005B
+:100A500020009847002070BD0020F1E70020EFE75C
+:100A6000DC1F0000690A0000002800D100BE7047AA
+:100A7000F8B505001700CE0807230B4001249C4061
+:100A8000E4B200281ED0002A1ED007291ED900205B
+:100A900031221449144B9847AB191B7923421ED1BC
+:100AA00029001248124B9847002811D0AF60AD19A9
+:100AB0002B7923432B710D4B9B191A7914431C710D
+:100AC0000020F8BD0020E3E70020E1E70120DFE798
+:100AD00000232B7129000548064B9847E6E70220C2
+:100AE0004042EEE7F41F0000690A000058000020B1
+:100AF000F90A0000110B00000368002B03D08B42A1
+:100B000003D01B68F9E7002070470120FCE70000D4
+:100B100070B504000D00064B984701235840C0B241
+:100B200039220449044B984723682B60256070BD27
+:100B3000F90A000014200000690A000010B5094BF2
+:100B40005A685A600220084B9847084B9847084B50
+:100B50009847084B9847084B98471F20074B9847E2
+:100B600010BDC04600400041E90C0000890C0000A7
+:100B7000AD0C0000790C0000E50C0000410C0000F9
+:100B8000F0B583B0254B5A690192019A5A61244B02
+:100B90001868431E9841C0B2DA222249224B984776
+:100BA00001256D422FE0DB00204AD3185D686B1CE5
+:100BB00003D01B4B1B68280098470122A240019BD1
+:100BC0009343019301981A4B9847013844B2631C30
+:100BD00014D00326002001E00139CEB2B042E6D89D
+:100BE00033185B10D9B2FF221340DF000F4ABA5C02
+:100BF000A242D8D0F0DA0131C8B2EFE7074B5A6908
+:100C00000192019A5A61019B002B05D00198084B73
+:100C10009847013844B2DAE703B0F0BD002800403D
+:100C2000600000204C200000690A00003420000011
+:100C30005D1E000010B5014B984710BD810B0000F0
+:100C4000C30707D5094A0A4B1A62094B5B687D2224
+:100C50001A42FAD1030707D5064A054BDA62044B5C
+:100C60005B687D221A42FAD17047C0460501010037
+:100C7000001C004004230100024B08229A71073A2D
+:100C80001A71704700080040074A9E239382002390
+:100C90009375D375D3691B0A1B02F82149010B40D8
+:100CA000D3610423137470470014004082220C4B5C
+:100CB0001A7538230A4AD35C9B07FAD4084BDB68C1
+:100CC000DB06FBD5064A137D802149420B43DBB28C
+:100CD00013753823024AD25C2A3B1A42F9D1704775
+:100CE0000010004070470000094B9B78032213401E
+:100CF00098420CD0064AFF239371937803218B43CB
+:100D0000084018439070024B9B79002BFBD0704732
+:100D10000004004010B504000268918953890B401B
+:100D2000DA0502D45B0407D410BD436898472368F2
+:100D3000802252009A81F7E78368984723688022CF
+:100D4000D2019A81F0E7000010B5041E37D0036885
+:100D5000002B32D001202F221A491B4B98471B4BE6
+:100D60001C6021680A691A4B1A42FBD10B889B0749
+:100D70000BD50B88022293430B800A69144B1A424D
+:100D8000FBD1226813699B07FCD4226813880121D8
+:100D90000B439BB213801369DB07FCD423681A69E9
+:100DA000D207FCD40B4A1A801969094A1142FBD1B7
+:100DB000236800221A66002010BD0020CBE7002027
+:100DC000C9E7C04664200000690A000064000020F2
+:100DD00003800000008BFFFF10B5041E15D00368D0
+:100DE000002B10D00120732209490A4B9847216833
+:100DF0000B88022213439BB20B800A69064B1A42EE
+:100E0000FBD1002010BD0020EDE70020EBE7C0463D
+:100E100064200000690A00000380000070B504002F
+:100E20000D00002810D00368002B0BD001208B226E
+:100E30000649074B98472268956113691B07FCD444
+:100E4000002070BD0020F2E70020F0E764200000E1
+:100E5000690A000010B5041E0FD00368002B0AD0E9
+:100E6000012097220649074B9847226813691B0700
+:100E7000FCD4906910BD0020F3E70020F1E7C046E4
+:100E800064200000690A000010B5024B1868024B8C
+:100E9000984710BD64000020150D0000024B9C46D1
+:100EA0006044800AC0B2704700FCFFBD10B50D4B16
+:100EB00098470023002B08D0E62292000A49002020
+:100EC0000A4B98470120404210BD5A00D218D10069
+:100ED000074A5218127D904202D00133DBB2E9E793
+:100EE00058B2F1E79D0E0000CC200000690A000016
+:100EF0007C20000070B505000C0008002D4B9847C1
+:100F0000C0B2E369DB071DD443001B18DA002A4B8B
+:100F10009B189A691C231A40E3699B07FCD123683C
+:100F20009B0709D5236802218B432360E3699B0754
+:100F3000FCD1E3699B07FCD4012313432360E369DD
+:100F40009B07FCD1E369DB07FCD443001B18DA00E4
+:100F5000194B9B189B692360E3699B07FCD14300F5
+:100F60001B18DA00144B9B18DB696360E3695B07AD
+:100F7000FCD442001218D1000F4B5B181A6AE260D1
+:100F8000DA7E03231A40AA81023B93429B415B42D3
+:100F9000626A0A490A409B0313436362E3695B0781
+:100FA000FCD443001818C200034B9B18DB8CEB8168
+:100FB000002070BDAD0E00007C200000FFBFFFFFD1
+:100FC00070B5050004692368DB0E01261E40431E30
+:100FD0009841C0B28E4A8F498F4B98476B68012B5E
+:100FE0004DD063688D4A13406360E3695B07FCD4AE
+:100FF0002B885A054ED56A88D20704D56A88802185
+:10100000C9000A436A805B00854A1A40E3695B07AE
+:10101000FCD4636A8021C9010B4013438022120271
+:1010200013436362E3695B07FCD42E697D4A337E18
+:10103000DBB21800511E002A02D00A009B07F6D02E
+:101040002368DB0E01221A40E3695B07FCD4638B43
+:101050009BB2C10700D48FE09A072FD501222276D8
+:101060006A88802149010A436A806A886E490A4079
+:101070006A80DB0700D4C6E005204042A2E0002ED3
+:10108000AFD062688023DB0213436360E3695B07D0
+:10109000FCD4ADE75B00FF2213406A8801210A40BF
+:1010A0001A43E3695B07FCD4636A8021C9010B40E2
+:1010B00013436362E3695B07FCD4B6E75B071BD4A9
+:1010C0006B885B0534D52A881212520006231A4019
+:1010D000E3695B07FCD4636A8021C9010B401343B9
+:1010E000F12213436362E3695B07FCD46B884F4AC8
+:1010F00013406B80002065E06B68002B04DD6B887B
+:101100008022520113436B806B881BB2002B06DBDD
+:101110006B88454A13406B800220404252E062686F
+:10112000C0239B0213436360E3695B07FCD4EFE7D2
+:101130006868002811D16B881BB2002B04DB6B8818
+:10114000394A13406B803DE06268C0239B02134321
+:101150006360E3695B07FCD4F1E7AB681A78282386
+:10116000E254E3695B07FCD4AB680133AB606B68A6
+:10117000013B6B60002025E0810747D569680029A5
+:101180003CD05B073AD401396960002901D1002ABB
+:101190001BD0012917D06B68002B07D16B881BB2BD
+:1011A000002B1BDB6B88204A13406B80AA68531C02
+:1011B000AB60E3695B07FCD42823E35C1370022374
+:1011C0002376002070BD002AE5D062688023DB0210
+:1011D00013436360E3695B07FCD4DCE76368124A8E
+:1011E00013406360E3695B07FCD46268C0239B0221
+:1011F00013436360E3695B07FCD4D3E702232376E0
+:1012000002204042DEE704204042DBE70020D9E72D
+:1012100094050000CC200000690A0000FFFFFBFFDE
+:10122000FE070000FFFF0000FFFEFFFFFFFBFFFFC8
+:1012300070B504000D00431E9841C0B2044A054930
+:10124000054B9847256129002000044B984770BD45
+:1012500007050000CC200000690A0000F50E000020
+:1012600070B50400194D431E9841C0B2184A2900B8
+:10127000184EB04724692000431E9841C0B2164A58
+:101280002900B0472368022213432360E3699B07C8
+:10129000FCD104201149E3695B07FCD4628B12097D
+:1012A00003231340012B0BD001390029F3DC013853
+:1012B000002807D010236383E3695B07FCD4E9E7C8
+:1012C000002070BD06204042FBE7C046CC20000055
+:1012D00024050000690A0000F4050000FFFF00007B
+:1012E000F8B505000E000469431E9841C0B2934A48
+:1012F0009349944FB8472869431E9841C0B2B82219
+:10130000D2008F49B8473000431E9841C0B28E4A80
+:101310008B49B8476B88DB0500D50BE172888023C9
+:101320005B009C461A4372802A00310089C989C239
+:101330006268634613436360E3695B07FCD428007B
+:10134000824B9847002800D19DE06B88804A13406B
+:101350006B80F8BD05204042A6E073881BB2002BCD
+:1013600004DB6B887A4A13406B80F2E76268C02323
+:101370009B0213436360E3695B07FCD4F1E7530707
+:101380001BD46B885B0534D52A88121252000623C1
+:101390001A40E3695B07FCD4636A8021C9010B40F2
+:1013A0001343F12213436362E3695B07FCD46B8848
+:1013B000684A13406B80002065E06B68002B04DDF9
+:1013C0006B888022520113436B806B881BB2002B09
+:1013D00006DB6B885E4A13406B800220404252E07D
+:1013E0006268C0239B0213436360E3695B07FCD41C
+:1013F000EFE76868002811D16B881BB2002B04DB73
+:101400006B88534A13406B803DE06268C0239B02A7
+:1014100013436360E3695B07FCD4F1E7AB681A78B8
+:101420002823E254E3695B07FCD4AB680133AB606B
+:101430006B68013B6B60002025E0BB0778D56B68CB
+:10144000002B6DD052076BD4013B6B60002B01D198
+:1014500000294CD0012B48D06B68002B07D16B883A
+:101460001BB2002B4CDB6B88394A13406B80AA6897
+:10147000531CAB60E3695B07FCD42823E35C137067
+:101480000223237600206B88DB0500D461E72869FE
+:10149000314A037EDBB21F00511E002A00D159E7FA
+:1014A0000A009B07F5D00020002800D055E72368EC
+:1014B000DB0E01211940E3695B07FCD4628B92B219
+:1014C000FB07BAD5930700D459E7012323766B882D
+:1014D000802149010B436B806B881D490B406B8059
+:1014E000D30722D505204042CDE70029B4D0626859
+:1014F0008023DB0213436360E3695B07FCD4ABE743
+:101500006368134A13406360E3695B07FCD4626855
+:10151000C0239B0213436360E3695B07FCD4A2E72B
+:101520000223237602204042ADE704204042AAE78E
+:101530000020A8E7062040420BE7C046BF05000098
+:10154000CC200000690A0000C1050000C10F0000A6
+:10155000FFFEFFFFFFFBFFFFFFFF0000024B034A00
+:101560005A6005221A60704710E000E0FFFFFF009C
+:1015700010B5014B984710BD5D15000070B5050012
+:101580000469E36ADB0705D50123E3620368002BE6
+:1015900000D09847A36A1B0706D50823E3626B684F
+:1015A000002B01D02800984770BD000010B5024BF9
+:1015B0001868024B984710BD680000207D15000098
+:1015C0000269136802210B43136013699B07FCD166
+:1015D00070470269136802218B43136013699B07EC
+:1015E000FCD17047026913699B07FCD113685B0843
+:1015F00001201840704770B505000469A37ADB0725
+:1016000005D50123A3720368002B00D09847637AA5
+:101610009B0706D50223A3726B68002B01D028001C
+:10162000984770BD034B984200D07047024B196039
+:10163000FBE7C046002C00426C00002010B50E4BAA
+:101640009C466044800AC3B20020002808D0B02223
+:1016500052000A4900200A4B98470120404210BD21
+:10166000820012189100074A8A5C9A4202D0013027
+:10167000C0B2EAE740B2F2E700E0FFBDE8200000B8
+:10168000690A00000000002070B506000C00080088
+:10169000534B9847050034612369DB0714D4236951
+:1016A0009B07FCD123689B0709D52368022293433B
+:1016B000236023699B07FCD123699B07FCD401238A
+:1016C000236023699B07FCD12369DB07FCD4AB00B3
+:1016D0005B199A00434B9B185B68236023699B0747
+:1016E000FCD1AA00521991003E4B5B189A7AE27322
+:1016F0001A89E280032222735A680C231340082BB4
+:1017000054D0002B66D1AB005B199A00354B9B1867
+:101710009B89A3832369C0221A42FBD1AB005B19CA
+:101720009A00304B9B181B8AE3832369C0221A421C
+:10173000FBD1310020002C4B9847AB005B199A007D
+:10174000284B9B185B785BB2002B0BDB1F221340EE
+:101750001E3A9A401300802224498B50BFF34F8FCA
+:10176000BFF36F8FAB005B199A001E4B9B185B7821
+:101770005BB2002B08DB1F2213401E3A9A40130075
+:10178000C022520019498B50AB005D19AA00154BBD
+:101790009B185B785BB2002B1FDB1F2213401E3AA5
+:1017A0009A401300114A1360002070BD0D4B5B1866
+:1017B000DB68E3612369C0221A42FBD1AB005B19ED
+:1017C0009A00084B9B181B6923622369C0221A42A6
+:1017D000FBD1AEE701204042E7E70020E5E7C04645
+:1017E0003D160000000000202516000000E100E08A
+:1017F00070B50E001500046920001B4B984782004D
+:1018000012189100194B5B18DE601D615A680C2399
+:101810001340082B16D083001B189A00134B9B18FB
+:101820009B89A3832369C0221A42FBD18300181825
+:1018300082000E4B9B181B8AE3832369C0221A4245
+:10184000FBD170BDE6612369C0221A42FBD183003F
+:1018500018188200054B9B181B6923622369C0225C
+:101860001A42FBD1EDE7C0463D1600000000002003
+:1018700010B5046920000C4B9847830018188200AB
+:101880000A4B9B185A680C231340082B06D0236977
+:10189000C0221A42FBD1A08B80B210BD2369C022A6
+:1018A0001A42FBD1E069F8E73D1600000000002075
+:1018B00010B504692000144B984783001818820063
+:1018C000124B9B185A680C231340082B11D0236924
+:1018D000C0221A42FBD1A18B89B22369C0221A42CD
+:1018E000FBD1E38B9BB2FA2080005843084B98470A
+:1018F00010BD2369C0221A42FBD1E1692369C022CD
+:101900001A42FBD1236AEEE73D16000000000020DA
+:10191000451D000070B504692000164B984705006E
+:10192000C22215490120154B9847A8004019820092
+:10193000134B9B185B785BB2002B0BDB1F22134011
+:101940001E3A9A40130080220E498B50BFF34F8FEE
+:10195000BFF36F8F236802229343236023699B07A1
+:10196000FCD123680122134323602369DB07FCD4E5
+:1019700070BDC0463D160000E8200000690A000066
+:101980000000002000E100E070B504000E0015002A
+:10199000431E9841C0B21822FF320D490D4B9847A3
+:1019A000002E08D12369002D02D101221A7204E011
+:1019B00001225A7201E0012E00D070BD2369002D72
+:1019C00002D002225A72F8E702221A72F5E7C046E4
+:1019D000E8200000690A0000014814307047C04642
+:1019E0000000002010B5024B1868024B984710BD4C
+:1019F0006C000020F715000030B58BB0234B9847E2
+:101A000002AC234BE3800423637119222271A3707B
+:101A100000256570257004A81E4B98471E4B9847FB
+:101A20001E4B9847029861681D4B984724201D4B18
+:101A3000984710219823C022D205D1501A4B9847BD
+:101A40006B46DC1DDD71991DD0230B7001227720C0
+:101A5000164B9847012221007720154B9847237891
+:101A6000602B01D1134B984702AB1C7801E0114B5E
+:101A70009847250002AC20000F4B98472478A542D8
+:101A8000F8D0E307F3D40D4B9847F2E709010000C3
+:101A9000E5070000B11B0000B51B0000191C000089
+:101AA000351C0000751C0000B91C0000E51C00007E
+:101AB000151D0000051C0000611C0000F11B00004A
+:101AC00070B582B00E00002813D1164B1D680CE0D3
+:101AD000737801AC63700123237020006B68984712
+:101AE00032782378134033702D68002DF0D102B086
+:101AF00070BD022804D00128F9D10A4B9C680DE082
+:101B0000084B5C6803E0F0B2636898472468002CD7
+:101B1000F9D1ECE7F0B2636898472468002CF9D15A
+:101B2000E5E7C0467000002070B5084E084C0C3444
+:101B3000320001212000074DA8473200002120007B
+:101B4000A847320002212000A84770BDC11A00003A
+:101B500070000020710A000010B50400431E984177
+:101B6000C0B240220349044B984721000348044B6C
+:101B7000984710BDFC200000690A0000700000209A
+:101B8000110B0000002303707047000010B5044BD8
+:101B900098470448044B4360044B984710BDC04627
+:101BA000291B000088000020851B0000591B000035
+:101BB0007047000010B5064B9847064C00220649B6
+:101BC0002000064B98472000054B984710BDC046A3
+:101BD000D502000090000020102700002D0A000010
+:101BE000E9090000014B9883D9837047002C00421B
+:101BF00010B500210148024B984710BDFFFF0000BF
+:101C0000E51B000010B502490020024B984710BDAB
+:101C1000FFFF0000E51B000010B5034B9847034889
+:101C2000034B984710BDC0469D010000B400002042
+:101C3000FD06000010B582B000900191054C01A98D
+:101C40002000054B984769462000044B984702B096
+:101C500010BDC046B40000208D0700002907000019
+:101C600010B501000148024B984710BDB400002098
+:101C7000F107000070B543091F2404400125290025
+:101C8000A140DA01C020C005101881600E04360C96
+:101C90008020C0053043074EB44662449062090C70
+:101CA000C020000601439162101940300378AB4315
+:101CB000037070BD0060004110B5054B9847054C9E
+:101CC00005492000054B98472000054B984710BD5B
+:101CD00035020000F800002018010020070900006C
+:101CE000E908000070B50C00150080221201010007
+:101CF0000448054B9847054B18682A002100044BFF
+:101D0000984770BDF8000020F50800001801002079
+:101D10001109000070B50C001500802212010100AD
+:101D20000448054B9847054B18682A002100044BCE
+:101D3000984770BDF8000020F50800001801002049
+:101D400049090000002243088B4274D303098B42E7
+:101D50005FD3030A8B4244D3030B8B4228D3030C7B
+:101D60008B420DD3FF22090212BA030C8B4202D31D
+:101D70001212090265D0030B8B4219D300E0090A45
+:101D8000C30B8B4201D3CB03C01A5241830B8B424E
+:101D900001D38B03C01A5241430B8B4201D34B0337
+:101DA000C01A5241030B8B4201D30B03C01A52419C
+:101DB000C30A8B4201D3CB02C01A5241830A8B4221
+:101DC00001D38B02C01A5241430A8B4201D34B020A
+:101DD000C01A5241030A8B4201D30B02C01A52416E
+:101DE000CDD2C3098B4201D3CB01C01A5241830922
+:101DF0008B4201D38B01C01A524143098B4201D35C
+:101E00004B01C01A524103098B4201D30B01C01A86
+:101E10005241C3088B4201D3CB00C01A5241830800
+:101E20008B4201D38B00C01A524143088B4201D32D
+:101E30004B00C01A5241411A00D20146524110468D
+:101E40007047FFE701B5002000F006F802BDC0466C
+:101E50000029F7D076E770477047C04610B50023D9
+:101E6000002802D000F004F8431C180010BDC04642
+:101E7000414208401C2101231B04984201D3000C5D
+:101E800010391B0A984201D3000A08391B099842ED
+:101E900001D30009043902A2105C401A7047C04601
+:101EA0001B1C1D1D1E1E1E1E1F1F1F1F1F1F1F1F51
+:101EB00070B500260C4D0D4C641BA410A64209D130
+:101EC000002600F02DF90A4D0A4C641BA410A6420E
+:101ED00005D170BDB300EB5898470136EEE7B3006B
+:101EE000EB5898470136F2E72C2100002C21000026
+:101EF0002C21000030210000C2030000E603000096
+:101F0000C6030000E6030000CA030000E603000069
+:101F1000CA030000E6030000E6030000CA03000055
+:101F2000E6030000CA030000E6030000DA03000035
+:101F3000EA030000DE030000EA030000E203000001
+:101F4000EA030000E2030000EA030000EA030000E5
+:101F5000E2030000EA030000E2030000EA030000DD
+:101F60008C05000086050000900500009E0500001D
+:101F7000AA050000BA050000360600001806000099
+:101F80005A0600007406000088060000960600004D
+:101F90002E2E2F68616C2F7372632F68616C5F63E4
+:101FA000616C656E6461722E630000002E2E2F68D6
+:101FB000616C2F7372632F68616C5F6932635F6D50
+:101FC0005F73796E632E63002E2E2F68616C2F7302
+:101FD00072632F68616C5F696F2E63002E2E2F680D
+:101FE000616C2F7372632F68616C5F70776D2E6305
+:101FF000000000002E2E2F68616C2F7574696C73C1
+:102000002F7372632F7574696C735F6576656E7478
+:102010002E6300002E2E2F68616C2F7574696C730F
+:102020002F7372632F7574696C735F6C6973742E90
+:10203000630000000500000025000000060000000D
+:102040001600000007000000170000002E2E2F6869
+:10205000706C2F6569632F68706C5F6569632E63B0
+:10206000000000002E2E2F68706C2F7274632F6892
+:10207000706C5F7274632E6300000000000000004B
+:102080000000000000000000000000000000000050
+:102090000100000014002000000100000E0F0000ED
+:1020A0000000D70000093D00000000000000000013
+:1020B0000000000000000000000000000000000020
+:1020C0000000000000000000000000002E2E2F681D
+:1020D000706C2F736572636F6D2F68706C5F7365C2
+:1020E00072636F6D2E6300002E2E2F68706C2F743C
+:1020F000632F68706C5F74632E6300002E2E2F7345
+:102100006C6565705F6D616E616765722F736C657C
+:1021100065705F6D616E616765722E63000000001F
+:10212000F8B5C046F8BC08BC9E467047D100000018
+:10213000F8B5C046F8BC08BC9E467047A900000030
+:102140000313000000000000000000329F0F000099
+:10215000CF0700008916000015190000C115000006
+:10216000D3150000F1170000E515000071180000FC
+:08217000B118000089190000FC
+:00000001FF
diff --git a/Smol Watch Project/My Project/Debug/My Project.lss b/Smol Watch Project/My Project/Debug/My Project.lss
new file mode 100644
index 00000000..b6e56b2d
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/My Project.lss
@@ -0,0 +1,5931 @@
+
+My Project.elf: file format elf32-littlearm
+
+Sections:
+Idx Name Size VMA LMA File off Algn
+ 0 .text 00002140 00000000 00000000 00010000 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 1 .relocate 00000038 20000000 00002140 00020000 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 2 .bss 000000e4 20000038 00002178 00020038 2**2
+ ALLOC
+ 3 .stack 00002004 2000011c 0000225c 00020038 2**0
+ ALLOC
+ 4 .ARM.attributes 00000028 00000000 00000000 00020038 2**0
+ CONTENTS, READONLY
+ 5 .comment 00000059 00000000 00000000 00020060 2**0
+ CONTENTS, READONLY
+ 6 .debug_info 000315e1 00000000 00000000 000200b9 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 7 .debug_abbrev 00004084 00000000 00000000 0005169a 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 8 .debug_loc 00011a80 00000000 00000000 0005571e 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 9 .debug_aranges 00000d00 00000000 00000000 0006719e 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 10 .debug_ranges 00000d80 00000000 00000000 00067e9e 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 11 .debug_macro 0001de3f 00000000 00000000 00068c1e 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 12 .debug_line 00015702 00000000 00000000 00086a5d 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 13 .debug_str 000912d9 00000000 00000000 0009c15f 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 14 .debug_frame 000020dc 00000000 00000000 0012d438 2**2
+ CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+00000000 :
+ 0: 20 21 00 20 21 01 00 00 1d 01 00 00 1d 01 00 00 !. !...........
+ ...
+ 2c: 1d 01 00 00 00 00 00 00 00 00 00 00 1d 01 00 00 ................
+ 3c: 1d 01 00 00 1d 01 00 00 1d 01 00 00 89 0e 00 00 ................
+ 4c: 35 0c 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00 5...............
+ 5c: 1d 01 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00 ................
+ 6c: 1d 01 00 00 1d 01 00 00 00 00 00 00 00 00 00 00 ................
+ 7c: ad 15 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00 ................
+ 8c: e5 19 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00 ................
+ 9c: 1d 01 00 00 1d 01 00 00 1d 01 00 00 ............
+
+000000a8 <__do_global_dtors_aux>:
+ a8: b510 push {r4, lr}
+ aa: 4c06 ldr r4, [pc, #24] ; (c4 <__do_global_dtors_aux+0x1c>)
+ ac: 7823 ldrb r3, [r4, #0]
+ ae: 2b00 cmp r3, #0
+ b0: d107 bne.n c2 <__do_global_dtors_aux+0x1a>
+ b2: 4b05 ldr r3, [pc, #20] ; (c8 <__do_global_dtors_aux+0x20>)
+ b4: 2b00 cmp r3, #0
+ b6: d002 beq.n be <__do_global_dtors_aux+0x16>
+ b8: 4804 ldr r0, [pc, #16] ; (cc <__do_global_dtors_aux+0x24>)
+ ba: e000 b.n be <__do_global_dtors_aux+0x16>
+ bc: bf00 nop
+ be: 2301 movs r3, #1
+ c0: 7023 strb r3, [r4, #0]
+ c2: bd10 pop {r4, pc}
+ c4: 20000038 .word 0x20000038
+ c8: 00000000 .word 0x00000000
+ cc: 00002140 .word 0x00002140
+
+000000d0 :
+ d0: 4b08 ldr r3, [pc, #32] ; (f4 )
+ d2: b510 push {r4, lr}
+ d4: 2b00 cmp r3, #0
+ d6: d003 beq.n e0
+ d8: 4907 ldr r1, [pc, #28] ; (f8 )
+ da: 4808 ldr r0, [pc, #32] ; (fc )
+ dc: e000 b.n e0
+ de: bf00 nop
+ e0: 4807 ldr r0, [pc, #28] ; (100 )
+ e2: 6803 ldr r3, [r0, #0]
+ e4: 2b00 cmp r3, #0
+ e6: d100 bne.n ea
+ e8: bd10 pop {r4, pc}
+ ea: 4b06 ldr r3, [pc, #24] ; (104 )
+ ec: 2b00 cmp r3, #0
+ ee: d0fb beq.n e8
+ f0: 4798 blx r3
+ f2: e7f9 b.n e8
+ f4: 00000000 .word 0x00000000
+ f8: 2000003c .word 0x2000003c
+ fc: 00002140 .word 0x00002140
+ 100: 00002140 .word 0x00002140
+ 104: 00000000 .word 0x00000000
+
+00000108 :
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void)
+{
+ 108: b510 push {r4, lr}
+ system_init();
+ 10a: 4b02 ldr r3, [pc, #8] ; (114 )
+ 10c: 4798 blx r3
+ sleep_manager_init();
+ 10e: 4b02 ldr r3, [pc, #8] ; (118 )
+ 110: 4798 blx r3
+}
+ 112: bd10 pop {r4, pc}
+ 114: 00000309 .word 0x00000309
+ 118: 00001b8d .word 0x00001b8d
+
+0000011c :
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+ 11c: e7fe b.n 11c
+ ...
+
+00000120 :
+{
+ 120: b510 push {r4, lr}
+ if (pSrc != pDest) {
+ 122: 4a10 ldr r2, [pc, #64] ; (164 )
+ 124: 4b10 ldr r3, [pc, #64] ; (168 )
+ 126: 429a cmp r2, r3
+ 128: d009 beq.n 13e
+ 12a: 4b0f ldr r3, [pc, #60] ; (168 )
+ 12c: 4a0d ldr r2, [pc, #52] ; (164 )
+ 12e: e003 b.n 138
+ *pDest++ = *pSrc++;
+ 130: 6811 ldr r1, [r2, #0]
+ 132: 6019 str r1, [r3, #0]
+ 134: 3304 adds r3, #4
+ 136: 3204 adds r2, #4
+ for (; pDest < &_erelocate;) {
+ 138: 490c ldr r1, [pc, #48] ; (16c )
+ 13a: 428b cmp r3, r1
+ 13c: d3f8 bcc.n 130
+ *pDest++ = *pSrc++;
+ 13e: 4b0c ldr r3, [pc, #48] ; (170 )
+ 140: e002 b.n 148
+ *pDest++ = 0;
+ 142: 2200 movs r2, #0
+ 144: 601a str r2, [r3, #0]
+ 146: 3304 adds r3, #4
+ for (pDest = &_szero; pDest < &_ezero;) {
+ 148: 4a0a ldr r2, [pc, #40] ; (174 )
+ 14a: 4293 cmp r3, r2
+ 14c: d3f9 bcc.n 142
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+ 14e: 4a0a ldr r2, [pc, #40] ; (178 )
+ 150: 21ff movs r1, #255 ; 0xff
+ 152: 4b0a ldr r3, [pc, #40] ; (17c )
+ 154: 438b bics r3, r1
+ 156: 6093 str r3, [r2, #8]
+ __libc_init_array();
+ 158: 4b09 ldr r3, [pc, #36] ; (180 )
+ 15a: 4798 blx r3
+ main();
+ 15c: 4b09 ldr r3, [pc, #36] ; (184 )
+ 15e: 4798 blx r3
+ 160: e7fe b.n 160
+ 162: 46c0 nop ; (mov r8, r8)
+ 164: 00002140 .word 0x00002140
+ 168: 20000000 .word 0x20000000
+ 16c: 20000038 .word 0x20000038
+ 170: 20000038 .word 0x20000038
+ 174: 2000011c .word 0x2000011c
+ 178: e000ed00 .word 0xe000ed00
+ 17c: 00000000 .word 0x00000000
+ 180: 00001eb1 .word 0x00001eb1
+ 184: 000019f9 .word 0x000019f9
+
+00000188 :
+ uint8_t tmp;
+ PORT_CRITICAL_SECTION_ENTER();
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 188: 4a03 ldr r2, [pc, #12] ; (198 )
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 18a: 6951 ldr r1, [r2, #20]
+ 18c: 2380 movs r3, #128 ; 0x80
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 18e: 009b lsls r3, r3, #2
+ 190: 430b orrs r3, r1
+ tmp |= PORT_PMUX_PMUXE(data);
+ 192: 6153 str r3, [r2, #20]
+ 194: 4770 bx lr
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 196: 46c0 nop ; (mov r8, r8)
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 198: 40000800 .word 0x40000800
+
+0000019c :
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 19c: b510 push {r4, lr}
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 19e: 4b03 ldr r3, [pc, #12] ; (1ac )
+ 1a0: 4798 blx r3
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 1a2: 4903 ldr r1, [pc, #12] ; (1b0 )
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 1a4: 4803 ldr r0, [pc, #12] ; (1b4 )
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 1a6: 4b04 ldr r3, [pc, #16] ; (1b8 )
+ tmp |= PORT_PMUX_PMUXO(data);
+ 1a8: 4798 blx r3
+ 1aa: bd10 pop {r4, pc}
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 1ac: 00000189 .word 0x00000189
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 1b0: 40002400 .word 0x40002400
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 1b4: 200000b4 .word 0x200000b4
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 1b8: 000006b5 .word 0x000006b5
+
+000001bc :
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 1bc: b570 push {r4, r5, r6, lr}
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 1be: 4b13 ldr r3, [pc, #76] ; (20c )
+ 1c0: 20de movs r0, #222 ; 0xde
+ tmp |= PORT_PMUX_PMUXE(data);
+ 1c2: 5c19 ldrb r1, [r3, r0]
+ 1c4: 2204 movs r2, #4
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 1c6: 4391 bics r1, r2
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 1c8: 5419 strb r1, [r3, r0]
+ 1ca: 5c19 ldrb r1, [r3, r0]
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 1cc: 2501 movs r5, #1
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 1ce: 43a9 bics r1, r5
+ 1d0: 2401 movs r4, #1
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 1d2: 4321 orrs r1, r4
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 1d4: b2c9 uxtb r1, r1
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 1d6: 5419 strb r1, [r3, r0]
+ tmp |= PORT_PMUX_PMUXO(data);
+ 1d8: 381f subs r0, #31
+ 1da: 5c19 ldrb r1, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 1dc: 260f movs r6, #15
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 1de: 43b1 bics r1, r6
+ 1e0: 2602 movs r6, #2
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 1e2: 4331 orrs r1, r6
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 1e4: b2c9 uxtb r1, r1
+ 1e6: 5419 strb r1, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 1e8: 21df movs r1, #223 ; 0xdf
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 1ea: 5c5e ldrb r6, [r3, r1]
+ 1ec: 4396 bics r6, r2
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 1ee: 545e strb r6, [r3, r1]
+ 1f0: 5c5a ldrb r2, [r3, r1]
+ tmp |= PORT_PMUX_PMUXE(data);
+ 1f2: 43aa bics r2, r5
+ 1f4: 4322 orrs r2, r4
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 1f6: b2d2 uxtb r2, r2
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 1f8: 545a strb r2, [r3, r1]
+ 1fa: 5c1a ldrb r2, [r3, r0]
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 1fc: 39d0 subs r1, #208 ; 0xd0
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 1fe: 400a ands r2, r1
+ 200: 2120 movs r1, #32
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 202: 430a orrs r2, r1
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 204: b2d2 uxtb r2, r2
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 206: 541a strb r2, [r3, r0]
+ tmp |= PORT_PMUX_PMUXO(data);
+ 208: bd70 pop {r4, r5, r6, pc}
+ 20a: 46c0 nop ; (mov r8, r8)
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 20c: 41006000 .word 0x41006000
+
+00000210 :
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 210: 4b06 ldr r3, [pc, #24] ; (22c )
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 212: 2140 movs r1, #64 ; 0x40
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 214: 22c4 movs r2, #196 ; 0xc4
+ 216: 5099 str r1, [r3, r2]
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 218: 3103 adds r1, #3
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 21a: 3a08 subs r2, #8
+ 21c: 5099 str r1, [r3, r2]
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 21e: 4a04 ldr r2, [pc, #16] ; (230 )
+ 220: 69d3 ldr r3, [r2, #28]
+ tmp |= PORT_PMUX_PMUXE(data);
+ 222: 393f subs r1, #63 ; 0x3f
+ 224: 430b orrs r3, r1
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 226: 61d3 str r3, [r2, #28]
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 228: 4770 bx lr
+ 22a: 46c0 nop ; (mov r8, r8)
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 22c: 40001c00 .word 0x40001c00
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 230: 40000800 .word 0x40000800
+
+00000234 :
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 234: b510 push {r4, lr}
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 236: 4b04 ldr r3, [pc, #16] ; (248 )
+ tmp |= PORT_PMUX_PMUXO(data);
+ 238: 4798 blx r3
+ 23a: 4904 ldr r1, [pc, #16] ; (24c )
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 23c: 4804 ldr r0, [pc, #16] ; (250 )
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 23e: 4b05 ldr r3, [pc, #20] ; (254 )
+ 240: 4798 blx r3
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 242: 4b05 ldr r3, [pc, #20] ; (258 )
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 244: 4798 blx r3
+ 246: bd10 pop {r4, pc}
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 248: 00000211 .word 0x00000211
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 24c: 42000800 .word 0x42000800
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 250: 200000f8 .word 0x200000f8
+ tmp |= PORT_PMUX_PMUXE(data);
+ 254: 000008a9 .word 0x000008a9
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 258: 000001bd .word 0x000001bd
+
+0000025c :
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 25c: b510 push {r4, lr}
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 25e: 4802 ldr r0, [pc, #8] ; (268 )
+ 260: 4b02 ldr r3, [pc, #8] ; (26c )
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 262: 4798 blx r3
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 264: bd10 pop {r4, pc}
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 266: 46c0 nop ; (mov r8, r8)
+ tmp |= PORT_PMUX_PMUXO(data);
+ 268: e000e010 .word 0xe000e010
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 26c: 0000082d .word 0x0000082d
+
+00000270 :
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 270: b530 push {r4, r5, lr}
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 272: 4b0f ldr r3, [pc, #60] ; (2b0 )
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 274: 2254 movs r2, #84 ; 0x54
+ 276: 5c99 ldrb r1, [r3, r2]
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 278: 2501 movs r5, #1
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 27a: 43a9 bics r1, r5
+ 27c: 2401 movs r4, #1
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 27e: 4321 orrs r1, r4
+ 280: b2c9 uxtb r1, r1
+ 282: 5499 strb r1, [r3, r2]
+ tmp |= PORT_PMUX_PMUXE(data);
+ 284: 203a movs r0, #58 ; 0x3a
+ 286: 5c19 ldrb r1, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 288: 3a45 subs r2, #69 ; 0x45
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 28a: 4391 bics r1, r2
+ 28c: 2204 movs r2, #4
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 28e: 4311 orrs r1, r2
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 290: b2c9 uxtb r1, r1
+ 292: 5419 strb r1, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 294: 2155 movs r1, #85 ; 0x55
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 296: 5c5a ldrb r2, [r3, r1]
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 298: 43aa bics r2, r5
+ tmp |= PORT_PMUX_PMUXO(data);
+ 29a: 4322 orrs r2, r4
+ 29c: b2d2 uxtb r2, r2
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 29e: 545a strb r2, [r3, r1]
+ gpio_set_pin_function(SEG21, PINMUX_PA19B_SLCD_LP35);
+
+ gpio_set_pin_function(SEG22, PINMUX_PB16B_SLCD_LP42);
+
+ gpio_set_pin_function(SEG23, PINMUX_PB17B_SLCD_LP43);
+}
+ 2a0: 5c1a ldrb r2, [r3, r0]
+ 2a2: 3946 subs r1, #70 ; 0x46
+ 2a4: 400a ands r2, r1
+ 2a6: 2140 movs r1, #64 ; 0x40
+ 2a8: 430a orrs r2, r1
+ 2aa: b2d2 uxtb r2, r2
+ 2ac: 541a strb r2, [r3, r0]
+}
+ 2ae: bd30 pop {r4, r5, pc}
+ 2b0: 41006000 .word 0x41006000
+
+000002b4 :
+}
+
+static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw)
+{
+ MCLK_CRITICAL_SECTION_ENTER();
+ ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3;
+ 2b4: 4a05 ldr r2, [pc, #20] ; (2cc )
+ 2b6: 69d1 ldr r1, [r2, #28]
+ 2b8: 2380 movs r3, #128 ; 0x80
+ 2ba: 011b lsls r3, r3, #4
+ 2bc: 430b orrs r3, r1
+ 2be: 61d3 str r3, [r2, #28]
+}
+
+static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+ GCLK_CRITICAL_SECTION_ENTER();
+ ((Gclk *)hw)->PCHCTRL[index].reg = data;
+ 2c0: 2140 movs r1, #64 ; 0x40
+ 2c2: 23e0 movs r3, #224 ; 0xe0
+ 2c4: 4a02 ldr r2, [pc, #8] ; (2d0 )
+ 2c6: 50d1 str r1, [r2, r3]
+}
+ 2c8: 4770 bx lr
+ 2ca: 46c0 nop ; (mov r8, r8)
+ 2cc: 40000800 .word 0x40000800
+ 2d0: 40001c00 .word 0x40001c00
+
+000002d4 :
+{
+ 2d4: b510 push {r4, lr}
+ PWM_0_CLOCK_init();
+ 2d6: 4b06 ldr r3, [pc, #24] ; (2f0 )
+ 2d8: 4798 blx r3
+ PWM_0_PORT_init();
+ 2da: 4b06 ldr r3, [pc, #24] ; (2f4 )
+ 2dc: 4798 blx r3
+ pwm_init(&PWM_0, TC3, _tc_get_pwm());
+ 2de: 4b06 ldr r3, [pc, #24] ; (2f8 )
+ 2e0: 4798 blx r3
+ 2e2: 0002 movs r2, r0
+ 2e4: 4905 ldr r1, [pc, #20] ; (2fc )
+ 2e6: 4806 ldr r0, [pc, #24] ; (300 )
+ 2e8: 4b06 ldr r3, [pc, #24] ; (304 )
+ 2ea: 4798 blx r3
+}
+ 2ec: bd10 pop {r4, pc}
+ 2ee: 46c0 nop ; (mov r8, r8)
+ 2f0: 000002b5 .word 0x000002b5
+ 2f4: 00000271 .word 0x00000271
+ 2f8: 000019d9 .word 0x000019d9
+ 2fc: 42002c00 .word 0x42002c00
+ 300: 20000090 .word 0x20000090
+ 304: 00000999 .word 0x00000999
+
+00000308 :
+ slcd_sync_init(&SEGMENT_LCD_0, SLCD);
+ SEGMENT_LCD_0_PORT_init();
+}
+
+void system_init(void)
+{
+ 308: b5f0 push {r4, r5, r6, r7, lr}
+ 30a: 46c6 mov lr, r8
+ 30c: b500 push {lr}
+ * Currently the following initialization functions are supported:
+ * - System clock initialization
+ */
+static inline void init_mcu(void)
+{
+ _init_chip();
+ 30e: 4b1c ldr r3, [pc, #112] ; (380 )
+ 310: 4798 blx r3
+ ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+ 312: 22c0 movs r2, #192 ; 0xc0
+ 314: 05d2 lsls r2, r2, #23
+ 316: 2404 movs r4, #4
+ 318: 6054 str r4, [r2, #4]
+
+static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
+ hri_port_wrconfig_reg_t data)
+{
+ PORT_CRITICAL_SECTION_ENTER();
+ ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+ 31a: 4b1a ldr r3, [pc, #104] ; (384 )
+ 31c: 491a ldr r1, [pc, #104] ; (388 )
+ 31e: 6299 str r1, [r3, #40] ; 0x28
+ 320: 491a ldr r1, [pc, #104] ; (38c )
+ 322: 6299 str r1, [r3, #40] ; 0x28
+ ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+ 324: 6054 str r4, [r2, #4]
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+ 326: 2042 movs r0, #66 ; 0x42
+ 328: 5c19 ldrb r1, [r3, r0]
+ 32a: 2504 movs r5, #4
+ 32c: 4329 orrs r1, r5
+ 32e: b2c9 uxtb r1, r1
+ 330: 5419 strb r1, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+ 332: 6154 str r4, [r2, #20]
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 334: 5c1c ldrb r4, [r3, r0]
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 336: 2101 movs r1, #1
+ 338: 438c bics r4, r1
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 33a: 541c strb r4, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+ 33c: 2794 movs r7, #148 ; 0x94
+ 33e: 51d1 str r1, [r2, r7]
+ ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+ 340: 2688 movs r6, #136 ; 0x88
+ 342: 5191 str r1, [r2, r6]
+ ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+ 344: 3066 adds r0, #102 ; 0x66
+ 346: 4c12 ldr r4, [pc, #72] ; (390 )
+ 348: 501c str r4, [r3, r0]
+ 34a: 24c0 movs r4, #192 ; 0xc0
+ 34c: 0624 lsls r4, r4, #24
+ 34e: 46a0 mov r8, r4
+ 350: 501c str r4, [r3, r0]
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 352: 24c0 movs r4, #192 ; 0xc0
+ 354: 46a4 mov ip, r4
+ 356: 5d1c ldrb r4, [r3, r4]
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 358: 438c bics r4, r1
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 35a: 4665 mov r5, ip
+ 35c: 555c strb r4, [r3, r5]
+ ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+ 35e: 2408 movs r4, #8
+ 360: 51d4 str r4, [r2, r7]
+ ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+ 362: 5194 str r4, [r2, r6]
+ ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+ 364: 4a0b ldr r2, [pc, #44] ; (394 )
+ 366: 501a str r2, [r3, r0]
+ 368: 4642 mov r2, r8
+ 36a: 501a str r2, [r3, r0]
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 36c: 301b adds r0, #27
+ 36e: 5c1a ldrb r2, [r3, r0]
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 370: 438a bics r2, r1
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 372: 541a strb r2, [r3, r0]
+ // Set pin direction to output
+ gpio_set_pin_direction(D0, GPIO_DIRECTION_OUT);
+
+ gpio_set_pin_function(D0, GPIO_PIN_FUNCTION_OFF);
+
+ delay_driver_init();
+ 374: 4b08 ldr r3, [pc, #32] ; (398 )
+ 376: 4798 blx r3
+ PWM_0_init();
+
+ PWM_1_init();
+ SEGMENT_LCD_0_init();
+*/
+}
+ 378: bc04 pop {r2}
+ 37a: 4690 mov r8, r2
+ 37c: bdf0 pop {r4, r5, r6, r7, pc}
+ 37e: 46c0 nop ; (mov r8, r8)
+ 380: 00000b3d .word 0x00000b3d
+ 384: 41006000 .word 0x41006000
+ 388: 40020004 .word 0x40020004
+ 38c: c0020000 .word 0xc0020000
+ 390: 40000001 .word 0x40000001
+ 394: 40000008 .word 0x40000008
+ 398: 0000025d .word 0x0000025d
+
+0000039c :
+ * \retval false not leap year.
+ * \retval true leap year.
+ */
+static bool leap_year(uint16_t year)
+{
+ if (year & 3) {
+ 39c: 0783 lsls r3, r0, #30
+ 39e: d101 bne.n 3a4
+ return false;
+ } else {
+ return true;
+ 3a0: 2001 movs r0, #1
+ }
+}
+ 3a2: 4770 bx lr
+ return false;
+ 3a4: 2000 movs r0, #0
+ 3a6: e7fc b.n 3a2
+
+000003a8 :
+
+/** \brief calculate the seconds in specified year/month
+ * \retval 0 month error.
+ */
+static uint32_t get_secs_in_month(uint32_t year, uint8_t month)
+{
+ 3a8: b510 push {r4, lr}
+ 3aa: 000c movs r4, r1
+ uint32_t sec_in_month = 0;
+
+ if (leap_year(year)) {
+ 3ac: b280 uxth r0, r0
+ 3ae: 4b10 ldr r3, [pc, #64] ; (3f0 )
+ 3b0: 4798 blx r3
+ 3b2: 2800 cmp r0, #0
+ 3b4: d00b beq.n 3ce
+ switch (month) {
+ 3b6: 2c0c cmp r4, #12
+ 3b8: d803 bhi.n 3c2
+ 3ba: 00a4 lsls r4, r4, #2
+ 3bc: 4b0d ldr r3, [pc, #52] ; (3f4 )
+ 3be: 591b ldr r3, [r3, r4]
+ 3c0: 469f mov pc, r3
+ uint32_t sec_in_month = 0;
+ 3c2: 2000 movs r0, #0
+ 3c4: e010 b.n 3e8
+ case 10:
+ case 12:
+ sec_in_month = SECS_IN_31DAYS;
+ break;
+ case 2:
+ sec_in_month = SECS_IN_29DAYS;
+ 3c6: 480c ldr r0, [pc, #48] ; (3f8 )
+ break;
+ 3c8: e00e b.n 3e8
+ case 4:
+ case 6:
+ case 9:
+ case 11:
+ sec_in_month = SECS_IN_30DAYS;
+ 3ca: 480c ldr r0, [pc, #48] ; (3fc )
+ break;
+ 3cc: e00c b.n 3e8
+ default:
+ break;
+ }
+ } else {
+ switch (month) {
+ 3ce: 2c0c cmp r4, #12
+ 3d0: d803 bhi.n 3da
+ 3d2: 00a4 lsls r4, r4, #2
+ 3d4: 4b0a ldr r3, [pc, #40] ; (400 )
+ 3d6: 591b ldr r3, [r3, r4]
+ 3d8: 469f mov pc, r3
+ uint32_t sec_in_month = 0;
+ 3da: 2000 movs r0, #0
+ 3dc: e004 b.n 3e8
+ case 10:
+ case 12:
+ sec_in_month = SECS_IN_31DAYS;
+ break;
+ case 2:
+ sec_in_month = SECS_IN_28DAYS;
+ 3de: 4809 ldr r0, [pc, #36] ; (404 )
+ break;
+ 3e0: e002 b.n 3e8
+ case 4:
+ case 6:
+ case 9:
+ case 11:
+ sec_in_month = SECS_IN_30DAYS;
+ 3e2: 4806 ldr r0, [pc, #24] ; (3fc )
+ break;
+ 3e4: e000 b.n 3e8
+ sec_in_month = SECS_IN_31DAYS;
+ 3e6: 4808 ldr r0, [pc, #32] ; (408 )
+ break;
+ }
+ }
+
+ return sec_in_month;
+}
+ 3e8: bd10 pop {r4, pc}
+ sec_in_month = SECS_IN_31DAYS;
+ 3ea: 4807 ldr r0, [pc, #28] ; (408 )
+ return sec_in_month;
+ 3ec: e7fc b.n 3e8
+ 3ee: 46c0 nop ; (mov r8, r8)
+ 3f0: 0000039d .word 0x0000039d
+ 3f4: 00001ef8 .word 0x00001ef8
+ 3f8: 00263b80 .word 0x00263b80
+ 3fc: 00278d00 .word 0x00278d00
+ 400: 00001f2c .word 0x00001f2c
+ 404: 0024ea00 .word 0x0024ea00
+ 408: 0028de80 .word 0x0028de80
+
+0000040c :
+
+/** \brief convert timestamp to date/time
+ */
+static int32_t convert_timestamp_to_datetime(struct calendar_descriptor *const calendar, uint32_t ts,
+ struct calendar_date_time *dt)
+{
+ 40c: b5f0 push {r4, r5, r6, r7, lr}
+ 40e: 46c6 mov lr, r8
+ 410: b500 push {lr}
+ 412: 000c movs r4, r1
+ 414: 4690 mov r8, r2
+ uint32_t tmp, sec_in_year, sec_in_month;
+ uint32_t tmp_year = calendar->base_year;
+ 416: 6986 ldr r6, [r0, #24]
+ 418: e004 b.n 424
+
+ tmp = ts;
+
+ /* Find year */
+ while (true) {
+ sec_in_year = leap_year(tmp_year) ? SECS_IN_LEAP_YEAR : SECS_IN_NON_LEAP_YEAR;
+ 41a: 4b1f ldr r3, [pc, #124] ; (498 )
+
+ if (tmp >= sec_in_year) {
+ 41c: 429c cmp r4, r3
+ 41e: d309 bcc.n 434
+ tmp -= sec_in_year;
+ 420: 1ae4 subs r4, r4, r3
+ tmp_year++;
+ 422: 3601 adds r6, #1
+ sec_in_year = leap_year(tmp_year) ? SECS_IN_LEAP_YEAR : SECS_IN_NON_LEAP_YEAR;
+ 424: b2b7 uxth r7, r6
+ 426: 0038 movs r0, r7
+ 428: 4b1c ldr r3, [pc, #112] ; (49c )
+ 42a: 4798 blx r3
+ 42c: 2800 cmp r0, #0
+ 42e: d0f4 beq.n 41a
+ 430: 4b1b ldr r3, [pc, #108] ; (4a0 )
+ 432: e7f3 b.n 41c
+ 434: 2501 movs r5, #1
+ break;
+ }
+ }
+ /* Find month of year */
+ while (true) {
+ sec_in_month = get_secs_in_month(tmp_year, tmp_month);
+ 436: 0029 movs r1, r5
+ 438: 0030 movs r0, r6
+ 43a: 4b1a ldr r3, [pc, #104] ; (4a4 )
+ 43c: 4798 blx r3
+
+ if (tmp >= sec_in_month) {
+ 43e: 4284 cmp r4, r0
+ 440: d303 bcc.n 44a
+ tmp -= sec_in_month;
+ 442: 1a24 subs r4, r4, r0
+ tmp_month++;
+ 444: 3501 adds r5, #1
+ 446: b2ed uxtb r5, r5
+ sec_in_month = get_secs_in_month(tmp_year, tmp_month);
+ 448: e7f5 b.n 436
+ 44a: 2101 movs r1, #1
+ break;
+ }
+ }
+ /* Find day of month */
+ while (true) {
+ if (tmp >= SECS_IN_DAY) {
+ 44c: 4b16 ldr r3, [pc, #88] ; (4a8 )
+ 44e: 429c cmp r4, r3
+ 450: d905 bls.n 45e
+ tmp -= SECS_IN_DAY;
+ 452: 4b16 ldr r3, [pc, #88] ; (4ac )
+ 454: 469c mov ip, r3
+ 456: 4464 add r4, ip
+ tmp_day++;
+ 458: 3101 adds r1, #1
+ 45a: b2c9 uxtb r1, r1
+ if (tmp >= SECS_IN_DAY) {
+ 45c: e7f6 b.n 44c
+ 45e: 2200 movs r2, #0
+ break;
+ }
+ }
+ /* Find hour of day */
+ while (true) {
+ if (tmp >= SECS_IN_HOUR) {
+ 460: 4b13 ldr r3, [pc, #76] ; (4b0 )
+ 462: 429c cmp r4, r3
+ 464: d905 bls.n 472
+ tmp -= SECS_IN_HOUR;
+ 466: 4b13 ldr r3, [pc, #76] ; (4b4 )
+ 468: 469c mov ip, r3
+ 46a: 4464 add r4, ip
+ tmp_hour++;
+ 46c: 3201 adds r2, #1
+ 46e: b2d2 uxtb r2, r2
+ if (tmp >= SECS_IN_HOUR) {
+ 470: e7f6 b.n 460
+ 472: 2300 movs r3, #0
+ break;
+ }
+ }
+ /* Find minute in hour */
+ while (true) {
+ if (tmp >= SECS_IN_MINUTE) {
+ 474: 2c3b cmp r4, #59 ; 0x3b
+ 476: d903 bls.n 480
+ tmp -= SECS_IN_MINUTE;
+ 478: 3c3c subs r4, #60 ; 0x3c
+ tmp_minutes++;
+ 47a: 3301 adds r3, #1
+ 47c: b2db uxtb r3, r3
+ if (tmp >= SECS_IN_MINUTE) {
+ 47e: e7f9 b.n 474
+ } else {
+ break;
+ }
+ }
+
+ dt->date.year = tmp_year;
+ 480: 4640 mov r0, r8
+ 482: 80c7 strh r7, [r0, #6]
+ dt->date.month = tmp_month;
+ 484: 7145 strb r5, [r0, #5]
+ dt->date.day = tmp_day;
+ 486: 7101 strb r1, [r0, #4]
+ dt->time.hour = tmp_hour;
+ 488: 7082 strb r2, [r0, #2]
+ dt->time.min = tmp_minutes;
+ 48a: 7043 strb r3, [r0, #1]
+ dt->time.sec = tmp;
+ 48c: 7004 strb r4, [r0, #0]
+
+ return ERR_NONE;
+}
+ 48e: 2000 movs r0, #0
+ 490: bc04 pop {r2}
+ 492: 4690 mov r8, r2
+ 494: bdf0 pop {r4, r5, r6, r7, pc}
+ 496: 46c0 nop ; (mov r8, r8)
+ 498: 01e13380 .word 0x01e13380
+ 49c: 0000039d .word 0x0000039d
+ 4a0: 01e28500 .word 0x01e28500
+ 4a4: 000003a9 .word 0x000003a9
+ 4a8: 0001517f .word 0x0001517f
+ 4ac: fffeae80 .word 0xfffeae80
+ 4b0: 00000e0f .word 0x00000e0f
+ 4b4: fffff1f0 .word 0xfffff1f0
+
+000004b8 :
+
+/** \brief convert date/time to timestamp
+ * \return timestamp
+ */
+static uint32_t convert_datetime_to_timestamp(struct calendar_descriptor *const calendar, struct calendar_date_time *dt)
+{
+ 4b8: b5f0 push {r4, r5, r6, r7, lr}
+ 4ba: 46de mov lr, fp
+ 4bc: 4657 mov r7, sl
+ 4be: 464e mov r6, r9
+ 4c0: 4645 mov r5, r8
+ 4c2: b5e0 push {r5, r6, r7, lr}
+ 4c4: b083 sub sp, #12
+ uint32_t tmp = 0;
+ uint32_t i = 0;
+ uint8_t year, month, day, hour, minutes, seconds;
+
+ year = dt->date.year - calendar->base_year;
+ 4c6: 88cb ldrh r3, [r1, #6]
+ 4c8: 9300 str r3, [sp, #0]
+ 4ca: b2de uxtb r6, r3
+ 4cc: 6983 ldr r3, [r0, #24]
+ 4ce: 4699 mov r9, r3
+ 4d0: 466a mov r2, sp
+ 4d2: 7113 strb r3, [r2, #4]
+ 4d4: 7913 ldrb r3, [r2, #4]
+ 4d6: 1af6 subs r6, r6, r3
+ 4d8: b2f6 uxtb r6, r6
+ month = dt->date.month;
+ 4da: 794f ldrb r7, [r1, #5]
+ day = dt->date.day;
+ 4dc: 790b ldrb r3, [r1, #4]
+ 4de: 469a mov sl, r3
+ hour = dt->time.hour;
+ 4e0: 788b ldrb r3, [r1, #2]
+ 4e2: 4698 mov r8, r3
+ minutes = dt->time.min;
+ 4e4: 784b ldrb r3, [r1, #1]
+ 4e6: 469b mov fp, r3
+ seconds = dt->time.sec;
+ 4e8: 780b ldrb r3, [r1, #0]
+ 4ea: 9301 str r3, [sp, #4]
+
+ /* tot up year field */
+ for (i = 0; i < year; ++i) {
+ 4ec: 2500 movs r5, #0
+ uint32_t tmp = 0;
+ 4ee: 2400 movs r4, #0
+ for (i = 0; i < year; ++i) {
+ 4f0: e003 b.n 4fa
+ if (leap_year(calendar->base_year + i)) {
+ tmp += SECS_IN_LEAP_YEAR;
+ } else {
+ tmp += SECS_IN_NON_LEAP_YEAR;
+ 4f2: 4b1a ldr r3, [pc, #104] ; (55c )
+ 4f4: 469c mov ip, r3
+ 4f6: 4464 add r4, ip
+ for (i = 0; i < year; ++i) {
+ 4f8: 3501 adds r5, #1
+ 4fa: 42b5 cmp r5, r6
+ 4fc: d20a bcs.n 514
+ if (leap_year(calendar->base_year + i)) {
+ 4fe: 464b mov r3, r9
+ 500: 1958 adds r0, r3, r5
+ 502: b280 uxth r0, r0
+ 504: 4b16 ldr r3, [pc, #88] ; (560 )
+ 506: 4798 blx r3
+ 508: 2800 cmp r0, #0
+ 50a: d0f2 beq.n 4f2
+ tmp += SECS_IN_LEAP_YEAR;
+ 50c: 4b15 ldr r3, [pc, #84] ; (564 )
+ 50e: 469c mov ip, r3
+ 510: 4464 add r4, ip
+ 512: e7f1 b.n 4f8
+ 514: 2501 movs r5, #1
+ 516: e005 b.n 524
+ }
+ }
+
+ /* tot up month field */
+ for (i = 1; i < month; ++i) {
+ tmp += get_secs_in_month(dt->date.year, i);
+ 518: b2e9 uxtb r1, r5
+ 51a: 9800 ldr r0, [sp, #0]
+ 51c: 4b12 ldr r3, [pc, #72] ; (568 )
+ 51e: 4798 blx r3
+ 520: 1824 adds r4, r4, r0
+ for (i = 1; i < month; ++i) {
+ 522: 3501 adds r5, #1
+ 524: 42bd cmp r5, r7
+ 526: d3f7 bcc.n 518
+ }
+
+ /* tot up day/hour/minute/second fields */
+ tmp += (day - 1) * SECS_IN_DAY;
+ 528: 4653 mov r3, sl
+ 52a: 3b01 subs r3, #1
+ 52c: 480f ldr r0, [pc, #60] ; (56c )
+ 52e: 4358 muls r0, r3
+ 530: 1824 adds r4, r4, r0
+ tmp += hour * SECS_IN_HOUR;
+ 532: 20e1 movs r0, #225 ; 0xe1
+ 534: 0100 lsls r0, r0, #4
+ 536: 4643 mov r3, r8
+ 538: 4358 muls r0, r3
+ 53a: 1820 adds r0, r4, r0
+ tmp += minutes * SECS_IN_MINUTE;
+ 53c: 465b mov r3, fp
+ 53e: 011b lsls r3, r3, #4
+ 540: 465a mov r2, fp
+ 542: 1a9b subs r3, r3, r2
+ 544: 009c lsls r4, r3, #2
+ 546: 1900 adds r0, r0, r4
+ tmp += seconds;
+ 548: 9b01 ldr r3, [sp, #4]
+ 54a: 469c mov ip, r3
+ 54c: 4460 add r0, ip
+
+ return tmp;
+}
+ 54e: b003 add sp, #12
+ 550: bc3c pop {r2, r3, r4, r5}
+ 552: 4690 mov r8, r2
+ 554: 4699 mov r9, r3
+ 556: 46a2 mov sl, r4
+ 558: 46ab mov fp, r5
+ 55a: bdf0 pop {r4, r5, r6, r7, pc}
+ 55c: 01e13380 .word 0x01e13380
+ 560: 0000039d .word 0x0000039d
+ 564: 01e28500 .word 0x01e28500
+ 568: 000003a9 .word 0x000003a9
+ 56c: 00015180 .word 0x00015180
+
+00000570 :
+
+/** \brief calibrate timestamp to make desired timestamp ahead of current timestamp
+ */
+static void calibrate_timestamp(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm,
+ struct calendar_alarm *current_dt)
+{
+ 570: b570 push {r4, r5, r6, lr}
+ 572: 000c movs r4, r1
+ uint32_t alarm_ts;
+ uint32_t current_ts = current_dt->cal_alarm.timestamp;
+ 574: 68d0 ldr r0, [r2, #12]
+
+ alarm_ts = alarm->cal_alarm.timestamp;
+ 576: 68cd ldr r5, [r1, #12]
+
+ /* calibrate timestamp */
+ switch (alarm->cal_alarm.option) {
+ 578: 7c0b ldrb r3, [r1, #16]
+ 57a: 2b05 cmp r3, #5
+ 57c: d806 bhi.n 58c
+ 57e: 009b lsls r3, r3, #2
+ 580: 4915 ldr r1, [pc, #84] ; (5d8 )
+ 582: 58cb ldr r3, [r1, r3]
+ 584: 469f mov pc, r3
+ case CALENDAR_ALARM_MATCH_SEC:
+
+ if (alarm_ts <= current_ts) {
+ 586: 42a8 cmp r0, r5
+ 588: d300 bcc.n 58c
+ alarm_ts += SECS_IN_MINUTE;
+ 58a: 353c adds r5, #60 ; 0x3c
+ default:
+ break;
+ }
+
+ /* desired timestamp after calibration */
+ alarm->cal_alarm.timestamp = alarm_ts;
+ 58c: 60e5 str r5, [r4, #12]
+}
+ 58e: bd70 pop {r4, r5, r6, pc}
+ if (alarm_ts <= current_ts) {
+ 590: 42a8 cmp r0, r5
+ 592: d3fb bcc.n 58c
+ alarm_ts += SECS_IN_HOUR;
+ 594: 23e1 movs r3, #225 ; 0xe1
+ 596: 011b lsls r3, r3, #4
+ 598: 469c mov ip, r3
+ 59a: 4465 add r5, ip
+ 59c: e7f6 b.n 58c
+ if (alarm_ts <= current_ts) {
+ 59e: 42a8 cmp r0, r5
+ 5a0: d3f4 bcc.n 58c
+ alarm_ts += SECS_IN_DAY;
+ 5a2: 4b0e ldr r3, [pc, #56] ; (5dc )
+ 5a4: 469c mov ip, r3
+ 5a6: 4465 add r5, ip
+ 5a8: e7f0 b.n 58c
+ if (alarm_ts <= current_ts) {
+ 5aa: 42a8 cmp r0, r5
+ 5ac: d3ee bcc.n 58c
+ alarm_ts += get_secs_in_month(current_dt->cal_alarm.datetime.date.year,
+ 5ae: 8950 ldrh r0, [r2, #10]
+ 5b0: 7a51 ldrb r1, [r2, #9]
+ 5b2: 4b0b ldr r3, [pc, #44] ; (5e0 )
+ 5b4: 4798 blx r3
+ 5b6: 182d adds r5, r5, r0
+ 5b8: e7e8 b.n 58c
+ if (alarm_ts <= current_ts) {
+ 5ba: 42a8 cmp r0, r5
+ 5bc: d3e6 bcc.n 58c
+ if (leap_year(current_dt->cal_alarm.datetime.date.year)) {
+ 5be: 8950 ldrh r0, [r2, #10]
+ 5c0: 4b08 ldr r3, [pc, #32] ; (5e4 )
+ 5c2: 4798 blx r3
+ 5c4: 2800 cmp r0, #0
+ 5c6: d103 bne.n 5d0
+ alarm_ts += SECS_IN_NON_LEAP_YEAR;
+ 5c8: 4b07 ldr r3, [pc, #28] ; (5e8 )
+ 5ca: 469c mov ip, r3
+ 5cc: 4465 add r5, ip
+ 5ce: e7dd b.n 58c
+ alarm_ts += SECS_IN_LEAP_YEAR;
+ 5d0: 4b06 ldr r3, [pc, #24] ; (5ec )
+ 5d2: 469c mov ip, r3
+ 5d4: 4465 add r5, ip
+ 5d6: e7d9 b.n 58c
+ 5d8: 00001f60 .word 0x00001f60
+ 5dc: 00015180 .word 0x00015180
+ 5e0: 000003a9 .word 0x000003a9
+ 5e4: 0000039d .word 0x0000039d
+ 5e8: 01e13380 .word 0x01e13380
+ 5ec: 01e28500 .word 0x01e28500
+
+000005f0 :
+
+/** \brief complete alarm to absolute date/time, then fill up the timestamp
+ */
+static void fill_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm)
+{
+ 5f0: b570 push {r4, r5, r6, lr}
+ 5f2: b086 sub sp, #24
+ 5f4: 0005 movs r5, r0
+ 5f6: 000c movs r4, r1
+ struct calendar_alarm current_dt;
+ uint32_t tmp, current_ts;
+
+ /* get current date/time */
+ current_ts = _calendar_get_counter(&calendar->device);
+ 5f8: 4b29 ldr r3, [pc, #164] ; (6a0 )
+ 5fa: 4798 blx r3
+ 5fc: 0006 movs r6, r0
+ convert_timestamp_to_datetime(calendar, current_ts, ¤t_dt.cal_alarm.datetime);
+ 5fe: aa01 add r2, sp, #4
+ 600: 0001 movs r1, r0
+ 602: 0028 movs r0, r5
+ 604: 4b27 ldr r3, [pc, #156] ; (6a4 )
+ 606: 4798 blx r3
+
+ current_dt.cal_alarm.timestamp = current_ts;
+ 608: 9603 str r6, [sp, #12]
+
+ /* complete alarm */
+ switch (alarm->cal_alarm.option) {
+ 60a: 7c23 ldrb r3, [r4, #16]
+ 60c: 2b05 cmp r3, #5
+ 60e: d812 bhi.n 636
+ 610: 009b lsls r3, r3, #2
+ 612: 4a25 ldr r2, [pc, #148] ; (6a8 )
+ 614: 58d3 ldr r3, [r2, r3]
+ 616: 469f mov pc, r3
+ case CALENDAR_ALARM_MATCH_SEC:
+ alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+ 618: 466b mov r3, sp
+ 61a: 895b ldrh r3, [r3, #10]
+ 61c: 8163 strh r3, [r4, #10]
+ alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+ 61e: 466b mov r3, sp
+ 620: 7a5b ldrb r3, [r3, #9]
+ 622: 7263 strb r3, [r4, #9]
+ alarm->cal_alarm.datetime.date.day = current_dt.cal_alarm.datetime.date.day;
+ 624: 466b mov r3, sp
+ 626: 7a1b ldrb r3, [r3, #8]
+ 628: 7223 strb r3, [r4, #8]
+ alarm->cal_alarm.datetime.time.hour = current_dt.cal_alarm.datetime.time.hour;
+ 62a: 466b mov r3, sp
+ 62c: 799b ldrb r3, [r3, #6]
+ 62e: 71a3 strb r3, [r4, #6]
+ alarm->cal_alarm.datetime.time.min = current_dt.cal_alarm.datetime.time.min;
+ 630: 466b mov r3, sp
+ 632: 795b ldrb r3, [r3, #5]
+ 634: 7163 strb r3, [r4, #5]
+ default:
+ break;
+ }
+
+ /* fill up the timestamp */
+ tmp = convert_datetime_to_timestamp(calendar, &alarm->cal_alarm.datetime);
+ 636: 1d26 adds r6, r4, #4
+ 638: 0031 movs r1, r6
+ 63a: 0028 movs r0, r5
+ 63c: 4b1b ldr r3, [pc, #108] ; (6ac )
+ 63e: 4798 blx r3
+ alarm->cal_alarm.timestamp = tmp;
+ 640: 60e0 str r0, [r4, #12]
+
+ /* calibrate the timestamp */
+ calibrate_timestamp(calendar, alarm, ¤t_dt);
+ 642: 466a mov r2, sp
+ 644: 0021 movs r1, r4
+ 646: 0028 movs r0, r5
+ 648: 4b19 ldr r3, [pc, #100] ; (6b0 )
+ 64a: 4798 blx r3
+ convert_timestamp_to_datetime(calendar, alarm->cal_alarm.timestamp, &alarm->cal_alarm.datetime);
+ 64c: 68e1 ldr r1, [r4, #12]
+ 64e: 0032 movs r2, r6
+ 650: 0028 movs r0, r5
+ 652: 4b14 ldr r3, [pc, #80] ; (6a4 )
+ 654: 4798 blx r3
+}
+ 656: b006 add sp, #24
+ 658: bd70 pop {r4, r5, r6, pc}
+ alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+ 65a: 466b mov r3, sp
+ 65c: 895b ldrh r3, [r3, #10]
+ 65e: 8163 strh r3, [r4, #10]
+ alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+ 660: 466b mov r3, sp
+ 662: 7a5b ldrb r3, [r3, #9]
+ 664: 7263 strb r3, [r4, #9]
+ alarm->cal_alarm.datetime.date.day = current_dt.cal_alarm.datetime.date.day;
+ 666: 466b mov r3, sp
+ 668: 7a1b ldrb r3, [r3, #8]
+ 66a: 7223 strb r3, [r4, #8]
+ alarm->cal_alarm.datetime.time.hour = current_dt.cal_alarm.datetime.time.hour;
+ 66c: 466b mov r3, sp
+ 66e: 799b ldrb r3, [r3, #6]
+ 670: 71a3 strb r3, [r4, #6]
+ break;
+ 672: e7e0 b.n 636
+ alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+ 674: 466b mov r3, sp
+ 676: 895b ldrh r3, [r3, #10]
+ 678: 8163 strh r3, [r4, #10]
+ alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+ 67a: 466b mov r3, sp
+ 67c: 7a5b ldrb r3, [r3, #9]
+ 67e: 7263 strb r3, [r4, #9]
+ alarm->cal_alarm.datetime.date.day = current_dt.cal_alarm.datetime.date.day;
+ 680: 466b mov r3, sp
+ 682: 7a1b ldrb r3, [r3, #8]
+ 684: 7223 strb r3, [r4, #8]
+ break;
+ 686: e7d6 b.n 636
+ alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+ 688: 466b mov r3, sp
+ 68a: 895b ldrh r3, [r3, #10]
+ 68c: 8163 strh r3, [r4, #10]
+ alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+ 68e: 466b mov r3, sp
+ 690: 7a5b ldrb r3, [r3, #9]
+ 692: 7263 strb r3, [r4, #9]
+ break;
+ 694: e7cf b.n 636
+ alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+ 696: 466b mov r3, sp
+ 698: 895b ldrh r3, [r3, #10]
+ 69a: 8163 strh r3, [r4, #10]
+ break;
+ 69c: e7cb b.n 636
+ 69e: 46c0 nop ; (mov r8, r8)
+ 6a0: 00000e55 .word 0x00000e55
+ 6a4: 0000040d .word 0x0000040d
+ 6a8: 00001f78 .word 0x00001f78
+ 6ac: 000004b9 .word 0x000004b9
+ 6b0: 00000571 .word 0x00000571
+
+000006b4 :
+}
+
+/** \brief Initialize Calendar
+ */
+int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw)
+{
+ 6b4: b570 push {r4, r5, r6, lr}
+ 6b6: 0004 movs r4, r0
+ 6b8: 000d movs r5, r1
+ int32_t ret = 0;
+
+ /* Sanity check arguments */
+ ASSERT(calendar);
+ 6ba: 1e43 subs r3, r0, #1
+ 6bc: 4198 sbcs r0, r3
+ 6be: b2c0 uxtb r0, r0
+ 6c0: 22e0 movs r2, #224 ; 0xe0
+ 6c2: 0052 lsls r2, r2, #1
+ 6c4: 4909 ldr r1, [pc, #36] ; (6ec )
+ 6c6: 4b0a ldr r3, [pc, #40] ; (6f0 )
+ 6c8: 4798 blx r3
+
+ if (calendar->device.hw == hw) {
+ 6ca: 6823 ldr r3, [r4, #0]
+ 6cc: 42ab cmp r3, r5
+ 6ce: d008 beq.n 6e2
+ /* Already initialized with current configuration */
+ return ERR_NONE;
+ } else if (calendar->device.hw != NULL) {
+ 6d0: 2b00 cmp r3, #0
+ 6d2: d108 bne.n 6e6
+ /* Initialized with another configuration */
+ return ERR_ALREADY_INITIALIZED;
+ }
+ calendar->device.hw = (void *)hw;
+ 6d4: 6025 str r5, [r4, #0]
+ ret = _calendar_init(&calendar->device);
+ 6d6: 0020 movs r0, r4
+ 6d8: 4b06 ldr r3, [pc, #24] ; (6f4 )
+ 6da: 4798 blx r3
+ calendar->base_year = DEFAULT_BASE_YEAR;
+ 6dc: 4b06 ldr r3, [pc, #24] ; (6f8 )
+ 6de: 61a3 str r3, [r4, #24]
+
+ return ret;
+}
+ 6e0: bd70 pop {r4, r5, r6, pc}
+ return ERR_NONE;
+ 6e2: 2000 movs r0, #0
+ 6e4: e7fc b.n 6e0
+ return ERR_ALREADY_INITIALIZED;
+ 6e6: 2012 movs r0, #18
+ 6e8: 4240 negs r0, r0
+ 6ea: e7f9 b.n 6e0
+ 6ec: 00001f90 .word 0x00001f90
+ 6f0: 00000a69 .word 0x00000a69
+ 6f4: 00000d49 .word 0x00000d49
+ 6f8: 000007b2 .word 0x000007b2
+
+000006fc :
+}
+
+/** \brief Enable the Calendar
+ */
+int32_t calendar_enable(struct calendar_descriptor *const calendar)
+{
+ 6fc: b510 push {r4, lr}
+ 6fe: 0004 movs r4, r0
+ /* Sanity check arguments */
+ ASSERT(calendar);
+ 700: 1e43 subs r3, r0, #1
+ 702: 4198 sbcs r0, r3
+ 704: b2c0 uxtb r0, r0
+ 706: 22e6 movs r2, #230 ; 0xe6
+ 708: 32ff adds r2, #255 ; 0xff
+ 70a: 4904 ldr r1, [pc, #16] ; (71c )
+ 70c: 4b04 ldr r3, [pc, #16] ; (720 )
+ 70e: 4798 blx r3
+
+ _calendar_enable(&calendar->device);
+ 710: 0020 movs r0, r4
+ 712: 4b04 ldr r3, [pc, #16] ; (724 )
+ 714: 4798 blx r3
+
+ return ERR_NONE;
+}
+ 716: 2000 movs r0, #0
+ 718: bd10 pop {r4, pc}
+ 71a: 46c0 nop ; (mov r8, r8)
+ 71c: 00001f90 .word 0x00001f90
+ 720: 00000a69 .word 0x00000a69
+ 724: 00000dd9 .word 0x00000dd9
+
+00000728 :
+}
+
+/** \brief Set time for calendar
+ */
+int32_t calendar_set_time(struct calendar_descriptor *const calendar, struct calendar_time *const p_calendar_time)
+{
+ 728: b530 push {r4, r5, lr}
+ 72a: b083 sub sp, #12
+ 72c: 0004 movs r4, r0
+ 72e: 000d movs r5, r1
+ struct calendar_date_time dt;
+ uint32_t current_ts, new_ts;
+
+ /* Sanity check arguments */
+ ASSERT(calendar);
+ 730: 1e43 subs r3, r0, #1
+ 732: 4198 sbcs r0, r3
+ 734: b2c0 uxtb r0, r0
+ 736: 2283 movs r2, #131 ; 0x83
+ 738: 0092 lsls r2, r2, #2
+ 73a: 490e ldr r1, [pc, #56] ; (774 )
+ 73c: 4b0e ldr r3, [pc, #56] ; (778 )
+ 73e: 4798 blx r3
+
+ /* convert time to timestamp */
+ current_ts = _calendar_get_counter(&calendar->device);
+ 740: 0020 movs r0, r4
+ 742: 4b0e ldr r3, [pc, #56] ; (77c )
+ 744: 4798 blx r3
+ 746: 0001 movs r1, r0
+ convert_timestamp_to_datetime(calendar, current_ts, &dt);
+ 748: 466a mov r2, sp
+ 74a: 0020 movs r0, r4
+ 74c: 4b0c ldr r3, [pc, #48] ; (780 )
+ 74e: 4798 blx r3
+ dt.time.sec = p_calendar_time->sec;
+ 750: 782b ldrb r3, [r5, #0]
+ 752: 466a mov r2, sp
+ 754: 7013 strb r3, [r2, #0]
+ dt.time.min = p_calendar_time->min;
+ 756: 786b ldrb r3, [r5, #1]
+ 758: 7053 strb r3, [r2, #1]
+ dt.time.hour = p_calendar_time->hour;
+ 75a: 78ab ldrb r3, [r5, #2]
+ 75c: 7093 strb r3, [r2, #2]
+
+ new_ts = convert_datetime_to_timestamp(calendar, &dt);
+ 75e: 4669 mov r1, sp
+ 760: 0020 movs r0, r4
+ 762: 4b08 ldr r3, [pc, #32] ; (784 )
+ 764: 4798 blx r3
+ 766: 0001 movs r1, r0
+
+ _calendar_set_counter(&calendar->device, new_ts);
+ 768: 0020 movs r0, r4
+ 76a: 4b07 ldr r3, [pc, #28] ; (788 )
+ 76c: 4798 blx r3
+
+ return ERR_NONE;
+}
+ 76e: 2000 movs r0, #0
+ 770: b003 add sp, #12
+ 772: bd30 pop {r4, r5, pc}
+ 774: 00001f90 .word 0x00001f90
+ 778: 00000a69 .word 0x00000a69
+ 77c: 00000e55 .word 0x00000e55
+ 780: 0000040d .word 0x0000040d
+ 784: 000004b9 .word 0x000004b9
+ 788: 00000e1d .word 0x00000e1d
+
+0000078c :
+
+/** \brief Set date for calendar
+ */
+int32_t calendar_set_date(struct calendar_descriptor *const calendar, struct calendar_date *const p_calendar_date)
+{
+ 78c: b530 push {r4, r5, lr}
+ 78e: b083 sub sp, #12
+ 790: 0004 movs r4, r0
+ 792: 000d movs r5, r1
+ struct calendar_date_time dt;
+ uint32_t current_ts, new_ts;
+
+ /* Sanity check arguments */
+ ASSERT(calendar);
+ 794: 1e43 subs r3, r0, #1
+ 796: 4198 sbcs r0, r3
+ 798: b2c0 uxtb r0, r0
+ 79a: 2289 movs r2, #137 ; 0x89
+ 79c: 0092 lsls r2, r2, #2
+ 79e: 490e ldr r1, [pc, #56] ; (7d8 )
+ 7a0: 4b0e ldr r3, [pc, #56] ; (7dc )
+ 7a2: 4798 blx r3
+
+ /* convert date to timestamp */
+ current_ts = _calendar_get_counter(&calendar->device);
+ 7a4: 0020 movs r0, r4
+ 7a6: 4b0e ldr r3, [pc, #56] ; (7e0 )
+ 7a8: 4798 blx r3
+ 7aa: 0001 movs r1, r0
+ convert_timestamp_to_datetime(calendar, current_ts, &dt);
+ 7ac: 466a mov r2, sp
+ 7ae: 0020 movs r0, r4
+ 7b0: 4b0c ldr r3, [pc, #48] ; (7e4 )
+ 7b2: 4798 blx r3
+ dt.date.day = p_calendar_date->day;
+ 7b4: 782b ldrb r3, [r5, #0]
+ 7b6: 466a mov r2, sp
+ 7b8: 7113 strb r3, [r2, #4]
+ dt.date.month = p_calendar_date->month;
+ 7ba: 786b ldrb r3, [r5, #1]
+ 7bc: 7153 strb r3, [r2, #5]
+ dt.date.year = p_calendar_date->year;
+ 7be: 886b ldrh r3, [r5, #2]
+ 7c0: 80d3 strh r3, [r2, #6]
+
+ new_ts = convert_datetime_to_timestamp(calendar, &dt);
+ 7c2: 4669 mov r1, sp
+ 7c4: 0020 movs r0, r4
+ 7c6: 4b08 ldr r3, [pc, #32] ; (7e8 )
+ 7c8: 4798 blx r3
+ 7ca: 0001 movs r1, r0
+
+ _calendar_set_counter(&calendar->device, new_ts);
+ 7cc: 0020 movs r0, r4
+ 7ce: 4b07 ldr r3, [pc, #28] ; (7ec )
+ 7d0: 4798 blx r3
+
+ return ERR_NONE;
+}
+ 7d2: 2000 movs r0, #0
+ 7d4: b003 add sp, #12
+ 7d6: bd30 pop {r4, r5, pc}
+ 7d8: 00001f90 .word 0x00001f90
+ 7dc: 00000a69 .word 0x00000a69
+ 7e0: 00000e55 .word 0x00000e55
+ 7e4: 0000040d .word 0x0000040d
+ 7e8: 000004b9 .word 0x000004b9
+ 7ec: 00000e1d .word 0x00000e1d
+
+000007f0