b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
223 lines
13 KiB
C
223 lines
13 KiB
C
/**
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* \file
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*
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* \brief Component description for PM
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAML22_PM_COMPONENT_
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#define _SAML22_PM_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR PM */
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/* ========================================================================== */
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/** \addtogroup SAML22_PM Power Manager */
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/*@{*/
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#define PM_U2240
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#define REV_PM 0x211
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/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t :2; /*!< bit: 0.. 1 Reserved */
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uint8_t IORET:1; /*!< bit: 2 I/O Retention */
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uint8_t :5; /*!< bit: 3.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_CTRLA_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_CTRLA_OFFSET 0x00 /**< \brief (PM_CTRLA offset) Control A */
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#define PM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (PM_CTRLA reset_value) Control A */
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#define PM_CTRLA_IORET_Pos 2 /**< \brief (PM_CTRLA) I/O Retention */
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#define PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos)
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#define PM_CTRLA_MASK _U_(0x04) /**< \brief (PM_CTRLA) MASK Register */
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/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */
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uint8_t :5; /*!< bit: 3.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_SLEEPCFG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */
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#define PM_SLEEPCFG_RESETVALUE _U_(0x02) /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */
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#define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */
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#define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
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#define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0) /**< \brief (PM_SLEEPCFG) CPU clock is OFF */
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#define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1) /**< \brief (PM_SLEEPCFG) AHB clock is OFF */
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#define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2) /**< \brief (PM_SLEEPCFG) APB clock are OFF */
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#define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< \brief (PM_SLEEPCFG) All Clocks are OFF */
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#define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x5) /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */
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#define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x6) /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */
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#define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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#define PM_SLEEPCFG_MASK _U_(0x07) /**< \brief (PM_SLEEPCFG) MASK Register */
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/* -------- PM_PLCFG : (PM Offset: 0x02) (R/W 8) Performance Level Configuration -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t PLSEL:2; /*!< bit: 0.. 1 Performance Level Select */
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uint8_t :5; /*!< bit: 2.. 6 Reserved */
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uint8_t PLDIS:1; /*!< bit: 7 Performance Level Disable */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_PLCFG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_PLCFG_OFFSET 0x02 /**< \brief (PM_PLCFG offset) Performance Level Configuration */
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#define PM_PLCFG_RESETVALUE _U_(0x00) /**< \brief (PM_PLCFG reset_value) Performance Level Configuration */
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#define PM_PLCFG_PLSEL_Pos 0 /**< \brief (PM_PLCFG) Performance Level Select */
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#define PM_PLCFG_PLSEL_Msk (_U_(0x3) << PM_PLCFG_PLSEL_Pos)
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#define PM_PLCFG_PLSEL(value) (PM_PLCFG_PLSEL_Msk & ((value) << PM_PLCFG_PLSEL_Pos))
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#define PM_PLCFG_PLSEL_PL0_Val _U_(0x0) /**< \brief (PM_PLCFG) Performance Level 0 */
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#define PM_PLCFG_PLSEL_PL1_Val _U_(0x1) /**< \brief (PM_PLCFG) Performance Level 1 */
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#define PM_PLCFG_PLSEL_PL2_Val _U_(0x2) /**< \brief (PM_PLCFG) Performance Level 2 */
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#define PM_PLCFG_PLSEL_PL0 (PM_PLCFG_PLSEL_PL0_Val << PM_PLCFG_PLSEL_Pos)
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#define PM_PLCFG_PLSEL_PL1 (PM_PLCFG_PLSEL_PL1_Val << PM_PLCFG_PLSEL_Pos)
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#define PM_PLCFG_PLSEL_PL2 (PM_PLCFG_PLSEL_PL2_Val << PM_PLCFG_PLSEL_Pos)
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#define PM_PLCFG_PLDIS_Pos 7 /**< \brief (PM_PLCFG) Performance Level Disable */
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#define PM_PLCFG_PLDIS (_U_(0x1) << PM_PLCFG_PLDIS_Pos)
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#define PM_PLCFG_MASK _U_(0x83) /**< \brief (PM_PLCFG) MASK Register */
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/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t PLRDY:1; /*!< bit: 0 Performance Level Interrupt Enable */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_INTENCLR_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_INTENCLR_OFFSET 0x04 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
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#define PM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
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#define PM_INTENCLR_PLRDY_Pos 0 /**< \brief (PM_INTENCLR) Performance Level Interrupt Enable */
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#define PM_INTENCLR_PLRDY (_U_(0x1) << PM_INTENCLR_PLRDY_Pos)
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#define PM_INTENCLR_MASK _U_(0x01) /**< \brief (PM_INTENCLR) MASK Register */
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/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t PLRDY:1; /*!< bit: 0 Performance Level Ready interrupt Enable */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_INTENSET_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_INTENSET_OFFSET 0x05 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
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#define PM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
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#define PM_INTENSET_PLRDY_Pos 0 /**< \brief (PM_INTENSET) Performance Level Ready interrupt Enable */
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#define PM_INTENSET_PLRDY (_U_(0x1) << PM_INTENSET_PLRDY_Pos)
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#define PM_INTENSET_MASK _U_(0x01) /**< \brief (PM_INTENSET) MASK Register */
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/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union { // __I to avoid read-modify-write on write-to-clear register
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struct {
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__I uint8_t PLRDY:1; /*!< bit: 0 Performance Level Ready */
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__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} PM_INTFLAG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_INTFLAG_OFFSET 0x06 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
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#define PM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
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#define PM_INTFLAG_PLRDY_Pos 0 /**< \brief (PM_INTFLAG) Performance Level Ready */
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#define PM_INTFLAG_PLRDY (_U_(0x1) << PM_INTFLAG_PLRDY_Pos)
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#define PM_INTFLAG_MASK _U_(0x01) /**< \brief (PM_INTFLAG) MASK Register */
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/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 16) Standby Configuration -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint16_t :6; /*!< bit: 0.. 5 Reserved */
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uint16_t VREGSMOD:2; /*!< bit: 6.. 7 Voltage Regulator Standby mode */
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uint16_t :2; /*!< bit: 8.. 9 Reserved */
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uint16_t BBIASHS:2; /*!< bit: 10..11 Back Bias for HMCRAMCHS */
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uint16_t :4; /*!< bit: 12..15 Reserved */
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} bit; /*!< Structure used for bit access */
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uint16_t reg; /*!< Type used for register access */
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} PM_STDBYCFG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */
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#define PM_STDBYCFG_RESETVALUE _U_(0x0400) /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */
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#define PM_STDBYCFG_VREGSMOD_Pos 6 /**< \brief (PM_STDBYCFG) Voltage Regulator Standby mode */
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#define PM_STDBYCFG_VREGSMOD_Msk (_U_(0x3) << PM_STDBYCFG_VREGSMOD_Pos)
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#define PM_STDBYCFG_VREGSMOD(value) (PM_STDBYCFG_VREGSMOD_Msk & ((value) << PM_STDBYCFG_VREGSMOD_Pos))
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#define PM_STDBYCFG_VREGSMOD_AUTO_Val _U_(0x0) /**< \brief (PM_STDBYCFG) Automatic mode */
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#define PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val _U_(0x1) /**< \brief (PM_STDBYCFG) Performance oriented */
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#define PM_STDBYCFG_VREGSMOD_LP_Val _U_(0x2) /**< \brief (PM_STDBYCFG) Low Power oriented */
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#define PM_STDBYCFG_VREGSMOD_AUTO (PM_STDBYCFG_VREGSMOD_AUTO_Val << PM_STDBYCFG_VREGSMOD_Pos)
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#define PM_STDBYCFG_VREGSMOD_PERFORMANCE (PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val << PM_STDBYCFG_VREGSMOD_Pos)
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#define PM_STDBYCFG_VREGSMOD_LP (PM_STDBYCFG_VREGSMOD_LP_Val << PM_STDBYCFG_VREGSMOD_Pos)
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#define PM_STDBYCFG_BBIASHS_Pos 10 /**< \brief (PM_STDBYCFG) Back Bias for HMCRAMCHS */
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#define PM_STDBYCFG_BBIASHS_Msk (_U_(0x3) << PM_STDBYCFG_BBIASHS_Pos)
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#define PM_STDBYCFG_BBIASHS(value) (PM_STDBYCFG_BBIASHS_Msk & ((value) << PM_STDBYCFG_BBIASHS_Pos))
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#define PM_STDBYCFG_MASK _U_(0x0CC0) /**< \brief (PM_STDBYCFG) MASK Register */
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/** \brief PM hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
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__IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */
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__IO PM_PLCFG_Type PLCFG; /**< \brief Offset: 0x02 (R/W 8) Performance Level Configuration */
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RoReg8 Reserved1[0x1];
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__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
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__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
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__IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
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RoReg8 Reserved2[0x1];
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__IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 16) Standby Configuration */
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} Pm;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAML22_PM_COMPONENT_ */
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