b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
110 lines
7.2 KiB
C
110 lines
7.2 KiB
C
/**
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* \file
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*
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* \brief Instance description for TC3
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAML22_TC3_INSTANCE_
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#define _SAML22_TC3_INSTANCE_
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/* ========== Register definition for TC3 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TC3_CTRLA (0x42002C00) /**< \brief (TC3) Control A */
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#define REG_TC3_CTRLBCLR (0x42002C04) /**< \brief (TC3) Control B Clear */
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#define REG_TC3_CTRLBSET (0x42002C05) /**< \brief (TC3) Control B Set */
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#define REG_TC3_EVCTRL (0x42002C06) /**< \brief (TC3) Event Control */
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#define REG_TC3_INTENCLR (0x42002C08) /**< \brief (TC3) Interrupt Enable Clear */
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#define REG_TC3_INTENSET (0x42002C09) /**< \brief (TC3) Interrupt Enable Set */
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#define REG_TC3_INTFLAG (0x42002C0A) /**< \brief (TC3) Interrupt Flag Status and Clear */
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#define REG_TC3_STATUS (0x42002C0B) /**< \brief (TC3) Status */
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#define REG_TC3_WAVE (0x42002C0C) /**< \brief (TC3) Waveform Generation Control */
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#define REG_TC3_DRVCTRL (0x42002C0D) /**< \brief (TC3) Control C */
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#define REG_TC3_DBGCTRL (0x42002C0F) /**< \brief (TC3) Debug Control */
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#define REG_TC3_SYNCBUSY (0x42002C10) /**< \brief (TC3) Synchronization Status */
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#define REG_TC3_COUNT16_COUNT (0x42002C14) /**< \brief (TC3) COUNT16 Count */
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#define REG_TC3_COUNT16_CC0 (0x42002C1C) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
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#define REG_TC3_COUNT16_CC1 (0x42002C1E) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
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#define REG_TC3_COUNT16_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
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#define REG_TC3_COUNT16_CCBUF1 (0x42002C32) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
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#define REG_TC3_COUNT32_COUNT (0x42002C14) /**< \brief (TC3) COUNT32 Count */
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#define REG_TC3_COUNT32_CC0 (0x42002C1C) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
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#define REG_TC3_COUNT32_CC1 (0x42002C20) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
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#define REG_TC3_COUNT32_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
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#define REG_TC3_COUNT32_CCBUF1 (0x42002C34) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
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#define REG_TC3_COUNT8_COUNT (0x42002C14) /**< \brief (TC3) COUNT8 Count */
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#define REG_TC3_COUNT8_PER (0x42002C1B) /**< \brief (TC3) COUNT8 Period */
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#define REG_TC3_COUNT8_CC0 (0x42002C1C) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
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#define REG_TC3_COUNT8_CC1 (0x42002C1D) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
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#define REG_TC3_COUNT8_PERBUF (0x42002C2F) /**< \brief (TC3) COUNT8 Period Buffer */
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#define REG_TC3_COUNT8_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
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#define REG_TC3_COUNT8_CCBUF1 (0x42002C31) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
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#else
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#define REG_TC3_CTRLA (*(RwReg *)0x42002C00UL) /**< \brief (TC3) Control A */
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#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TC3) Control B Clear */
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#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TC3) Control B Set */
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#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C06UL) /**< \brief (TC3) Event Control */
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#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C08UL) /**< \brief (TC3) Interrupt Enable Clear */
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#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C09UL) /**< \brief (TC3) Interrupt Enable Set */
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#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0AUL) /**< \brief (TC3) Interrupt Flag Status and Clear */
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#define REG_TC3_STATUS (*(RwReg8 *)0x42002C0BUL) /**< \brief (TC3) Status */
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#define REG_TC3_WAVE (*(RwReg8 *)0x42002C0CUL) /**< \brief (TC3) Waveform Generation Control */
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#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42002C0DUL) /**< \brief (TC3) Control C */
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#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C0FUL) /**< \brief (TC3) Debug Control */
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#define REG_TC3_SYNCBUSY (*(RoReg *)0x42002C10UL) /**< \brief (TC3) Synchronization Status */
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#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C14UL) /**< \brief (TC3) COUNT16 Count */
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#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C1CUL) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
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#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1EUL) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
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#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42002C30UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
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#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42002C32UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
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#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C14UL) /**< \brief (TC3) COUNT32 Count */
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#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C1CUL) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
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#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C20UL) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
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#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42002C30UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
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#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42002C34UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
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#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C14UL) /**< \brief (TC3) COUNT8 Count */
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#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C1BUL) /**< \brief (TC3) COUNT8 Period */
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#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C1CUL) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
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#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C1DUL) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
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#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42002C2FUL) /**< \brief (TC3) COUNT8 Period Buffer */
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#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42002C30UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
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#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42002C31UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for TC3 peripheral ========== */
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#define TC3_CC_NUM 2
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#define TC3_DMAC_ID_MC_0 29
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#define TC3_DMAC_ID_MC_1 30
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#define TC3_DMAC_ID_MC_LSB 29
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#define TC3_DMAC_ID_MC_MSB 30
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#define TC3_DMAC_ID_MC_SIZE 2
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#define TC3_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger
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#define TC3_EXT 0
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#define TC3_GCLK_ID 24
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#define TC3_MASTER 0
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#define TC3_OW_NUM 2
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#endif /* _SAML22_TC3_INSTANCE_ */
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