597 lines
32 KiB
C
597 lines
32 KiB
C
/**
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* \file
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*
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* \brief Header file for SAML22J16A
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAML22J16A_
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#define _SAML22J16A_
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/**
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* \ingroup SAML22_definitions
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* \addtogroup SAML22J16A_definitions SAML22J16A definitions
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* This file defines all structures and symbols for SAML22J16A:
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* - registers and bitfields
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* - peripheral base address
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* - peripheral ID
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* - PIO definitions
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*/
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/*@{*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#include <stdint.h>
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#ifndef __cplusplus
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typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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#else
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typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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#endif
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typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
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typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
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typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
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typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
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typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
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typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
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#endif
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#if !defined(SKIP_INTEGER_LITERALS)
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#if defined(_U_) || defined(_L_) || defined(_UL_)
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#error "Integer Literals macros already defined elsewhere"
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#endif
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
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#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
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#define _L_(x) x ## L /**< C code: Long integer literal constant value */
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#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
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#else /* Assembler */
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#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
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#define _L_(x) x /**< Assembler: Long integer literal constant value */
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#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* SKIP_INTEGER_LITERALS */
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/* ************************************************************************** */
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/** CMSIS DEFINITIONS FOR SAML22J16A */
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/* ************************************************************************** */
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/** \defgroup SAML22J16A_cmsis CMSIS Definitions */
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/*@{*/
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/** Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M0+ Processor Exceptions Numbers *******************/
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NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
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SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
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PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
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/****** SAML22J16A-specific Interrupt Numbers *********************/
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SYSTEM_IRQn = 0, /**< 0 SAML22J16A System Interrupts */
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WDT_IRQn = 1, /**< 1 SAML22J16A Watchdog Timer (WDT) */
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RTC_IRQn = 2, /**< 2 SAML22J16A Real-Time Counter (RTC) */
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EIC_IRQn = 3, /**< 3 SAML22J16A External Interrupt Controller (EIC) */
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FREQM_IRQn = 4, /**< 4 SAML22J16A Frequency Meter (FREQM) */
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USB_IRQn = 5, /**< 5 SAML22J16A Universal Serial Bus (USB) */
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NVMCTRL_IRQn = 6, /**< 6 SAML22J16A Non-Volatile Memory Controller (NVMCTRL) */
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DMAC_IRQn = 7, /**< 7 SAML22J16A Direct Memory Access Controller (DMAC) */
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EVSYS_IRQn = 8, /**< 8 SAML22J16A Event System Interface (EVSYS) */
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SERCOM0_IRQn = 9, /**< 9 SAML22J16A Serial Communication Interface 0 (SERCOM0) */
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SERCOM1_IRQn = 10, /**< 10 SAML22J16A Serial Communication Interface 1 (SERCOM1) */
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SERCOM2_IRQn = 11, /**< 11 SAML22J16A Serial Communication Interface 2 (SERCOM2) */
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SERCOM3_IRQn = 12, /**< 12 SAML22J16A Serial Communication Interface 3 (SERCOM3) */
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TCC0_IRQn = 15, /**< 15 SAML22J16A Timer Counter Control (TCC0) */
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TC0_IRQn = 16, /**< 16 SAML22J16A Basic Timer Counter 0 (TC0) */
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TC1_IRQn = 17, /**< 17 SAML22J16A Basic Timer Counter 1 (TC1) */
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TC2_IRQn = 18, /**< 18 SAML22J16A Basic Timer Counter 2 (TC2) */
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TC3_IRQn = 19, /**< 19 SAML22J16A Basic Timer Counter 3 (TC3) */
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ADC_IRQn = 20, /**< 20 SAML22J16A Analog Digital Converter (ADC) */
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AC_IRQn = 21, /**< 21 SAML22J16A Analog Comparators (AC) */
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PTC_IRQn = 22, /**< 22 SAML22J16A Peripheral Touch Controller (PTC) */
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SLCD_IRQn = 23, /**< 23 SAML22J16A Segment Liquid Crystal Display Controller (SLCD) */
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AES_IRQn = 24, /**< 24 SAML22J16A Advanced Encryption Standard (AES) */
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TRNG_IRQn = 25, /**< 25 SAML22J16A True Random Generator (TRNG) */
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PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */
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} IRQn_Type;
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typedef struct _DeviceVectors
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{
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/* Stack pointer */
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void* pvStack;
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/* Cortex-M handlers */
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void* pfnReset_Handler;
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void* pfnNonMaskableInt_Handler;
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void* pfnHardFault_Handler;
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void* pvReservedM12;
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void* pvReservedM11;
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void* pvReservedM10;
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void* pvReservedM9;
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void* pvReservedM8;
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void* pvReservedM7;
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void* pvReservedM6;
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void* pfnSVCall_Handler;
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void* pvReservedM4;
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void* pvReservedM3;
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void* pfnPendSV_Handler;
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void* pfnSysTick_Handler;
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/* Peripheral handlers */
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void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
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void* pfnWDT_Handler; /* 1 Watchdog Timer */
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void* pfnRTC_Handler; /* 2 Real-Time Counter */
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void* pfnEIC_Handler; /* 3 External Interrupt Controller */
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void* pfnFREQM_Handler; /* 4 Frequency Meter */
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void* pfnUSB_Handler; /* 5 Universal Serial Bus */
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void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */
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void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */
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void* pfnEVSYS_Handler; /* 8 Event System Interface */
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void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
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void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
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void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
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void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
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void* pvReserved13;
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void* pvReserved14;
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void* pfnTCC0_Handler; /* 15 Timer Counter Control */
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void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */
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void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */
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void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */
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void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */
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void* pfnADC_Handler; /* 20 Analog Digital Converter */
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void* pfnAC_Handler; /* 21 Analog Comparators */
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void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */
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void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */
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void* pfnAES_Handler; /* 24 Advanced Encryption Standard */
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void* pfnTRNG_Handler; /* 25 True Random Generator */
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} DeviceVectors;
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/* Cortex-M0+ processor handlers */
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void Reset_Handler ( void );
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void NonMaskableInt_Handler ( void );
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void HardFault_Handler ( void );
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void SVCall_Handler ( void );
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void PendSV_Handler ( void );
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void SysTick_Handler ( void );
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/* Peripherals handlers */
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void SYSTEM_Handler ( void );
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void WDT_Handler ( void );
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void RTC_Handler ( void );
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void EIC_Handler ( void );
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void FREQM_Handler ( void );
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void USB_Handler ( void );
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void NVMCTRL_Handler ( void );
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void DMAC_Handler ( void );
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void EVSYS_Handler ( void );
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void SERCOM0_Handler ( void );
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void SERCOM1_Handler ( void );
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void SERCOM2_Handler ( void );
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void SERCOM3_Handler ( void );
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void TCC0_Handler ( void );
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void TC0_Handler ( void );
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void TC1_Handler ( void );
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void TC2_Handler ( void );
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void TC3_Handler ( void );
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void ADC_Handler ( void );
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void AC_Handler ( void );
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void PTC_Handler ( void );
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void SLCD_Handler ( void );
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void AES_Handler ( void );
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void TRNG_Handler ( void );
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/*
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* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
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*/
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#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
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#define __VTOR_PRESENT 1 /*!< VTOR present or not */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* \brief CMSIS includes
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*/
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#include <core_cm0plus.h>
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#if !defined DONT_USE_CMSIS_INIT
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#include "system_saml22.h"
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#endif /* DONT_USE_CMSIS_INIT */
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/*@}*/
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/* ************************************************************************** */
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/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22J16A */
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/* ************************************************************************** */
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/** \defgroup SAML22J16A_api Peripheral Software API */
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/*@{*/
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#include "component/ac.h"
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#include "component/adc.h"
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#include "component/aes.h"
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#include "component/ccl.h"
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#include "component/dmac.h"
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#include "component/dsu.h"
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#include "component/eic.h"
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#include "component/evsys.h"
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#include "component/freqm.h"
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#include "component/gclk.h"
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#include "component/mclk.h"
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#include "component/mtb.h"
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#include "component/nvmctrl.h"
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#include "component/oscctrl.h"
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#include "component/osc32kctrl.h"
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#include "component/pac.h"
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#include "component/pm.h"
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#include "component/port.h"
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#include "component/rstc.h"
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#include "component/rtc.h"
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#include "component/sercom.h"
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#include "component/slcd.h"
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#include "component/supc.h"
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#include "component/tc.h"
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#include "component/tcc.h"
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#include "component/trng.h"
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#include "component/usb.h"
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#include "component/wdt.h"
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/*@}*/
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/* ************************************************************************** */
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/** REGISTERS ACCESS DEFINITIONS FOR SAML22J16A */
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/* ************************************************************************** */
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/** \defgroup SAML22J16A_reg Registers Access Definitions */
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/*@{*/
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#include "instance/ac.h"
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#include "instance/adc.h"
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#include "instance/aes.h"
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#include "instance/ccl.h"
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#include "instance/dmac.h"
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#include "instance/dsu.h"
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#include "instance/eic.h"
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#include "instance/evsys.h"
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#include "instance/freqm.h"
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#include "instance/gclk.h"
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#include "instance/mclk.h"
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#include "instance/mtb.h"
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#include "instance/nvmctrl.h"
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#include "instance/oscctrl.h"
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#include "instance/osc32kctrl.h"
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#include "instance/pac.h"
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#include "instance/pm.h"
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#include "instance/port.h"
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#include "instance/ptc.h"
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#include "instance/rstc.h"
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#include "instance/rtc.h"
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#include "instance/sercom0.h"
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#include "instance/sercom1.h"
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#include "instance/sercom2.h"
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#include "instance/sercom3.h"
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#include "instance/slcd.h"
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#include "instance/supc.h"
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#include "instance/tc0.h"
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#include "instance/tc1.h"
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#include "instance/tc2.h"
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#include "instance/tc3.h"
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#include "instance/tcc0.h"
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#include "instance/trng.h"
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#include "instance/usb.h"
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#include "instance/wdt.h"
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/*@}*/
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/* ************************************************************************** */
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/** PERIPHERAL ID DEFINITIONS FOR SAML22J16A */
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/* ************************************************************************** */
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/** \defgroup SAML22J16A_id Peripheral Ids Definitions */
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/*@{*/
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// Peripheral instances on HPB0 bridge
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#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
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#define ID_PM 1 /**< \brief Power Manager (PM) */
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#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
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#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
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#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
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#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */
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#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
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#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
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#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
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#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
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#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
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#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
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// Peripheral instances on HPB1 bridge
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#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */
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#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
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#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
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#define ID_PORT 35 /**< \brief Port Module (PORT) */
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#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
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#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
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// Peripheral instances on HPB2 bridge
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#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */
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#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */
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#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */
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#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */
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#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */
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#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */
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#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */
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#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */
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#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */
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#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
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#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */
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#define ID_AC 77 /**< \brief Analog Comparators (AC) */
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#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */
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#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */
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#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */
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#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */
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#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */
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#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */
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/*@}*/
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/* ************************************************************************** */
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/** BASE ADDRESS DEFINITIONS FOR SAML22J16A */
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/* ************************************************************************** */
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/** \defgroup SAML22J16A_base Peripheral Base Address Definitions */
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/*@{*/
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#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
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#define AC (0x42003400) /**< \brief (AC) APB Base Address */
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#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */
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#define AES (0x42004000) /**< \brief (AES) APB Base Address */
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#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */
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#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */
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#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
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#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
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#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */
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#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
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#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
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#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
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#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */
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#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
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#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
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#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
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#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
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#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
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#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */
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#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */
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#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */
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#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
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#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
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#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
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#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
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#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
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#define PM (0x40000400) /**< \brief (PM) APB Base Address */
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#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */
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#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
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#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */
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#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
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#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
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#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */
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#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */
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#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */
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#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */
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#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */
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#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
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#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */
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#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */
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#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */
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#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
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#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */
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#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */
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#define USB (0x41000000) /**< \brief (USB) APB Base Address */
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#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
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#else
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#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */
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#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
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#define AC_INSTS { AC } /**< \brief (AC) Instances List */
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#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */
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#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
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#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
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#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */
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#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */
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#define AES_INSTS { AES } /**< \brief (AES) Instances List */
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#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */
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#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
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#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
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#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */
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#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
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#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
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#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
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#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
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#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
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#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
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#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
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#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
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#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */
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#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
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#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
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#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
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#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
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#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
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#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
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#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
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#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
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#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
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#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
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#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
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#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */
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#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
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#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
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#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
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#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
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#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
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#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
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#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
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#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */
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#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */
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#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */
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#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
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#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
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#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
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#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
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#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
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#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
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#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
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#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
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#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
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#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
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#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
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#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
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#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
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#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
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#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
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#define PM_INSTS { PM } /**< \brief (PM) Instances List */
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#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */
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#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
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#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
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#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
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#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
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#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
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#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */
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#define PTC_GCLK_ID 27
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#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
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#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
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#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
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#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
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#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
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#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
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#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
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#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
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#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */
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#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */
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#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */
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#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */
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#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
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#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
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#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */
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#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */
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#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */
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#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
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#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
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#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
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#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */
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#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */
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#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */
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#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
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#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */
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#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */
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#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */
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#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */
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#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */
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#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */
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#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */
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#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */
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#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */
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#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
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#define USB_INSTS { USB } /**< \brief (USB) Instances List */
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#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
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#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
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#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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/* ************************************************************************** */
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/** PORT DEFINITIONS FOR SAML22J16A */
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/* ************************************************************************** */
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/** \defgroup SAML22J16A_port PORT Definitions */
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/*@{*/
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#include "pio/saml22j16a.h"
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/*@}*/
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/* ************************************************************************** */
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/** MEMORY MAPPING DEFINITIONS FOR SAML22J16A */
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/* ************************************************************************** */
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#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */
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#define FLASH_PAGE_SIZE 64
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#define FLASH_NB_OF_PAGES 1024
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#define FLASH_USER_PAGE_SIZE 64
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#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */
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#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
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#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
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#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
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#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
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#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
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#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
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#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
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#define DSU_DID_RESETVALUE _UL_(0x10820107)
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#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */
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#define PORT_GROUPS 2
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/* ************************************************************************** */
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/** ELECTRICAL DEFINITIONS FOR SAML22J16A */
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/* ************************************************************************** */
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#ifdef __cplusplus
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}
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#endif
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/*@}*/
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#endif /* SAML22J16A_H */
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