127 lines
6.7 KiB
C
Executable File
127 lines
6.7 KiB
C
Executable File
/**
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* \file
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*
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* \brief Component description for RSTC
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*
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* Copyright (c) 2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAML22_RSTC_COMPONENT_
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#define _SAML22_RSTC_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR RSTC */
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/* ========================================================================== */
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/** \addtogroup SAML22_RSTC Reset Controller */
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/*@{*/
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#define RSTC_U2239
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#define REV_RSTC 0x300
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/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t POR:1; /*!< bit: 0 Power On Reset */
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uint8_t BODCORE:1; /*!< bit: 1 Brown Out CORE Detector Reset */
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uint8_t BODVDD:1; /*!< bit: 2 Brown Out VDD Detector Reset */
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uint8_t :1; /*!< bit: 3 Reserved */
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uint8_t EXT:1; /*!< bit: 4 External Reset */
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uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
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uint8_t SYST:1; /*!< bit: 6 System Reset Request */
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uint8_t BACKUP:1; /*!< bit: 7 Backup Reset */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} RSTC_RCAUSE_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */
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#define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */
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#define RSTC_RCAUSE_POR (0x1ul << RSTC_RCAUSE_POR_Pos)
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#define RSTC_RCAUSE_BODCORE_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out CORE Detector Reset */
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#define RSTC_RCAUSE_BODCORE (0x1ul << RSTC_RCAUSE_BODCORE_Pos)
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#define RSTC_RCAUSE_BODVDD_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out VDD Detector Reset */
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#define RSTC_RCAUSE_BODVDD (0x1ul << RSTC_RCAUSE_BODVDD_Pos)
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#define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */
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#define RSTC_RCAUSE_EXT (0x1ul << RSTC_RCAUSE_EXT_Pos)
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#define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */
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#define RSTC_RCAUSE_WDT (0x1ul << RSTC_RCAUSE_WDT_Pos)
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#define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */
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#define RSTC_RCAUSE_SYST (0x1ul << RSTC_RCAUSE_SYST_Pos)
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#define RSTC_RCAUSE_BACKUP_Pos 7 /**< \brief (RSTC_RCAUSE) Backup Reset */
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#define RSTC_RCAUSE_BACKUP (0x1ul << RSTC_RCAUSE_BACKUP_Pos)
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#define RSTC_RCAUSE_MASK 0xF7ul /**< \brief (RSTC_RCAUSE) MASK Register */
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/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/ 8) Backup Exit Source -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t EXTWAKE:1; /*!< bit: 0 External Wakeup */
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uint8_t RTC:1; /*!< bit: 1 Real Timer Counter Interrupt */
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uint8_t BBPS:1; /*!< bit: 2 Battery Backup Power Switch */
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uint8_t :5; /*!< bit: 3.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} RSTC_BKUPEXIT_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RSTC_BKUPEXIT_OFFSET 0x02 /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */
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#define RSTC_BKUPEXIT_RESETVALUE 0x00ul /**< \brief (RSTC_BKUPEXIT reset_value) Backup Exit Source */
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#define RSTC_BKUPEXIT_EXTWAKE_Pos 0 /**< \brief (RSTC_BKUPEXIT) External Wakeup */
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#define RSTC_BKUPEXIT_EXTWAKE (0x1ul << RSTC_BKUPEXIT_EXTWAKE_Pos)
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#define RSTC_BKUPEXIT_RTC_Pos 1 /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */
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#define RSTC_BKUPEXIT_RTC (0x1ul << RSTC_BKUPEXIT_RTC_Pos)
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#define RSTC_BKUPEXIT_BBPS_Pos 2 /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */
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#define RSTC_BKUPEXIT_BBPS (0x1ul << RSTC_BKUPEXIT_BBPS_Pos)
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#define RSTC_BKUPEXIT_MASK 0x07ul /**< \brief (RSTC_BKUPEXIT) MASK Register */
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/** \brief RSTC hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */
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RoReg8 Reserved1[0x1];
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__I RSTC_BKUPEXIT_Type BKUPEXIT; /**< \brief Offset: 0x02 (R/ 8) Backup Exit Source */
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} Rstc;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAML22_RSTC_COMPONENT_ */
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