104 lines
6.5 KiB
C
Executable File
104 lines
6.5 KiB
C
Executable File
/**
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* \file
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*
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* \brief Instance description for ADC
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*
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* Copyright (c) 2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAML22_ADC_INSTANCE_
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#define _SAML22_ADC_INSTANCE_
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/* ========== Register definition for ADC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_ADC_CTRLA (0x42003000U) /**< \brief (ADC) Control A */
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#define REG_ADC_CTRLB (0x42003001U) /**< \brief (ADC) Control B */
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#define REG_ADC_REFCTRL (0x42003002U) /**< \brief (ADC) Reference Control */
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#define REG_ADC_EVCTRL (0x42003003U) /**< \brief (ADC) Event Control */
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#define REG_ADC_INTENCLR (0x42003004U) /**< \brief (ADC) Interrupt Enable Clear */
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#define REG_ADC_INTENSET (0x42003005U) /**< \brief (ADC) Interrupt Enable Set */
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#define REG_ADC_INTFLAG (0x42003006U) /**< \brief (ADC) Interrupt Flag Status and Clear */
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#define REG_ADC_SEQSTATUS (0x42003007U) /**< \brief (ADC) Sequence Status */
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#define REG_ADC_INPUTCTRL (0x42003008U) /**< \brief (ADC) Input Control */
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#define REG_ADC_CTRLC (0x4200300AU) /**< \brief (ADC) Control C */
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#define REG_ADC_AVGCTRL (0x4200300CU) /**< \brief (ADC) Average Control */
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#define REG_ADC_SAMPCTRL (0x4200300DU) /**< \brief (ADC) Sample Time Control */
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#define REG_ADC_WINLT (0x4200300EU) /**< \brief (ADC) Window Monitor Lower Threshold */
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#define REG_ADC_WINUT (0x42003010U) /**< \brief (ADC) Window Monitor Upper Threshold */
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#define REG_ADC_GAINCORR (0x42003012U) /**< \brief (ADC) Gain Correction */
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#define REG_ADC_OFFSETCORR (0x42003014U) /**< \brief (ADC) Offset Correction */
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#define REG_ADC_SWTRIG (0x42003018U) /**< \brief (ADC) Software Trigger */
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#define REG_ADC_DBGCTRL (0x4200301CU) /**< \brief (ADC) Debug Control */
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#define REG_ADC_SYNCBUSY (0x42003020U) /**< \brief (ADC) Synchronization Busy */
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#define REG_ADC_RESULT (0x42003024U) /**< \brief (ADC) Result */
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#define REG_ADC_SEQCTRL (0x42003028U) /**< \brief (ADC) Sequence Control */
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#define REG_ADC_CALIB (0x4200302CU) /**< \brief (ADC) Calibration */
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#else
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#define REG_ADC_CTRLA (*(RwReg8 *)0x42003000U) /**< \brief (ADC) Control A */
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#define REG_ADC_CTRLB (*(RwReg8 *)0x42003001U) /**< \brief (ADC) Control B */
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#define REG_ADC_REFCTRL (*(RwReg8 *)0x42003002U) /**< \brief (ADC) Reference Control */
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#define REG_ADC_EVCTRL (*(RwReg8 *)0x42003003U) /**< \brief (ADC) Event Control */
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#define REG_ADC_INTENCLR (*(RwReg8 *)0x42003004U) /**< \brief (ADC) Interrupt Enable Clear */
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#define REG_ADC_INTENSET (*(RwReg8 *)0x42003005U) /**< \brief (ADC) Interrupt Enable Set */
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#define REG_ADC_INTFLAG (*(RwReg8 *)0x42003006U) /**< \brief (ADC) Interrupt Flag Status and Clear */
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#define REG_ADC_SEQSTATUS (*(RoReg8 *)0x42003007U) /**< \brief (ADC) Sequence Status */
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#define REG_ADC_INPUTCTRL (*(RwReg16*)0x42003008U) /**< \brief (ADC) Input Control */
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#define REG_ADC_CTRLC (*(RwReg16*)0x4200300AU) /**< \brief (ADC) Control C */
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#define REG_ADC_AVGCTRL (*(RwReg8 *)0x4200300CU) /**< \brief (ADC) Average Control */
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#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x4200300DU) /**< \brief (ADC) Sample Time Control */
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#define REG_ADC_WINLT (*(RwReg16*)0x4200300EU) /**< \brief (ADC) Window Monitor Lower Threshold */
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#define REG_ADC_WINUT (*(RwReg16*)0x42003010U) /**< \brief (ADC) Window Monitor Upper Threshold */
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#define REG_ADC_GAINCORR (*(RwReg16*)0x42003012U) /**< \brief (ADC) Gain Correction */
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#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42003014U) /**< \brief (ADC) Offset Correction */
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#define REG_ADC_SWTRIG (*(RwReg8 *)0x42003018U) /**< \brief (ADC) Software Trigger */
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#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200301CU) /**< \brief (ADC) Debug Control */
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#define REG_ADC_SYNCBUSY (*(RoReg16*)0x42003020U) /**< \brief (ADC) Synchronization Busy */
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#define REG_ADC_RESULT (*(RoReg16*)0x42003024U) /**< \brief (ADC) Result */
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#define REG_ADC_SEQCTRL (*(RwReg *)0x42003028U) /**< \brief (ADC) Sequence Control */
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#define REG_ADC_CALIB (*(RwReg16*)0x4200302CU) /**< \brief (ADC) Calibration */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for ADC peripheral ========== */
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#define ADC_DMAC_ID_RESRDY 31 // index of DMA RESRDY trigger
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#define ADC_EXTCHANNEL_MSB 19 // Number of external channels
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#define ADC_GCLK_ID 25 // index of Generic Clock
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#define ADC_INT_CH30 2 // Select OPAMP or CTAT on Channel 30
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#define ADC_MASTER_SLAVE_MODE 0 // ADC Master/Slave Mode
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#endif /* _SAML22_ADC_INSTANCE_ */
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