b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
87 lines
5.3 KiB
C
87 lines
5.3 KiB
C
/**
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* \file
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*
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* \brief Instance description for OSCCTRL
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAML22_OSCCTRL_INSTANCE_
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#define _SAML22_OSCCTRL_INSTANCE_
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/* ========== Register definition for OSCCTRL peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_OSCCTRL_INTENCLR (0x40001000) /**< \brief (OSCCTRL) Interrupt Enable Clear */
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#define REG_OSCCTRL_INTENSET (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Set */
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#define REG_OSCCTRL_INTFLAG (0x40001008) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
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#define REG_OSCCTRL_STATUS (0x4000100C) /**< \brief (OSCCTRL) Power and Clocks Status */
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#define REG_OSCCTRL_XOSCCTRL (0x40001010) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
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#define REG_OSCCTRL_CFDPRESC (0x40001012) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */
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#define REG_OSCCTRL_EVCTRL (0x40001013) /**< \brief (OSCCTRL) Event Control */
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#define REG_OSCCTRL_OSC16MCTRL (0x40001014) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */
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#define REG_OSCCTRL_DFLLCTRL (0x40001018) /**< \brief (OSCCTRL) DFLL48M Control */
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#define REG_OSCCTRL_DFLLVAL (0x4000101C) /**< \brief (OSCCTRL) DFLL48M Value */
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#define REG_OSCCTRL_DFLLMUL (0x40001020) /**< \brief (OSCCTRL) DFLL48M Multiplier */
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#define REG_OSCCTRL_DFLLSYNC (0x40001024) /**< \brief (OSCCTRL) DFLL48M Synchronization */
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#define REG_OSCCTRL_DPLLCTRLA (0x40001028) /**< \brief (OSCCTRL) DPLL Control */
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#define REG_OSCCTRL_DPLLRATIO (0x4000102C) /**< \brief (OSCCTRL) DPLL Ratio Control */
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#define REG_OSCCTRL_DPLLCTRLB (0x40001030) /**< \brief (OSCCTRL) Digital Core Configuration */
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#define REG_OSCCTRL_DPLLPRESC (0x40001034) /**< \brief (OSCCTRL) DPLL Prescaler */
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#define REG_OSCCTRL_DPLLSYNCBUSY (0x40001038) /**< \brief (OSCCTRL) DPLL Synchronization Busy */
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#define REG_OSCCTRL_DPLLSTATUS (0x4000103C) /**< \brief (OSCCTRL) DPLL Status */
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#else
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#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001000UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */
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#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Set */
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#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
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#define REG_OSCCTRL_STATUS (*(RoReg *)0x4000100CUL) /**< \brief (OSCCTRL) Power and Clocks Status */
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#define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40001010UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
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#define REG_OSCCTRL_CFDPRESC (*(RwReg8 *)0x40001012UL) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */
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#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001013UL) /**< \brief (OSCCTRL) Event Control */
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#define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40001014UL) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */
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#define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40001018UL) /**< \brief (OSCCTRL) DFLL48M Control */
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#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x4000101CUL) /**< \brief (OSCCTRL) DFLL48M Value */
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#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001020UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */
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#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40001024UL) /**< \brief (OSCCTRL) DFLL48M Synchronization */
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#define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40001028UL) /**< \brief (OSCCTRL) DPLL Control */
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#define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x4000102CUL) /**< \brief (OSCCTRL) DPLL Ratio Control */
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#define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40001030UL) /**< \brief (OSCCTRL) Digital Core Configuration */
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#define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40001034UL) /**< \brief (OSCCTRL) DPLL Prescaler */
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#define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40001038UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy */
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#define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x4000103CUL) /**< \brief (OSCCTRL) DPLL Status */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for OSCCTRL peripheral ========== */
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#define OSCCTRL_DFLL48M_COARSE_MSB 5
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#define OSCCTRL_DFLL48M_FINE_MSB 9
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#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
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#define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
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#define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
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#define OSCCTRL_CFD_VERSION 0x100
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#define OSCCTRL_DFLL48M_VERSION 0x320
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#define OSCCTRL_FDPLL_VERSION 0x211
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#define OSCCTRL_OSC16M_VERSION 0x101
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#define OSCCTRL_XOSC_VERSION 0x201
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#endif /* _SAML22_OSCCTRL_INSTANCE_ */
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