b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
143 lines
11 KiB
C
143 lines
11 KiB
C
/**
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* \file
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*
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* \brief Instance description for SERCOM5
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAML22_SERCOM5_INSTANCE_
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#define _SAML22_SERCOM5_INSTANCE_
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/* ========== Register definition for SERCOM5 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SERCOM5_I2CM_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CM Control A */
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#define REG_SERCOM5_I2CM_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CM Control B */
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#define REG_SERCOM5_I2CM_BAUD (0x4200180C) /**< \brief (SERCOM5) I2CM Baud Rate */
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#define REG_SERCOM5_I2CM_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
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#define REG_SERCOM5_I2CM_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
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#define REG_SERCOM5_I2CM_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
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#define REG_SERCOM5_I2CM_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CM Status */
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#define REG_SERCOM5_I2CM_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CM Synchronization Busy */
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#define REG_SERCOM5_I2CM_ADDR (0x42001824) /**< \brief (SERCOM5) I2CM Address */
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#define REG_SERCOM5_I2CM_DATA (0x42001828) /**< \brief (SERCOM5) I2CM Data */
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#define REG_SERCOM5_I2CM_DBGCTRL (0x42001830) /**< \brief (SERCOM5) I2CM Debug Control */
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#define REG_SERCOM5_I2CS_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CS Control A */
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#define REG_SERCOM5_I2CS_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CS Control B */
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#define REG_SERCOM5_I2CS_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
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#define REG_SERCOM5_I2CS_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
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#define REG_SERCOM5_I2CS_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
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#define REG_SERCOM5_I2CS_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CS Status */
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#define REG_SERCOM5_I2CS_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CS Synchronization Busy */
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#define REG_SERCOM5_I2CS_ADDR (0x42001824) /**< \brief (SERCOM5) I2CS Address */
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#define REG_SERCOM5_I2CS_DATA (0x42001828) /**< \brief (SERCOM5) I2CS Data */
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#define REG_SERCOM5_SPI_CTRLA (0x42001800) /**< \brief (SERCOM5) SPI Control A */
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#define REG_SERCOM5_SPI_CTRLB (0x42001804) /**< \brief (SERCOM5) SPI Control B */
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#define REG_SERCOM5_SPI_BAUD (0x4200180C) /**< \brief (SERCOM5) SPI Baud Rate */
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#define REG_SERCOM5_SPI_INTENCLR (0x42001814) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
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#define REG_SERCOM5_SPI_INTENSET (0x42001816) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
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#define REG_SERCOM5_SPI_INTFLAG (0x42001818) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
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#define REG_SERCOM5_SPI_STATUS (0x4200181A) /**< \brief (SERCOM5) SPI Status */
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#define REG_SERCOM5_SPI_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) SPI Synchronization Busy */
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#define REG_SERCOM5_SPI_ADDR (0x42001824) /**< \brief (SERCOM5) SPI Address */
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#define REG_SERCOM5_SPI_DATA (0x42001828) /**< \brief (SERCOM5) SPI Data */
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#define REG_SERCOM5_SPI_DBGCTRL (0x42001830) /**< \brief (SERCOM5) SPI Debug Control */
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#define REG_SERCOM5_USART_CTRLA (0x42001800) /**< \brief (SERCOM5) USART Control A */
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#define REG_SERCOM5_USART_CTRLB (0x42001804) /**< \brief (SERCOM5) USART Control B */
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#define REG_SERCOM5_USART_CTRLC (0x42001808) /**< \brief (SERCOM5) USART Control C */
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#define REG_SERCOM5_USART_BAUD (0x4200180C) /**< \brief (SERCOM5) USART Baud Rate */
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#define REG_SERCOM5_USART_RXPL (0x4200180E) /**< \brief (SERCOM5) USART Receive Pulse Length */
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#define REG_SERCOM5_USART_INTENCLR (0x42001814) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
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#define REG_SERCOM5_USART_INTENSET (0x42001816) /**< \brief (SERCOM5) USART Interrupt Enable Set */
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#define REG_SERCOM5_USART_INTFLAG (0x42001818) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
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#define REG_SERCOM5_USART_STATUS (0x4200181A) /**< \brief (SERCOM5) USART Status */
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#define REG_SERCOM5_USART_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) USART Synchronization Busy */
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#define REG_SERCOM5_USART_RXERRCNT (0x42001820) /**< \brief (SERCOM5) USART Receive Error Count */
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#define REG_SERCOM5_USART_DATA (0x42001828) /**< \brief (SERCOM5) USART Data */
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#define REG_SERCOM5_USART_DBGCTRL (0x42001830) /**< \brief (SERCOM5) USART Debug Control */
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#else
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#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CM Control A */
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#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CM Control B */
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#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4200180CUL) /**< \brief (SERCOM5) I2CM Baud Rate */
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#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
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#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
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#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
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#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CM Status */
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#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CM Synchronization Busy */
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#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CM Address */
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#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CM Data */
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#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) I2CM Debug Control */
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#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CS Control A */
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#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CS Control B */
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#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
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#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
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#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
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#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CS Status */
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#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CS Synchronization Busy */
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#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CS Address */
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#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CS Data */
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#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) SPI Control A */
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#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) SPI Control B */
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#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM5) SPI Baud Rate */
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#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
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#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
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#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
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#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) SPI Status */
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#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) SPI Synchronization Busy */
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#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) SPI Address */
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#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001828UL) /**< \brief (SERCOM5) SPI Data */
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#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) SPI Debug Control */
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#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) USART Control A */
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#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) USART Control B */
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#define REG_SERCOM5_USART_CTRLC (*(RwReg *)0x42001808UL) /**< \brief (SERCOM5) USART Control C */
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#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4200180CUL) /**< \brief (SERCOM5) USART Baud Rate */
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#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */
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#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
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#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */
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#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
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#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) USART Status */
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#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) USART Synchronization Busy */
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#define REG_SERCOM5_USART_RXERRCNT (*(RoReg8 *)0x42001820UL) /**< \brief (SERCOM5) USART Receive Error Count */
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#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001828UL) /**< \brief (SERCOM5) USART Data */
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#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) USART Debug Control */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for SERCOM5 peripheral ========== */
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#define SERCOM5_DMAC_ID_RX 12 // Index of DMA RX trigger
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#define SERCOM5_DMAC_ID_TX 13 // Index of DMA TX trigger
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#define SERCOM5_GCLK_ID_CORE 21
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#define SERCOM5_GCLK_ID_SLOW 15
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#define SERCOM5_INT_MSB 3
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#define SERCOM5_PMSB 3
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#define SERCOM5_SPI 1 // SPI mode implemented?
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#define SERCOM5_TWIM 1 // TWI Master mode implemented?
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#define SERCOM5_TWIS 1 // TWI Slave mode implemented?
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#define SERCOM5_TWI_HSMODE 1 // TWI HighSpeed mode implemented?
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#define SERCOM5_USART 1 // USART mode implemented?
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#define SERCOM5_USART_ISO7816 1 // USART ISO7816 mode implemented?
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#define SERCOM5_USART_LIN_MASTER 0 // USART LIN Master mode implemented?
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#define SERCOM5_USART_RS485 1 // USART RS485 mode implemented?
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#endif /* _SAML22_SERCOM5_INSTANCE_ */
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