b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
110 lines
7.2 KiB
C
110 lines
7.2 KiB
C
/**
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* \file
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*
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* \brief Instance description for TC0
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAML22_TC0_INSTANCE_
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#define _SAML22_TC0_INSTANCE_
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/* ========== Register definition for TC0 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TC0_CTRLA (0x42002000) /**< \brief (TC0) Control A */
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#define REG_TC0_CTRLBCLR (0x42002004) /**< \brief (TC0) Control B Clear */
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#define REG_TC0_CTRLBSET (0x42002005) /**< \brief (TC0) Control B Set */
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#define REG_TC0_EVCTRL (0x42002006) /**< \brief (TC0) Event Control */
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#define REG_TC0_INTENCLR (0x42002008) /**< \brief (TC0) Interrupt Enable Clear */
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#define REG_TC0_INTENSET (0x42002009) /**< \brief (TC0) Interrupt Enable Set */
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#define REG_TC0_INTFLAG (0x4200200A) /**< \brief (TC0) Interrupt Flag Status and Clear */
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#define REG_TC0_STATUS (0x4200200B) /**< \brief (TC0) Status */
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#define REG_TC0_WAVE (0x4200200C) /**< \brief (TC0) Waveform Generation Control */
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#define REG_TC0_DRVCTRL (0x4200200D) /**< \brief (TC0) Control C */
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#define REG_TC0_DBGCTRL (0x4200200F) /**< \brief (TC0) Debug Control */
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#define REG_TC0_SYNCBUSY (0x42002010) /**< \brief (TC0) Synchronization Status */
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#define REG_TC0_COUNT16_COUNT (0x42002014) /**< \brief (TC0) COUNT16 Count */
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#define REG_TC0_COUNT16_CC0 (0x4200201C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
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#define REG_TC0_COUNT16_CC1 (0x4200201E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
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#define REG_TC0_COUNT16_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
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#define REG_TC0_COUNT16_CCBUF1 (0x42002032) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
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#define REG_TC0_COUNT32_COUNT (0x42002014) /**< \brief (TC0) COUNT32 Count */
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#define REG_TC0_COUNT32_CC0 (0x4200201C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
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#define REG_TC0_COUNT32_CC1 (0x42002020) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
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#define REG_TC0_COUNT32_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
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#define REG_TC0_COUNT32_CCBUF1 (0x42002034) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
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#define REG_TC0_COUNT8_COUNT (0x42002014) /**< \brief (TC0) COUNT8 Count */
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#define REG_TC0_COUNT8_PER (0x4200201B) /**< \brief (TC0) COUNT8 Period */
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#define REG_TC0_COUNT8_CC0 (0x4200201C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
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#define REG_TC0_COUNT8_CC1 (0x4200201D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
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#define REG_TC0_COUNT8_PERBUF (0x4200202F) /**< \brief (TC0) COUNT8 Period Buffer */
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#define REG_TC0_COUNT8_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
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#define REG_TC0_COUNT8_CCBUF1 (0x42002031) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
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#else
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#define REG_TC0_CTRLA (*(RwReg *)0x42002000UL) /**< \brief (TC0) Control A */
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#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004UL) /**< \brief (TC0) Control B Clear */
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#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005UL) /**< \brief (TC0) Control B Set */
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#define REG_TC0_EVCTRL (*(RwReg16*)0x42002006UL) /**< \brief (TC0) Event Control */
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#define REG_TC0_INTENCLR (*(RwReg8 *)0x42002008UL) /**< \brief (TC0) Interrupt Enable Clear */
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#define REG_TC0_INTENSET (*(RwReg8 *)0x42002009UL) /**< \brief (TC0) Interrupt Enable Set */
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#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */
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#define REG_TC0_STATUS (*(RwReg8 *)0x4200200BUL) /**< \brief (TC0) Status */
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#define REG_TC0_WAVE (*(RwReg8 *)0x4200200CUL) /**< \brief (TC0) Waveform Generation Control */
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#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200200DUL) /**< \brief (TC0) Control C */
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#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200200FUL) /**< \brief (TC0) Debug Control */
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#define REG_TC0_SYNCBUSY (*(RoReg *)0x42002010UL) /**< \brief (TC0) Synchronization Status */
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#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002014UL) /**< \brief (TC0) COUNT16 Count */
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#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4200201CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
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#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
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#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x42002030UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
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#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x42002032UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
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#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002014UL) /**< \brief (TC0) COUNT32 Count */
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#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200201CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
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#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42002020UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
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#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42002030UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
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#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42002034UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
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#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002014UL) /**< \brief (TC0) COUNT8 Count */
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#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4200201BUL) /**< \brief (TC0) COUNT8 Period */
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#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4200201CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
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#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4200201DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
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#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4200202FUL) /**< \brief (TC0) COUNT8 Period Buffer */
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#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x42002030UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
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#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x42002031UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for TC0 peripheral ========== */
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#define TC0_CC_NUM 2
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#define TC0_DMAC_ID_MC_0 20
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#define TC0_DMAC_ID_MC_1 21
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#define TC0_DMAC_ID_MC_LSB 20
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#define TC0_DMAC_ID_MC_MSB 21
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#define TC0_DMAC_ID_MC_SIZE 2
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#define TC0_DMAC_ID_OVF 19 // Indexes of DMA Overflow trigger
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#define TC0_EXT 0
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#define TC0_GCLK_ID 23
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#define TC0_MASTER 1
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#define TC0_OW_NUM 2
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#endif /* _SAML22_TC0_INSTANCE_ */
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