b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
116 lines
7.6 KiB
C
116 lines
7.6 KiB
C
/**
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* \file
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*
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* \brief Instance description for TCC0
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAML22_TCC0_INSTANCE_
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#define _SAML22_TCC0_INSTANCE_
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/* ========== Register definition for TCC0 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TCC0_CTRLA (0x42001C00) /**< \brief (TCC0) Control A */
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#define REG_TCC0_CTRLBCLR (0x42001C04) /**< \brief (TCC0) Control B Clear */
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#define REG_TCC0_CTRLBSET (0x42001C05) /**< \brief (TCC0) Control B Set */
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#define REG_TCC0_SYNCBUSY (0x42001C08) /**< \brief (TCC0) Synchronization Busy */
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#define REG_TCC0_FCTRLA (0x42001C0C) /**< \brief (TCC0) Recoverable Fault A Configuration */
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#define REG_TCC0_FCTRLB (0x42001C10) /**< \brief (TCC0) Recoverable Fault B Configuration */
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#define REG_TCC0_WEXCTRL (0x42001C14) /**< \brief (TCC0) Waveform Extension Configuration */
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#define REG_TCC0_DRVCTRL (0x42001C18) /**< \brief (TCC0) Driver Control */
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#define REG_TCC0_DBGCTRL (0x42001C1E) /**< \brief (TCC0) Debug Control */
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#define REG_TCC0_EVCTRL (0x42001C20) /**< \brief (TCC0) Event Control */
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#define REG_TCC0_INTENCLR (0x42001C24) /**< \brief (TCC0) Interrupt Enable Clear */
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#define REG_TCC0_INTENSET (0x42001C28) /**< \brief (TCC0) Interrupt Enable Set */
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#define REG_TCC0_INTFLAG (0x42001C2C) /**< \brief (TCC0) Interrupt Flag Status and Clear */
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#define REG_TCC0_STATUS (0x42001C30) /**< \brief (TCC0) Status */
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#define REG_TCC0_COUNT (0x42001C34) /**< \brief (TCC0) Count */
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#define REG_TCC0_PATT (0x42001C38) /**< \brief (TCC0) Pattern */
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#define REG_TCC0_WAVE (0x42001C3C) /**< \brief (TCC0) Waveform Control */
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#define REG_TCC0_PER (0x42001C40) /**< \brief (TCC0) Period */
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#define REG_TCC0_CC0 (0x42001C44) /**< \brief (TCC0) Compare and Capture 0 */
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#define REG_TCC0_CC1 (0x42001C48) /**< \brief (TCC0) Compare and Capture 1 */
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#define REG_TCC0_CC2 (0x42001C4C) /**< \brief (TCC0) Compare and Capture 2 */
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#define REG_TCC0_CC3 (0x42001C50) /**< \brief (TCC0) Compare and Capture 3 */
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#define REG_TCC0_PATTBUF (0x42001C64) /**< \brief (TCC0) Pattern Buffer */
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#define REG_TCC0_PERBUF (0x42001C6C) /**< \brief (TCC0) Period Buffer */
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#define REG_TCC0_CCBUF0 (0x42001C70) /**< \brief (TCC0) Compare and Capture Buffer 0 */
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#define REG_TCC0_CCBUF1 (0x42001C74) /**< \brief (TCC0) Compare and Capture Buffer 1 */
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#define REG_TCC0_CCBUF2 (0x42001C78) /**< \brief (TCC0) Compare and Capture Buffer 2 */
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#define REG_TCC0_CCBUF3 (0x42001C7C) /**< \brief (TCC0) Compare and Capture Buffer 3 */
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#else
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#define REG_TCC0_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (TCC0) Control A */
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#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42001C04UL) /**< \brief (TCC0) Control B Clear */
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#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42001C05UL) /**< \brief (TCC0) Control B Set */
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#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42001C08UL) /**< \brief (TCC0) Synchronization Busy */
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#define REG_TCC0_FCTRLA (*(RwReg *)0x42001C0CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */
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#define REG_TCC0_FCTRLB (*(RwReg *)0x42001C10UL) /**< \brief (TCC0) Recoverable Fault B Configuration */
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#define REG_TCC0_WEXCTRL (*(RwReg *)0x42001C14UL) /**< \brief (TCC0) Waveform Extension Configuration */
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#define REG_TCC0_DRVCTRL (*(RwReg *)0x42001C18UL) /**< \brief (TCC0) Driver Control */
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#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x42001C1EUL) /**< \brief (TCC0) Debug Control */
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#define REG_TCC0_EVCTRL (*(RwReg *)0x42001C20UL) /**< \brief (TCC0) Event Control */
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#define REG_TCC0_INTENCLR (*(RwReg *)0x42001C24UL) /**< \brief (TCC0) Interrupt Enable Clear */
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#define REG_TCC0_INTENSET (*(RwReg *)0x42001C28UL) /**< \brief (TCC0) Interrupt Enable Set */
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#define REG_TCC0_INTFLAG (*(RwReg *)0x42001C2CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */
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#define REG_TCC0_STATUS (*(RwReg *)0x42001C30UL) /**< \brief (TCC0) Status */
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#define REG_TCC0_COUNT (*(RwReg *)0x42001C34UL) /**< \brief (TCC0) Count */
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#define REG_TCC0_PATT (*(RwReg16*)0x42001C38UL) /**< \brief (TCC0) Pattern */
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#define REG_TCC0_WAVE (*(RwReg *)0x42001C3CUL) /**< \brief (TCC0) Waveform Control */
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#define REG_TCC0_PER (*(RwReg *)0x42001C40UL) /**< \brief (TCC0) Period */
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#define REG_TCC0_CC0 (*(RwReg *)0x42001C44UL) /**< \brief (TCC0) Compare and Capture 0 */
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#define REG_TCC0_CC1 (*(RwReg *)0x42001C48UL) /**< \brief (TCC0) Compare and Capture 1 */
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#define REG_TCC0_CC2 (*(RwReg *)0x42001C4CUL) /**< \brief (TCC0) Compare and Capture 2 */
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#define REG_TCC0_CC3 (*(RwReg *)0x42001C50UL) /**< \brief (TCC0) Compare and Capture 3 */
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#define REG_TCC0_PATTBUF (*(RwReg16*)0x42001C64UL) /**< \brief (TCC0) Pattern Buffer */
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#define REG_TCC0_PERBUF (*(RwReg *)0x42001C6CUL) /**< \brief (TCC0) Period Buffer */
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#define REG_TCC0_CCBUF0 (*(RwReg *)0x42001C70UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */
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#define REG_TCC0_CCBUF1 (*(RwReg *)0x42001C74UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */
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#define REG_TCC0_CCBUF2 (*(RwReg *)0x42001C78UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */
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#define REG_TCC0_CCBUF3 (*(RwReg *)0x42001C7CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for TCC0 peripheral ========== */
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#define TCC0_CC_NUM 4 // Number of Compare/Capture units
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#define TCC0_DITHERING 1 // Dithering feature implemented
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#define TCC0_DMAC_ID_MC_0 15
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#define TCC0_DMAC_ID_MC_1 16
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#define TCC0_DMAC_ID_MC_2 17
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#define TCC0_DMAC_ID_MC_3 18
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#define TCC0_DMAC_ID_MC_LSB 15
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#define TCC0_DMAC_ID_MC_MSB 18
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#define TCC0_DMAC_ID_MC_SIZE 4
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#define TCC0_DMAC_ID_OVF 14 // DMA overflow/underflow/retrigger trigger
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#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
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#define TCC0_EXT 31 // Coding of implemented extended features
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#define TCC0_GCLK_ID 22 // Index of Generic Clock
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#define TCC0_OTMX 1 // Output Matrix feature implemented
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#define TCC0_OW_NUM 8 // Number of Output Waveforms
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#define TCC0_PG 1 // Pattern Generation feature implemented
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#define TCC0_SIZE 24
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#define TCC0_SWAP 1 // DTI outputs swap feature implemented
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#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
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#endif /* _SAML22_TCC0_INSTANCE_ */
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