b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
1464 lines
43 KiB
C
1464 lines
43 KiB
C
/**
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* \file
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*
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* \brief SAM EIC
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*
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* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAML22_EIC_COMPONENT_
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#ifndef _HRI_EIC_L22_H_INCLUDED_
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#define _HRI_EIC_L22_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_EIC_CRITICAL_SECTIONS)
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#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define EIC_CRITICAL_SECTION_ENTER()
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#define EIC_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint16_t hri_eic_nmiflag_reg_t;
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typedef uint32_t hri_eic_asynch_reg_t;
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typedef uint32_t hri_eic_config_reg_t;
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typedef uint32_t hri_eic_evctrl_reg_t;
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typedef uint32_t hri_eic_intenset_reg_t;
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typedef uint32_t hri_eic_intflag_reg_t;
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typedef uint32_t hri_eic_syncbusy_reg_t;
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typedef uint8_t hri_eic_ctrla_reg_t;
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typedef uint8_t hri_eic_nmictrl_reg_t;
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static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg)
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{
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while (((Eic *)hw)->SYNCBUSY.reg & reg) {
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};
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}
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static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg)
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{
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return ((Eic *)hw)->SYNCBUSY.reg & reg;
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}
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static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw)
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{
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return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos;
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}
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static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw)
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{
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((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI;
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}
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static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
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{
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uint16_t tmp;
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tmp = ((Eic *)hw)->NMIFLAG.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw)
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{
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return ((Eic *)hw)->NMIFLAG.reg;
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}
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static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
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{
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((Eic *)hw)->NMIFLAG.reg = mask;
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}
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static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Eic *)hw)->INTFLAG.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw)
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{
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return ((Eic *)hw)->INTFLAG.reg;
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}
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static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
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{
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((Eic *)hw)->INTFLAG.reg = mask;
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}
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static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
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{
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((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask);
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}
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static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Eic *)hw)->INTENSET.reg;
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tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos;
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return tmp;
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}
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static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw)
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{
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uint32_t tmp;
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tmp = ((Eic *)hw)->INTENSET.reg;
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tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos;
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return tmp;
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}
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static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data)
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{
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((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data);
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((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data);
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}
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static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
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{
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((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask);
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}
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static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
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{
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((Eic *)hw)->INTENSET.reg = mask;
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}
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static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Eic *)hw)->INTENSET.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw)
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{
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return ((Eic *)hw)->INTENSET.reg;
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}
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static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data)
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{
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((Eic *)hw)->INTENSET.reg = data;
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((Eic *)hw)->INTENCLR.reg = ~data;
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}
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static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
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{
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((Eic *)hw)->INTENCLR.reg = mask;
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}
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static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw)
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{
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return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos;
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}
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static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw)
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{
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return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos;
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}
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static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Eic *)hw)->SYNCBUSY.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw)
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{
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return ((Eic *)hw)->SYNCBUSY.reg;
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}
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static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw)
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{
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uint8_t tmp;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
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tmp = ((Eic *)hw)->CTRLA.reg;
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tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos;
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return (bool)tmp;
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}
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static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw)
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{
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uint8_t tmp;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
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tmp = ((Eic *)hw)->CTRLA.reg;
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tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos;
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return (bool)tmp;
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}
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static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
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{
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uint8_t tmp;
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EIC_CRITICAL_SECTION_ENTER();
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tmp = ((Eic *)hw)->CTRLA.reg;
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tmp &= ~EIC_CTRLA_ENABLE;
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tmp |= value << EIC_CTRLA_ENABLE_Pos;
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((Eic *)hw)->CTRLA.reg = tmp;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw)
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{
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uint8_t tmp;
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tmp = ((Eic *)hw)->CTRLA.reg;
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tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos;
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return (bool)tmp;
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}
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static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value)
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{
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uint8_t tmp;
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EIC_CRITICAL_SECTION_ENTER();
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tmp = ((Eic *)hw)->CTRLA.reg;
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tmp &= ~EIC_CTRLA_CKSEL;
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tmp |= value << EIC_CTRLA_CKSEL_Pos;
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((Eic *)hw)->CTRLA.reg = tmp;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->CTRLA.reg |= mask;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
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{
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uint8_t tmp;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
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tmp = ((Eic *)hw)->CTRLA.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->CTRLA.reg = data;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->CTRLA.reg &= ~mask;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->CTRLA.reg ^= mask;
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw)
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{
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hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
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return ((Eic *)hw)->CTRLA.reg;
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}
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static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN;
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw)
|
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{
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uint8_t tmp;
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tmp = ((Eic *)hw)->NMICTRL.reg;
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tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos;
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return (bool)tmp;
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}
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static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value)
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{
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uint8_t tmp;
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EIC_CRITICAL_SECTION_ENTER();
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tmp = ((Eic *)hw)->NMICTRL.reg;
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tmp &= ~EIC_NMICTRL_NMIFILTEN;
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tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos;
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((Eic *)hw)->NMICTRL.reg = tmp;
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EIC_CRITICAL_SECTION_LEAVE();
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|
}
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static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw)
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|
{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN;
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN;
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EIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw)
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{
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EIC_CRITICAL_SECTION_ENTER();
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((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw)
|
|
{
|
|
uint8_t tmp;
|
|
tmp = ((Eic *)hw)->NMICTRL.reg;
|
|
tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value)
|
|
{
|
|
uint8_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->NMICTRL.reg;
|
|
tmp &= ~EIC_NMICTRL_NMIASYNCH;
|
|
tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos;
|
|
((Eic *)hw)->NMICTRL.reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
|
|
{
|
|
uint8_t tmp;
|
|
tmp = ((Eic *)hw)->NMICTRL.reg;
|
|
tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data)
|
|
{
|
|
uint8_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->NMICTRL.reg;
|
|
tmp &= ~EIC_NMICTRL_NMISENSE_Msk;
|
|
tmp |= EIC_NMICTRL_NMISENSE(data);
|
|
((Eic *)hw)->NMICTRL.reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw)
|
|
{
|
|
uint8_t tmp;
|
|
tmp = ((Eic *)hw)->NMICTRL.reg;
|
|
tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->NMICTRL.reg |= mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
|
|
{
|
|
uint8_t tmp;
|
|
tmp = ((Eic *)hw)->NMICTRL.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->NMICTRL.reg = data;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->NMICTRL.reg &= ~mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->NMICTRL.reg ^= mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw)
|
|
{
|
|
return ((Eic *)hw)->NMICTRL.reg;
|
|
}
|
|
|
|
static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->EVCTRL.reg;
|
|
tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->EVCTRL.reg;
|
|
tmp &= ~EIC_EVCTRL_EXTINTEO_Msk;
|
|
tmp |= EIC_EVCTRL_EXTINTEO(data);
|
|
((Eic *)hw)->EVCTRL.reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->EVCTRL.reg;
|
|
tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->EVCTRL.reg |= mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->EVCTRL.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->EVCTRL.reg = data;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->EVCTRL.reg &= ~mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->EVCTRL.reg ^= mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw)
|
|
{
|
|
return ((Eic *)hw)->EVCTRL.reg;
|
|
}
|
|
|
|
static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->ASYNCH.reg;
|
|
tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->ASYNCH.reg;
|
|
tmp &= ~EIC_ASYNCH_ASYNCH_Msk;
|
|
tmp |= EIC_ASYNCH_ASYNCH(data);
|
|
((Eic *)hw)->ASYNCH.reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->ASYNCH.reg;
|
|
tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->ASYNCH.reg |= mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->ASYNCH.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->ASYNCH.reg = data;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->ASYNCH.reg &= ~mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->ASYNCH.reg ^= mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw)
|
|
{
|
|
return ((Eic *)hw)->ASYNCH.reg;
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_FILTEN0;
|
|
tmp |= value << EIC_CONFIG_FILTEN0_Pos;
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_FILTEN1;
|
|
tmp |= value << EIC_CONFIG_FILTEN1_Pos;
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_FILTEN2;
|
|
tmp |= value << EIC_CONFIG_FILTEN2_Pos;
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_FILTEN3;
|
|
tmp |= value << EIC_CONFIG_FILTEN3_Pos;
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_FILTEN4;
|
|
tmp |= value << EIC_CONFIG_FILTEN4_Pos;
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_FILTEN5;
|
|
tmp |= value << EIC_CONFIG_FILTEN5_Pos;
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_FILTEN6;
|
|
tmp |= value << EIC_CONFIG_FILTEN6_Pos;
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_FILTEN7;
|
|
tmp |= value << EIC_CONFIG_FILTEN7_Pos;
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index,
|
|
hri_eic_config_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_SENSE0_Msk;
|
|
tmp |= EIC_CONFIG_SENSE0(data);
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index,
|
|
hri_eic_config_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_SENSE1_Msk;
|
|
tmp |= EIC_CONFIG_SENSE1(data);
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index,
|
|
hri_eic_config_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_SENSE2_Msk;
|
|
tmp |= EIC_CONFIG_SENSE2(data);
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index,
|
|
hri_eic_config_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_SENSE3_Msk;
|
|
tmp |= EIC_CONFIG_SENSE3(data);
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index,
|
|
hri_eic_config_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_SENSE4_Msk;
|
|
tmp |= EIC_CONFIG_SENSE4(data);
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index,
|
|
hri_eic_config_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_SENSE5_Msk;
|
|
tmp |= EIC_CONFIG_SENSE5(data);
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index,
|
|
hri_eic_config_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_SENSE6_Msk;
|
|
tmp |= EIC_CONFIG_SENSE6(data);
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index,
|
|
hri_eic_config_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= ~EIC_CONFIG_SENSE7_Msk;
|
|
tmp |= EIC_CONFIG_SENSE7(data);
|
|
((Eic *)hw)->CONFIG[index].reg = tmp;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask);
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg |= mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index,
|
|
hri_eic_config_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Eic *)hw)->CONFIG[index].reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg = data;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg &= ~mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
|
|
{
|
|
EIC_CRITICAL_SECTION_ENTER();
|
|
((Eic *)hw)->CONFIG[index].reg ^= mask;
|
|
EIC_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index)
|
|
{
|
|
return ((Eic *)hw)->CONFIG[index].reg;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _HRI_EIC_L22_H_INCLUDED */
|
|
#endif /* _SAML22_EIC_COMPONENT_ */
|