b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
173 lines
9.0 KiB
C
173 lines
9.0 KiB
C
/**
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* \file
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*
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* \brief Component description for TRNG
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAML22_TRNG_COMPONENT_
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#define _SAML22_TRNG_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR TRNG */
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/* ========================================================================== */
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/** \addtogroup SAML22_TRNG True Random Generator */
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/*@{*/
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#define TRNG_U2242
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#define REV_TRNG 0x101
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/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t :1; /*!< bit: 0 Reserved */
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uint8_t ENABLE:1; /*!< bit: 1 Enable */
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uint8_t :4; /*!< bit: 2.. 5 Reserved */
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uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
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uint8_t :1; /*!< bit: 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} TRNG_CTRLA_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_CTRLA_OFFSET 0x00 /**< \brief (TRNG_CTRLA offset) Control A */
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#define TRNG_CTRLA_RESETVALUE _U_(0x00) /**< \brief (TRNG_CTRLA reset_value) Control A */
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#define TRNG_CTRLA_ENABLE_Pos 1 /**< \brief (TRNG_CTRLA) Enable */
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#define TRNG_CTRLA_ENABLE (_U_(0x1) << TRNG_CTRLA_ENABLE_Pos)
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#define TRNG_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TRNG_CTRLA) Run in Standby */
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#define TRNG_CTRLA_RUNSTDBY (_U_(0x1) << TRNG_CTRLA_RUNSTDBY_Pos)
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#define TRNG_CTRLA_MASK _U_(0x42) /**< \brief (TRNG_CTRLA) MASK Register */
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/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t DATARDYEO:1; /*!< bit: 0 Data Ready Event Output */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} TRNG_EVCTRL_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_EVCTRL_OFFSET 0x04 /**< \brief (TRNG_EVCTRL offset) Event Control */
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#define TRNG_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (TRNG_EVCTRL reset_value) Event Control */
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#define TRNG_EVCTRL_DATARDYEO_Pos 0 /**< \brief (TRNG_EVCTRL) Data Ready Event Output */
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#define TRNG_EVCTRL_DATARDYEO (_U_(0x1) << TRNG_EVCTRL_DATARDYEO_Pos)
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#define TRNG_EVCTRL_MASK _U_(0x01) /**< \brief (TRNG_EVCTRL) MASK Register */
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/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} TRNG_INTENCLR_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_INTENCLR_OFFSET 0x08 /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */
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#define TRNG_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */
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#define TRNG_INTENCLR_DATARDY_Pos 0 /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */
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#define TRNG_INTENCLR_DATARDY (_U_(0x1) << TRNG_INTENCLR_DATARDY_Pos)
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#define TRNG_INTENCLR_MASK _U_(0x01) /**< \brief (TRNG_INTENCLR) MASK Register */
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/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} TRNG_INTENSET_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_INTENSET_OFFSET 0x09 /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */
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#define TRNG_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */
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#define TRNG_INTENSET_DATARDY_Pos 0 /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */
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#define TRNG_INTENSET_DATARDY (_U_(0x1) << TRNG_INTENSET_DATARDY_Pos)
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#define TRNG_INTENSET_MASK _U_(0x01) /**< \brief (TRNG_INTENSET) MASK Register */
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/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union { // __I to avoid read-modify-write on write-to-clear register
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struct {
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__I uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Flag */
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__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} TRNG_INTFLAG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_INTFLAG_OFFSET 0x0A /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */
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#define TRNG_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */
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#define TRNG_INTFLAG_DATARDY_Pos 0 /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */
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#define TRNG_INTFLAG_DATARDY (_U_(0x1) << TRNG_INTFLAG_DATARDY_Pos)
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#define TRNG_INTFLAG_MASK _U_(0x01) /**< \brief (TRNG_INTFLAG) MASK Register */
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/* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/ 32) Output Data -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t DATA:32; /*!< bit: 0..31 Output Data */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} TRNG_DATA_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define TRNG_DATA_OFFSET 0x20 /**< \brief (TRNG_DATA offset) Output Data */
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#define TRNG_DATA_RESETVALUE _U_(0x00000000) /**< \brief (TRNG_DATA reset_value) Output Data */
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#define TRNG_DATA_DATA_Pos 0 /**< \brief (TRNG_DATA) Output Data */
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#define TRNG_DATA_DATA_Msk (_U_(0xFFFFFFFF) << TRNG_DATA_DATA_Pos)
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#define TRNG_DATA_DATA(value) (TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos))
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#define TRNG_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (TRNG_DATA) MASK Register */
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/** \brief TRNG hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__IO TRNG_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
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RoReg8 Reserved1[0x3];
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__IO TRNG_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */
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RoReg8 Reserved2[0x3];
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__IO TRNG_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
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__IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
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__IO TRNG_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
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RoReg8 Reserved3[0x15];
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__I TRNG_DATA_Type DATA; /**< \brief Offset: 0x20 (R/ 32) Output Data */
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} Trng;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAML22_TRNG_COMPONENT_ */
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