b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
267 lines
6.7 KiB
C
267 lines
6.7 KiB
C
/* Auto-generated config file peripheral_clk_config.h */
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#ifndef PERIPHERAL_CLK_CONFIG_H
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#define PERIPHERAL_CLK_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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// <y> ADC Clock Source
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// <id> adc_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <i> Select the clock source for ADC.
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#ifndef CONF_GCLK_ADC_SRC
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#define CONF_GCLK_ADC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#endif
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/**
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* \def CONF_GCLK_ADC_FREQUENCY
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* \brief ADC's Clock frequency
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*/
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#ifndef CONF_GCLK_ADC_FREQUENCY
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#define CONF_GCLK_ADC_FREQUENCY 4000000
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#endif
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// <y> EIC Clock Source
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// <id> eic_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <i> Select the clock source for EIC.
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#ifndef CONF_GCLK_EIC_SRC
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#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#endif
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/**
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* \def CONF_GCLK_EIC_FREQUENCY
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* \brief EIC's Clock frequency
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*/
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#ifndef CONF_GCLK_EIC_FREQUENCY
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#define CONF_GCLK_EIC_FREQUENCY 32768
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#endif
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/**
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* \def CONF_CPU_FREQUENCY
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* \brief CPU's Clock frequency
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*/
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#ifndef CONF_CPU_FREQUENCY
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#define CONF_CPU_FREQUENCY 4000000
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#endif
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// <y> RTC Clock Source
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// <id> rtc_clk_selection
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// <RTC_CLOCK_SOURCE"> RTC source
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// <i> Select the clock source for RTC.
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#ifndef CONF_GCLK_RTC_SRC
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#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
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#endif
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/**
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* \def CONF_GCLK_RTC_FREQUENCY
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* \brief RTC's Clock frequency
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*/
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#ifndef CONF_GCLK_RTC_FREQUENCY
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#define CONF_GCLK_RTC_FREQUENCY 1024
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#endif
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// <y> Core Clock Source
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// <id> core_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <i> Select the clock source for CORE.
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#ifndef CONF_GCLK_SERCOM1_CORE_SRC
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#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#endif
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// <y> Slow Clock Source
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// <id> slow_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <i> Select the slow clock source.
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#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
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#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#endif
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/**
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* \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
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* \brief SERCOM1's Core Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
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#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 4000000
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#endif
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/**
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* \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
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* \brief SERCOM1's Slow Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
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#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
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#endif
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// <y> Core Clock Source
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// <id> core_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <i> Select the clock source for CORE.
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#ifndef CONF_GCLK_SERCOM3_CORE_SRC
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#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#endif
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// <y> Slow Clock Source
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// <id> slow_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <i> Select the slow clock source.
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#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
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#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#endif
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/**
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* \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
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* \brief SERCOM3's Core Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
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#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 4000000
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#endif
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/**
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* \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
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* \brief SERCOM3's Slow Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
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#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
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#endif
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// <y> TC Clock Source
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// <id> tc_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <i> Select the clock source for TC.
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#ifndef CONF_GCLK_TC3_SRC
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#define CONF_GCLK_TC3_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#endif
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/**
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* \def CONF_GCLK_TC3_FREQUENCY
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* \brief TC3's Clock frequency
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*/
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#ifndef CONF_GCLK_TC3_FREQUENCY
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#define CONF_GCLK_TC3_FREQUENCY 32768
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#endif
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// <y> TCC Clock Source
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// <id> tcc_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <i> Select the clock source for TCC.
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#ifndef CONF_GCLK_TCC0_SRC
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#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#endif
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/**
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* \def CONF_GCLK_TCC0_FREQUENCY
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* \brief TCC0's Clock frequency
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*/
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#ifndef CONF_GCLK_TCC0_FREQUENCY
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#define CONF_GCLK_TCC0_FREQUENCY 16000000
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#endif
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#include <hpl_osc32kctrl_config.h>
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// <y> SLCD Clock Source
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// <id> slcd_clk_selection
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// <SLCD_CLOCK_SOURCE"> SLCD source
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// <i> Select the clock source for SLCD.
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#ifndef CONF_GCLK_SLCD_SRC
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#define CONF_GCLK_SLCD_SRC SLCD_CLOCK_SOURCE
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#endif
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/**
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* \def CONF_GCLK_SLCD_FREQUENCY
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* \brief SLCD's Clock frequency
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*/
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#ifndef CONF_GCLK_SLCD_FREQUENCY
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#define CONF_GCLK_SLCD_FREQUENCY 32768
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#endif
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#ifndef SLCD_FRAME_FREQUENCY
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#define SLCD_FRAME_FREQUENCY \
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(CONF_GCLK_SLCD_FREQUENCY \
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/ (((CONF_SLCD_PRESC + 1) * 16) * (CONF_SLCD_CKDIV + 1) \
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* ((CONF_SLCD_COM_NUM == 4) ? 6 : ((CONF_SLCD_COM_NUM == 5) ? 8 : (CONF_SLCD_COM_NUM + 1)))))
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#endif
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// <<< end of configuration section >>>
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#endif // PERIPHERAL_CLK_CONFIG_H
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