484 lines
12 KiB
C
484 lines
12 KiB
C
/* Auto-generated config file hpl_oscctrl_config.h */
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#ifndef HPL_OSCCTRL_CONFIG_H
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#define HPL_OSCCTRL_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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// <e> External Multipurpose Crystal Oscillator Configuration
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// <i> Indicates whether configuration for XOSC is enabled or not
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// <id> enable_xosc
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#ifndef CONF_XOSC_CONFIG
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#define CONF_XOSC_CONFIG 0
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#endif
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// <o> Frequency <400000-32000000>
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// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
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// <id> xosc_frequency
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#ifndef CONF_XOSC_FREQUENCY
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#define CONF_XOSC_FREQUENCY 400000
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#endif
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// <h> External Multipurpose Crystal Oscillator Control
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// <q> Oscillator enable
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// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
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// <id> xosc_arch_enable
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#ifndef CONF_XOSC_ENABLE
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#define CONF_XOSC_ENABLE 0
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#endif
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// <o> Start-Up Time
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// <0x0=>31us
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// <0x1=>61us
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// <0x2=>122us
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// <0x3=>244us
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// <0x4=>488us
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// <0x5=>977us
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// <0x6=>1953us
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// <0x7=>3906us
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// <0x8=>7813us
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// <0x9=>15625us
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// <0xA=>31250us
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// <0xB=>62500us
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// <0xC=>125000us
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// <0xD=>250000us
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// <0xE=>500000us
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// <0xF=>1000000us
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// <id> xosc_arch_startup
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#ifndef CONF_XOSC_STARTUP
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#define CONF_XOSC_STARTUP 0x0
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#endif
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// <q> Automatic Amplitude Gain Control
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// <i> Indicates whether Automatic Amplitude Gain Control is enabled or not
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// <id> xosc_arch_ampgc
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#ifndef CONF_XOSC_AMPGC
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#define CONF_XOSC_AMPGC 0
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#endif
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// <o> External Multipurpose Crystal Oscillator Gain
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// <0x0=>2MHz
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// <0x1=>4MHz
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// <0x2=>8MHz
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// <0x3=>16MHz
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// <0x4=>30MHz
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// <id> xosc_arch_gain
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#ifndef CONF_XOSC_GAIN
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#define CONF_XOSC_GAIN 0x0
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#endif
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// <q> On Demand Control
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// <i> Indicates whether On Demand Control is enabled or not
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// <id> xosc_arch_ondemand
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#ifndef CONF_XOSC_ONDEMAND
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#define CONF_XOSC_ONDEMAND 1
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#endif
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> xosc_arch_runstdby
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#ifndef CONF_XOSC_RUNSTDBY
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#define CONF_XOSC_RUNSTDBY 0
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#endif
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// <q> Clock Switch Back
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// <i> Indicates whether Clock Switch Back is enabled or not
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// <id> xosc_arch_swben
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#ifndef CONF_XOSC_SWBEN
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#define CONF_XOSC_SWBEN 0
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#endif
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// <q> Clock Failure Detector
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// <i> Indicates whether Clock Failure Detector is enabled or not
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// <id> xosc_arch_cfden
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#ifndef CONF_XOSC_CFDEN
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#define CONF_XOSC_CFDEN 0
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#endif
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// <q> Clock Failure Detector Event Out
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// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
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// <id> xosc_arch_cfdeo
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#ifndef CONF_XOSC_CFDEO
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#define CONF_XOSC_CFDEO 0
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#endif
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// <q> Crystal connected to XIN/XOUT Enable
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// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
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// <id> xosc_arch_xtalen
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#ifndef CONF_XOSC_XTALEN
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#define CONF_XOSC_XTALEN 0
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#endif
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//</h>
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//</e>
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// <e> 16MHz Internal Oscillator Configuration
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// <i> Indicates whether configuration for OSC8M is enabled or not
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// <id> enable_osc16m
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#ifndef CONF_OSC16M_CONFIG
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#define CONF_OSC16M_CONFIG 1
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#endif
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// <h> 16MHz Internal Oscillator Control
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// <q> Enable
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// <i> Indicates whether 16MHz Internal Oscillator is enabled or not
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// <id> osc16m_arch_enable
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#ifndef CONF_OSC16M_ENABLE
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#define CONF_OSC16M_ENABLE 1
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#endif
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// <q> On Demand Control
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// <i> Indicates whether On Demand Control is enabled or not
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// <id> osc16m_arch_ondemand
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#ifndef CONF_OSC16M_ONDEMAND
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#define CONF_OSC16M_ONDEMAND 1
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#endif
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> osc16m_arch_runstdby
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#ifndef CONF_OSC16M_RUNSTDBY
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#define CONF_OSC16M_RUNSTDBY 0
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#endif
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// <y> Oscillator Frequency Selection(Mhz)
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// <OSCCTRL_OSC16MCTRL_FSEL_4_Val"> 4
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// <OSCCTRL_OSC16MCTRL_FSEL_8_Val"> 8
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// <OSCCTRL_OSC16MCTRL_FSEL_12_Val"> 12
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// <OSCCTRL_OSC16MCTRL_FSEL_16_Val"> 16
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// <i> This defines the oscillator frequency (Mhz)
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// <id> osc16m_freq
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#ifndef CONF_OSC16M_FSEL
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#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val
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#endif
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// <q> Oscillator Calibration Control
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// <i> Indicates whether Oscillator Calibration is enabled or not
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// <id> osc16m_arch_calib_enable
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#ifndef CONF_OSC16M_CALIB_ENABLE
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#define CONF_OSC16M_CALIB_ENABLE 0
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#endif
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// <o> 4MHz Frequency Calibration <0x0-0x3F>
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// <id> osc16m_arch_4m_fcal
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#ifndef CONF_OSC16M_FCAL
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#define CONF_OSC16M_4M_FCAL 0
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#endif
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// <o> 4MHz Temperature Calibration <0x0-0x3F>
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// <id> osc16m_arch_4m_tcal
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#ifndef CONF_OSC16M_TCAL
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#define CONF_OSC16M_4M_TCAL 0
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#endif
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// <o> 8MHz Frequency Calibration <0x0-0x3F>
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// <id> osc16m_arch_8m_fcal
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#ifndef CONF_OSC16M_FCAL
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#define CONF_OSC16M_8M_FCAL 0
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#endif
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// <o> 8MHz Temperature Calibration <0x0-0x3F>
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// <id> osc16m_arch_8m_tcal
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#ifndef CONF_OSC16M_TCAL
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#define CONF_OSC16M_8M_TCAL 0
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#endif
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// <o> 12MHz Frequency Calibration <0x0-0x3F>
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// <id> osc16m_arch_12m_fcal
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#ifndef CONF_OSC16M_FCAL
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#define CONF_OSC16M_12M_FCAL 0
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#endif
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// <o> 12MHz Temperature Calibration <0x0-0x3F>
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// <id> osc16m_arch_12m_tcal
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#ifndef CONF_OSC16M_TCAL
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#define CONF_OSC16M_12M_TCAL 0
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#endif
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// <o> 16MHz Frequency Calibration <0x0-0x3F>
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// <id> osc16m_arch_fcal
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#ifndef CONF_OSC16M_FCAL
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#define CONF_OSC16M_16M_FCAL 0
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#endif
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// <o> 16MHz Temperature Calibration <0x0-0x3F>
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// <id> osc16m_arch_16m_tcal
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#ifndef CONF_OSC16M_TCAL
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#define CONF_OSC16M_16M_TCAL 0
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#endif
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//</h>
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//</e>
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// <e> DFLL Configuration
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// <i> Indicates whether configuration for DFLL is enabled or not
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// <id> enable_dfll48m
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#ifndef CONF_DFLL_CONFIG
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#define CONF_DFLL_CONFIG 0
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#endif
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// <y> Reference Clock Source
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source.
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// <id> dfll48m_ref_clock
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#ifndef CONF_DFLL_GCLK
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#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
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#endif
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// <h> Digital Frequency Locked Loop Control
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// <q> DFLL Enable
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// <i> Indicates whether DFLL is enabled or not
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// <id> dfll48m_arch_enable
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#ifndef CONF_DFLL_ENABLE
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#define CONF_DFLL_ENABLE 0
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#endif
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// <q> Wait Lock
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// <i> Indicates whether Wait Lock is enabled or not
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// <id> dfll_arch_waitlock
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#ifndef CONF_DFLL_WAITLOCK
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#define CONF_DFLL_WAITLOCK 0
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#endif
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// <q> Bypass Coarse Lock
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// <i> Indicates whether Bypass Coarse Lock is enabled or not
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// <id> dfll_arch_bplckc
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#ifndef CONF_DFLL_BPLCKC
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#define CONF_DFLL_BPLCKC 0
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#endif
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// <q> Quick Lock Disable
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// <i> Indicates whether Quick Lock Disable is enabled or not
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// <id> dfll_arch_qldis
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#ifndef CONF_DFLL_QLDIS
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#define CONF_DFLL_QLDIS 0
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#endif
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// <q> Chill Cycle Disable
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// <i> Indicates whether Chill Cycle Disable is enabled or not
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// <id> dfll_arch_ccdis
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#ifndef CONF_DFLL_CCDIS
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#define CONF_DFLL_CCDIS 0
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#endif
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// <q> On Demand Control
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// <i> Indicates whether On Demand Control is enabled or not
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// <id> dfll_arch_ondemand
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#ifndef CONF_DFLL_ONDEMAND
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#define CONF_DFLL_ONDEMAND 1
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#endif
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> dfll_arch_runstdby
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#ifndef CONF_DFLL_RUNSTDBY
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#define CONF_DFLL_RUNSTDBY 0
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#endif
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// <q> USB Clock Recovery Mode
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// <i> Indicates whether USB Clock Recovery Mode is enabled or not
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// <id> dfll_arch_usbcrm
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#ifndef CONF_DFLL_USBCRM
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#define CONF_DFLL_USBCRM 0
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#endif
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// <q> Lose Lock After Wake
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// <i> Indicates whether Lose Lock After Wake is enabled or not
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// <id> dfll_arch_llaw
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#ifndef CONF_DFLL_LLAW
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#define CONF_DFLL_LLAW 0
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#endif
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// <q> Stable DFLL Frequency
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// <i> Indicates whether Stable DFLL Frequency is enabled or not
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// <id> dfll_arch_stable
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#ifndef CONF_DFLL_STABLE
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#define CONF_DFLL_STABLE 0
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#endif
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// <o> Operating Mode Selection
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// <0=>Open Loop Mode
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// <1=>Closed Loop Mode
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// <id> dfll48m_mode
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#ifndef CONF_DFLL_MODE
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#define CONF_DFLL_MODE 0
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#endif
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// <o> Coarse Maximum Step <0x0-0x1F>
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// <id> dfll_arch_cstep
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#ifndef CONF_DFLL_CSTEP
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#define CONF_DFLL_CSTEP 1
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#endif
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// <o> Fine Maximum Step <0x0-0x3FF>
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// <id> dfll_arch_fstep
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#ifndef CONF_DFLL_FSTEP
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#define CONF_DFLL_FSTEP 1
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#endif
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// <o> DFLL Multiply Factor <0x0-0xFFFF>
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// <id> dfll48m_mul
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#ifndef CONF_DFLL_MUL
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#define CONF_DFLL_MUL 0
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#endif
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// <e> DFLL Calibration Overwrite
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// <i> Indicates whether Overwrite Calibration value of DFLL
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// <id> dfll_arch_calibration
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#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
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#define CONF_DFLL_OVERWRITE_CALIBRATION 0
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#endif
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// <o> Coarse Value <0x0-0x3F>
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// <id> dfll_arch_coarse
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#ifndef CONF_DFLL_COARSE
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#define CONF_DFLL_COARSE (0x1f / 4)
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#endif
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// <o> Fine Value <0x0-0x3FF>
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// <id> dfll_arch_fine
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#ifndef CONF_DFLL_FINE
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#define CONF_DFLL_FINE (0x200)
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#endif
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//</e>
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//</h>
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//</e>
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// <e> DPLL Configuration
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// <i> Indicates whether configuration for DPLL is enabled or not
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// <id> enable_fdpll96m
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#ifndef CONF_DPLL_CONFIG
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#define CONF_DPLL_CONFIG 0
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#endif
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// <y> Reference Clock Source
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// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
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// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source.
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// <id> fdpll96m_ref_clock
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#ifndef CONF_DPLL_GCLK
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#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K
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#endif
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// <h> Digital Phase Locked Loop Control
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// <q> Enable
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// <i> Indicates whether Digital Phase Locked Loop is enabled or not
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// <id> fdpll96m_arch_enable
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#ifndef CONF_DPLL_ENABLE
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#define CONF_DPLL_ENABLE 0
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#endif
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// <q> On Demand Control
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// <i> Indicates whether On Demand Control is enabled or not
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// <id> fdpll96m_arch_ondemand
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#ifndef CONF_DPLL_ONDEMAND
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#define CONF_DPLL_ONDEMAND 1
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#endif
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> fdpll96m_arch_runstdby
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#ifndef CONF_DPLL_RUNSTDBY
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#define CONF_DPLL_RUNSTDBY 0
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#endif
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// <o> Loop Divider Ratio Fractional Part <0x0-0xF>
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// <id> fdpll96m_ldrfrac
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#ifndef CONF_DPLL_LDRFRAC
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#define CONF_DPLL_LDRFRAC 0xd
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#endif
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// <o> Loop Divider Ratio Integer Part <0x0-0xFFF>
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// <id> fdpll96m_ldr
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#ifndef CONF_DPLL_LDR
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#define CONF_DPLL_LDR 0x5b7
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#endif
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// <o> Clock Divider <0x0-0x3FF>
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// <id> fdpll96m_clock_div
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#ifndef CONF_DPLL_DIV
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#define CONF_DPLL_DIV 0
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#endif
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// <q> Lock Bypass
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// <i> Indicates whether Lock Bypass is enabled or not
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// <id> fdpll96m_arch_lbypass
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#ifndef CONF_DPLL_LBYPASS
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#define CONF_DPLL_LBYPASS 0
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#endif
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// <o> Lock Time
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// <0=>No time-out, automatic lock
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// <4=>The Time-out if no lock within 8 ms
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// <5=>The Time-out if no lock within 9 ms
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// <6=>The Time-out if no lock within 10 ms
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// <7=>The Time-out if no lock within 11 ms
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// <id> fdpll96m_arch_ltime
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#ifndef CONF_DPLL_LTIME
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#define CONF_DPLL_LTIME 0
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#endif
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// <o> Reference Clock Selection
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// <0=>XOSC32K clock reference
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// <1=>XOSC clock reference
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// <2=>GCLK clock reference
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// <id> fdpll96m_arch_refclk
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#ifndef CONF_DPLL_REFCLK
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#define CONF_DPLL_REFCLK 0
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#endif
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// <q> Wake Up Fast
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// <i> Indicates whether Wake Up Fast is enabled or not
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// <id> fdpll96m_arch_wuf
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#ifndef CONF_DPLL_WUF
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#define CONF_DPLL_WUF 0
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#endif
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// <q> Low-Power Enable
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// <i> Indicates whether Low-Power Enable is enabled or not
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// <id> fdpll96m_arch_lpen
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#ifndef CONF_DPLL_LPEN
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#define CONF_DPLL_LPEN 0
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#endif
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// <o> Reference Clock Selection
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// <0=>Default filter mode
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// <1=>Low bandwidth filter
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// <2=>High bandwidth filter
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// <3=>High damping filter
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// <id> fdpll96m_arch_filter
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#ifndef CONF_DPLL_FILTER
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#define CONF_DPLL_FILTER 0
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#endif
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// <y> Output Clock Prescaler
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// <OSCCTRL_DPLLPRESC_PRESC_DIV1_Val"> 1
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// <OSCCTRL_DPLLPRESC_PRESC_DIV2_Val"> 2
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// <OSCCTRL_DPLLPRESC_PRESC_DIV4_Val"> 4
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// <id> fdpll96m_presc
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#ifndef CONF_DPLL_PRESC
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#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val
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#endif
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//</h>
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//</e>
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// <<< end of configuration section >>>
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#endif // HPL_OSCCTRL_CONFIG_H
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