548 lines
19 KiB
C
548 lines
19 KiB
C
/* Auto-generated config file hpl_tcc_config.h */
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#ifndef HPL_TCC_CONFIG_H
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#define HPL_TCC_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include <peripheral_clk_config.h>
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#ifndef CONF_TCC0_ENABLE
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#define CONF_TCC0_ENABLE 1
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#endif
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#ifndef CONF_TCC0_PWM_ENABLE
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#define CONF_TCC0_PWM_ENABLE 1
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#endif
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// <h> Basic settings
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// <y> TCC0 Prescaler
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// <TCC_CTRLA_PRESCALER_DIV1_Val"> No division
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// <TCC_CTRLA_PRESCALER_DIV2_Val"> Divide by 2
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// <TCC_CTRLA_PRESCALER_DIV4_Val"> Divide by 4
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// <TCC_CTRLA_PRESCALER_DIV8_Val"> Divide by 8
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// <TCC_CTRLA_PRESCALER_DIV16_Val"> Divide by 16
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// <TCC_CTRLA_PRESCALER_DIV64_Val"> Divide by 64
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// <TCC_CTRLA_PRESCALER_DIV256_Val"> Divide by 256
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// <TCC_CTRLA_PRESCALER_DIV1024_Val"> Divide by 1024
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// <i> This defines the TCC0 prescaler value
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// <id> tcc_prescaler
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#ifndef CONF_TCC0_PRESCALER
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#define CONF_TCC0_PRESCALER TCC_CTRLA_PRESCALER_DIV8_Val
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#endif
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// <hidden>
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//<o> TCC0 Period Value <0x000000-0xFFFFFF>
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// <id> tcc_per
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#ifndef CONF_TCC0_PER
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#define CONF_TCC0_PER 0x2710
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#endif
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// </hidden>
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// </h>
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// <h> PWM Waveform Output settings
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// <o> TCC0 Waveform Period Value (uS) <0x00-0xFFFFFFFF>
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// <i> The unit of this value is us.
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// <id> tcc_arch_wave_per_val
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#ifndef CONF_TCC0_WAVE_PER_VAL
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#define CONF_TCC0_WAVE_PER_VAL 0x3e8
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#endif
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// <o> TCC0 Waveform Duty Value (0.1%) <0x00-0x03E8>
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// <i> The unit of this value is 1/1000.
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// <id> tcc_arch_wave_duty_val
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#ifndef CONF_TCC0_WAVE_DUTY_VAL
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#define CONF_TCC0_WAVE_DUTY_VAL 0x1f4
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#endif
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// <o> TCC0 Waveform Channel Select <0x00-0x03>
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// <i> Index of the Compare Channel register, into which the Waveform Duty Value is written.
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// <i> Give index of the Compare Channel register here in 0x00-0x03 range.
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// <id> tcc_arch_sel_ch
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#ifndef CONF_TCC0_SEL_CH
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#define CONF_TCC0_SEL_CH 0x1
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#endif
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/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
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#if CONF_TCC0_PRESCALER < TCC_CTRLA_PRESCALER_DIV64_Val
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#define CONF_TCC0_PER_REG \
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((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1000000 / (1 << CONF_TCC0_PRESCALER) - 1))
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#define CONF_TCC0_CCX_REG ((uint32_t)(((double)(double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
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#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV64_Val
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#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 64000000 - 1))
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#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
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#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV256_Val
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#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 256000000 - 1))
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#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
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#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV1024_Val
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#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1024000000 - 1))
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#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
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#endif
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// </h>
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// <h> Advanced settings
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/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL A register.
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* May be used by other abstractions based on TC. */
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//#define CONF_TCC0_RESOLUTION TCC_CTRLA_RESOLUTION_NONE_Val
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// <q> Run in standby
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// <i> Indicates whether the TCC0 will continue running in standby sleep mode or not
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// <id> tcc_arch_runstdby
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#ifndef CONF_TCC0_RUNSTDBY
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#define CONF_TCC0_RUNSTDBY 0
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#endif
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// <y> TCC0 Prescaler and Counter Synchronization Selection
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// <TCC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
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// <TCC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
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// <TCC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
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// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock.
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// <id> tcc_arch_prescsync
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#ifndef CONF_TCC0_PRESCSYNC
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#define CONF_TCC0_PRESCSYNC TCC_CTRLA_PRESCSYNC_GCLK_Val
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#endif
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// <y> TCC0 Waveform Generation Selection
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// <TCC_WAVE_WAVEGEN_NPWM_Val"> Single-slope PWM
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// <TCC_WAVE_WAVEGEN_DSCRITICAL_Val"> Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
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// <TCC_WAVE_WAVEGEN_DSBOTTOM_Val"> Dual-slope, interrupt/event at ZERO (DSBOTTOM)
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// <TCC_WAVE_WAVEGEN_DSBOTH_Val"> Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
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// <TCC_WAVE_WAVEGEN_DSTOP_Val"> Dual-slope, interrupt/event at Top (DSTOP)
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// <id> tcc_arch_wavegen
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#ifndef CONF_TCC0_WAVEGEN
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#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_NPWM_Val
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#endif
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// <q> TCC0 Auto Lock
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// <i> Indicates whether the TCC0 Auto Lock is enabled or not
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// <id> tcc_arch_alock
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#ifndef CONF_TCC0_ALOCK
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#define CONF_TCC0_ALOCK 0
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#endif
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// <q> TCC0 Capture Channel 0 Enable
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// <i> Indicates whether the TCC0 Capture Channel 0 is enabled or not
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// <id> tcc_arch_cpten0
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#ifndef CONF_TCC0_CPTEN0
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#define CONF_TCC0_CPTEN0 0
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#endif
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// <q> TCC0 Capture Channel 1 Enable
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// <i> Indicates whether the TCC0 Capture Channel 1 is enabled or not
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// <id> tcc_arch_cpten1
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#ifndef CONF_TCC0_CPTEN1
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#define CONF_TCC0_CPTEN1 0
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#endif
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// <q> TCC0 Capture Channel 2 Enable
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// <i> Indicates whether the TCC0 Capture Channel 2 is enabled or not
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// <id> tcc_arch_cpten2
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#ifndef CONF_TCC0_CPTEN2
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#define CONF_TCC0_CPTEN2 0
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#endif
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// <q> TCC0 Capture Channel 3 Enable
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// <i> Indicates whether the TCC0 Capture Channel 3 is enabled or not
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// <id> tcc_arch_cpten3
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#ifndef CONF_TCC0_CPTEN3
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#define CONF_TCC0_CPTEN3 0
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#endif
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// <hidden>
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// <q> TCC0 Capture Channel 4 Enable
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// <i> Indicates whether the TCC0 Capture Channel 4 is enabled or not
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// <id> tcc_arch_cpten4
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#ifndef CONF_TCC0_CPTEN4
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#define CONF_TCC0_CPTEN4 0
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#endif
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// </hidden>
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// <hidden>
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// <q> TCC0 Capture Channel 5 Enable
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// <i> Indicates whether the TCC0 Capture Channel 5 is enabled or not
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// <id> tcc_arch_cpten5
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#ifndef CONF_TCC0_CPTEN5
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#define CONF_TCC0_CPTEN5 0
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#endif
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// </hidden>
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// <hidden>
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// <q> TCC0 Capture Channel 6 Enable
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// <i> Indicates whether the TCC0 Capture Channel 6 is enabled or not
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// <id> tcc_arch_cpten6
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#ifndef CONF_TCC0_CPTEN6
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#define CONF_TCC0_CPTEN6 0
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#endif
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// </hidden>
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// <hidden>
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// <q> TCC0 Capture Channel 7 Enable
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// <i> Indicates whether the TCC0 Capture Channel 7 is enabled or not
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// <id> tcc_arch_cpten7
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#ifndef CONF_TCC0_CPTEN7
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#define CONF_TCC0_CPTEN7 0
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#endif
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// </hidden>
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// <q> TCC0 Lock update
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// <i> Indicates whether the TCC0 Lock update is enabled or not
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// <id> tcc_arch_lupd
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#ifndef CONF_TCC0_LUPD
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#define CONF_TCC0_LUPD 1
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#endif
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/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register.
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* May be used by other abstractions based on TC. */
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//#define CONF_TCC0_DIR 0
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//#define CONF_TCC0_ONESHOT 0
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/* Commented intentionally. No fault control for timers. */
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/*#define CONF_TCC0_FAULT_A_SRC TCC_FCTRLA_SRC_DISABLE_Val
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#define CONF_TCC0_FAULT_A_KEEP 0
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#define CONF_TCC0_FAULT_A_QUAL 0
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#define CONF_TCC0_FAULT_A_BLANK TCC_FCTRLA_BLANK_DISABLE_Val
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#define CONF_TCC0_FAULT_A_RESTART 0
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#define CONF_TCC0_FAULT_A_HALT TCC_FCTRLA_HALT_DISABLE_Val
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#define CONF_TCC0_FAULT_A_CHSEL TCC_FCTRLA_CHSEL_CC0_Val
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#define CONF_TCC0_FAULT_A_CAPTURE TCC_FCTRLA_CAPTURE_DISABLE_Val
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#define CONF_TCC0_FAULT_A_BLACNKPRESC 0
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#define CONF_TCC0_FAULT_A_BLANKVAL 0
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#define CONF_TCC0_FAULT_A_FILTERVAL 0
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#define CONF_TCC0_FAULT_B_SRC TCC_FCTRLB_SRC_DISABLE_Val
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#define CONF_TCC0_FAULT_B_KEEP 0
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#define CONF_TCC0_FAULT_B_QUAL 0
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#define CONF_TCC0_FAULT_B_BLANK TCC_FCTRLB_BLANK_DISABLE_Val
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#define CONF_TCC0_FAULT_B_RESTART 0
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#define CONF_TCC0_FAULT_B_HALT TCC_FCTRLB_HALT_DISABLE_Val
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#define CONF_TCC0_FAULT_B_CHSEL TCC_FCTRLB_CHSEL_CC0_Val
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#define CONF_TCC0_FAULT_B_CAPTURE TCC_FCTRLB_CAPTURE_DISABLE_Val
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#define CONF_TCC0_FAULT_B_BLACNKPRESC 0
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#define CONF_TCC0_FAULT_B_BLANKVAL 0
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#define CONF_TCC0_FAULT_B_FILTERVAL 0*/
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/* Commented intentionally. No dead-time control for timers. */
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/*#define CONF_TCC0_OTMX 0
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#define CONF_TCC0_DTIEN0 0
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#define CONF_TCC0_DTIEN1 0
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#define CONF_TCC0_DTIEN2 0
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#define CONF_TCC0_DTIEN3 0
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#define CONF_TCC0_DTHS 0*/
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/* Commented intentionally. No driver control for timers. */
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/*#define CONF_TCC0_NRE0 0
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#define CONF_TCC0_NRE1 0
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#define CONF_TCC0_NRE2 0
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#define CONF_TCC0_NRE3 0
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#define CONF_TCC0_NRE4 0
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#define CONF_TCC0_NRE5 0
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#define CONF_TCC0_NRE6 0
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#define CONF_TCC0_NRE7 0
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#define CONF_TCC0_NVR0 0
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#define CONF_TCC0_NVR1 0
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#define CONF_TCC0_NVR2 0
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#define CONF_TCC0_NVR3 0
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#define CONF_TCC0_NVR4 0
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#define CONF_TCC0_NVR5 0
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#define CONF_TCC0_NVR6 0
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#define CONF_TCC0_NVR7 0
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#define CONF_TCC0_INVEN0 0
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#define CONF_TCC0_INVEN1 0
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#define CONF_TCC0_INVEN2 0
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#define CONF_TCC0_INVEN3 0
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#define CONF_TCC0_INVEN4 0
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#define CONF_TCC0_INVEN5 0
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#define CONF_TCC0_INVEN6 0
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#define CONF_TCC0_INVEN7 0
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#define CONF_TCC0_FILTERVAL0 0
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#define CONF_TCC0_FILTERVAL1 0*/
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// <q> TCC0 Debug Running Mode
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// <i> Indicates whether the TCC0 Debug Running Mode is enabled or not
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// <id> tcc_arch_dbgrun
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#ifndef CONF_TCC0_DBGRUN
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#define CONF_TCC0_DBGRUN 0
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#endif
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/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of Debug Control register.
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* May be used by other abstractions based on TC. */
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//#define CONF_TCC0_FDDBD 0
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// <e> Event control
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// <id> timer_event_control
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#ifndef CONF_TCC0_EVENT_CONTROL_ENABLE
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#define CONF_TCC0_EVENT_CONTROL_ENABLE 0
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#endif
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// <q> Match or Capture Channel 0 Event Output
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// <i> This bit indicates whether match/capture event on channel 0 is enabled and will be generated
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// <id> tcc_arch_mceo0
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#ifndef CONF_TCC0_MCEO0
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#define CONF_TCC0_MCEO0 0
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#endif
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// <q> Match or Capture Channel 0 Event Input
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// <i> This bit indicates whether match/capture 0 incoming event is enabled
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// <id> tcc_arch_mcei0
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#ifndef CONF_TCC0_MCEI0
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#define CONF_TCC0_MCEI0 0
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#endif
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// <q> Match or Capture Channel 1 Event Output
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// <i> This bit indicates whether match/capture event on channel 1 is enabled and will be generated
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// <id> tcc_arch_mceo1
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#ifndef CONF_TCC0_MCEO1
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#define CONF_TCC0_MCEO1 0
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#endif
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// <q> Match or Capture Channel 1 Event Input
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// <i> This bit indicates whether match/capture 1 incoming event is enabled
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// <id> tcc_arch_mcei1
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#ifndef CONF_TCC0_MCEI1
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#define CONF_TCC0_MCEI1 0
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#endif
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// <q> Match or Capture Channel 2 Event Output
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// <i> This bit indicates whether match/capture event on channel 2 is enabled and will be generated
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// <id> tcc_arch_mceo2
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#ifndef CONF_TCC0_MCEO2
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#define CONF_TCC0_MCEO2 0
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#endif
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// <q> Match or Capture Channel 2 Event Input
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// <i> This bit indicates whether match/capture 2 incoming event is enabled
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// <id> tcc_arch_mcei2
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#ifndef CONF_TCC0_MCEI2
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#define CONF_TCC0_MCEI2 0
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#endif
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// <q> Match or Capture Channel 3 Event Output
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// <i> This bit indicates whether match/capture event on channel 3 is enabled and will be generated
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// <id> tcc_arch_mceo3
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#ifndef CONF_TCC0_MCEO3
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#define CONF_TCC0_MCEO3 0
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#endif
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// <q> Match or Capture Channel 3 Event Input
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// <i> This bit indicates whether match/capture 3 incoming event is enabled
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// <id> tcc_arch_mcei3
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#ifndef CONF_TCC0_MCEI3
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#define CONF_TCC0_MCEI3 0
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#endif
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// <q> Timer/Counter Event Input 0
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// <i> This bit is used to enable input event 0 to the TCC
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// <id> tcc_arch_tcei0
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#ifndef CONF_TCC0_TCEI0
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#define CONF_TCC0_TCEI0 0
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#endif
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// <q> Timer/Counter Event Input 0 Invert
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// <i> This bit inverts the event 0 input
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// <id> tcc_arch_tceinv0
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#ifndef CONF_TCC0_TCINV0
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#define CONF_TCC0_TCINV0 0
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#endif
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// <q> Timer/Counter Event Input 1
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// <i> This bit is used to enable input event 1 to the TCC
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// <id> tcc_arch_tcei1
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#ifndef CONF_TCC0_TCEI1
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#define CONF_TCC0_TCEI1 0
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#endif
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// <q> Timer/Counter Event Input 1 Invert
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// <i> This bit inverts the event 1 input
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// <id> tcc_arch_tceinv1
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#ifndef CONF_TCC0_TCINV1
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#define CONF_TCC0_TCINV1 0
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#endif
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// <q> Timer/Counter Event Output
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// <i> This bit is used to enable the counter cycle event.
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//<id> tcc_arch_cnteo
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#ifndef CONF_TCC0_CNTEO
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#define CONF_TCC0_CNTEO 0
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#endif
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// <q> Re-trigger Event Output
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// <i> This bit is used to enable the counter re-trigger event.
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//<id> tcc_arch_trgeo
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#ifndef CONF_TCC0_TRGEO
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#define CONF_TCC0_TRGEO 0
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#endif
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// <q> Overflow/Underflow Event Output
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// <i> This bit is used to enable enable event on overflow/underflow.
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//<id> tcc_arch_ovfeo
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#ifndef CONF_TCC0_OVFEO
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#define CONF_TCC0_OVFEO 0
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#endif
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// <o> Timer/Counter Interrupt and Event Output Selection
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// <0=> An interrupt/event is generated when a new counter cycle starts
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// <1=> An interrupt/event is generated when a counter cycle ends
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// <2=> An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
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// <3=> An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
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// <i> These bits define on which part of the counter cycle the counter event output is generated
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// <id> tcc_arch_cntsel
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#ifndef CONF_TCC0_CNTSEL
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#define CONF_TCC0_CNTSEL 0
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#endif
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// <o> Timer/Counter Event Input 0 Action
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// <0=>Event action disabled
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// <1=>Start restart or re-trigger on event
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// <2=>Count on event
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// <3=>Start on event
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// <4=>Increment on event
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// <5=>Count on active state of asynchronous event
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// <6=>Capture overflow times (Max value)
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// <7=>Non-recoverable fault
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// <i> These bits define the action the TCC performs on TCE0 event input 0
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// <id> tcc_arch_evact0
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#ifndef CONF_TCC0_EVACT0
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#define CONF_TCC0_EVACT0 0
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#endif
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// <o> Timer/Counter Event Input 1 Action
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// <0=>Event action disabled
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// <1=>Re-trigger counter on event
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// <2=>Direction control
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// <3=>Stop counter on event
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// <4=>Decrement counter on event
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// <5=>Period capture value in CC0 register, pulse width capture value in CC1 register
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// <6=>Period capture value in CC1 register, pulse width capture value in CC0 register
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// <7=>Non-recoverable fault
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// <i> These bits define the action the TCC performs on TCE0 event input 0
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// <id> tcc_arch_evact1
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#ifndef CONF_TCC0_EVACT1
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#define CONF_TCC0_EVACT1 0
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#endif
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// </e>
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/* Commented intentionally. No pattern control for timers. */
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/*#define CONF_TCC0_PGE0 0
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#define CONF_TCC0_PGE1 0
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#define CONF_TCC0_PGE2 0
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#define CONF_TCC0_PGE3 0
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#define CONF_TCC0_PGE4 0
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#define CONF_TCC0_PGE5 0
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#define CONF_TCC0_PGE6 0
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#define CONF_TCC0_PGE7 0
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#define CONF_TCC0_PGV0 0
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#define CONF_TCC0_PGV1 0
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#define CONF_TCC0_PGV2 0
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#define CONF_TCC0_PGV3 0
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#define CONF_TCC0_PGV4 0
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#define CONF_TCC0_PGV5 0
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#define CONF_TCC0_PGV6 0
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#define CONF_TCC0_PGV7 0*/
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/* Commented intentionally. No pattern waveform control for timers. */
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/*#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_MFRQ_Val
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#define CONF_TCC0_RAMP TCC_WAVE_RAMP_RAMP1_Val
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#define CONF_TCC0_CIPEREN 0
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#define CONF_TCC0_CICCEN0 0
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#define CONF_TCC0_CICCEN1 0
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#define CONF_TCC0_CICCEN2 0
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#define CONF_TCC0_CICCEN3 0
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#define CONF_TCC0_POL0 0
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#define CONF_TCC0_POL1 0
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#define CONF_TCC0_POL2 0
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#define CONF_TCC0_POL3 0
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#define CONF_TCC0_POL4 0
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#define CONF_TCC0_POL5 0
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#define CONF_TCC0_POL6 0
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#define CONF_TCC0_POL7 0
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#define CONF_TCC0_SWAP0 0
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#define CONF_TCC0_SWAP1 0
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#define CONF_TCC0_SWAP2 0
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#define CONF_TCC0_SWAP3 0*/
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//<o> TCC0 Compare and Capture value 0 <0x00-0xFFFFFF>
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// <id> tcc_arch_cc0
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#ifndef CONF_TCC0_CC0
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#define CONF_TCC0_CC0 0x0
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#endif
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//<o> TCC0 Compare and Capture value 1 <0x00-0xFFFFFF>
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// <id> tcc_arch_cc1
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#ifndef CONF_TCC0_CC1
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#define CONF_TCC0_CC1 0x0
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#endif
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//<o> TCC0 Compare and Capture value 2 <0x00-0xFFFFFF>
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// <id> tcc_arch_cc2
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#ifndef CONF_TCC0_CC2
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#define CONF_TCC0_CC2 0x0
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#endif
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//<o> TCC0 Compare and Capture value 3 <0x00-0xFFFFFF>
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// <id> tcc_arch_cc3
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#ifndef CONF_TCC0_CC3
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#define CONF_TCC0_CC3 0x0
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#endif
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/* Commented intentionally. No pattern control for timers. */
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/*#define CONF_TCC0_PATTB_PGEB0 0
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#define CONF_TCC0_PATTB_PGEB1 0
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#define CONF_TCC0_PATTB_PGEB2 0
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#define CONF_TCC0_PATTB_PGEB3 0
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#define CONF_TCC0_PATTB_PGEB4 0
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#define CONF_TCC0_PATTB_PGEB5 0
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#define CONF_TCC0_PATTB_PGEB6 0
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#define CONF_TCC0_PATTB_PGEB7 0
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#define CONF_TCC0_PATTB_PGVB0 0
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#define CONF_TCC0_PATTB_PGVB1 0
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#define CONF_TCC0_PATTB_PGVB2 0
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#define CONF_TCC0_PATTB_PGVB3 0
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#define CONF_TCC0_PATTB_PGVB4 0
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#define CONF_TCC0_PATTB_PGVB5 0
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#define CONF_TCC0_PATTB_PGVB6 0
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#define CONF_TCC0_PATTB_PGVB7 0*/
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|
|
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/* Commented intentionally. No waveform control for timers. */
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/*#define CONF_TCC0_WAVEGENB TCC_WAVEB_WAVEGENB_MFRQ_Val
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#define CONF_TCC0_RAMPB TCC_WAVE_RAMP_RAMP1_Val
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#define CONF_TCC0_CIPERENB 0
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#define CONF_TCC0_CICCEN0B 0
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#define CONF_TCC0_CICCEN1B 0
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#define CONF_TCC0_CICCEN2B 0
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#define CONF_TCC0_CICCEN3B 0
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#define CONF_TCC0_POL0B 0
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#define CONF_TCC0_POL1B 0
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#define CONF_TCC0_POL2B 0
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#define CONF_TCC0_POL3B 0
|
|
#define CONF_TCC0_POL4B 0
|
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#define CONF_TCC0_POL5B 0
|
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#define CONF_TCC0_POL6B 0
|
|
#define CONF_TCC0_POL7B 0
|
|
#define CONF_TCC0_SWAP0B 0
|
|
#define CONF_TCC0_SWAP1B 0
|
|
#define CONF_TCC0_SWAP2B 0
|
|
#define CONF_TCC0_SWAP3B 0*/
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|
|
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/* Commented intentionally. No buffering for timers. */
|
|
/*#define CONF_TCC0_PERB 0
|
|
#define CONF_TCC0_CCB0 0
|
|
#define CONF_TCC0_CCB1 0
|
|
#define CONF_TCC0_CCB2 0
|
|
#define CONF_TCC0_CCB3 0*/
|
|
// </h>
|
|
|
|
#define CONF_TCC0_CTRLA \
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TCC_CTRLA_PRESCALER(CONF_TCC0_PRESCALER) | (CONF_TCC0_RUNSTDBY << TCC_CTRLA_RUNSTDBY_Pos) \
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| TCC_CTRLA_PRESCSYNC(CONF_TCC0_PRESCSYNC) | (CONF_TCC0_CPTEN0 << TCC_CTRLA_CPTEN0_Pos) \
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| (CONF_TCC0_CPTEN1 << TCC_CTRLA_CPTEN1_Pos) | (CONF_TCC0_CPTEN2 << TCC_CTRLA_CPTEN2_Pos) \
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|
| (CONF_TCC0_CPTEN3 << TCC_CTRLA_CPTEN3_Pos) | (CONF_TCC0_ALOCK << TCC_CTRLA_ALOCK_Pos)
|
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#define CONF_TCC0_CTRLB (CONF_TCC0_LUPD << TCC_CTRLBSET_LUPD_Pos)
|
|
#define CONF_TCC0_DBGCTRL (CONF_TCC0_DBGRUN << TCC_DBGCTRL_DBGRUN_Pos)
|
|
#define CONF_TCC0_EVCTRL \
|
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TCC_EVCTRL_CNTSEL(CONF_TCC0_CNTSEL) | (CONF_TCC0_OVFEO << TCC_EVCTRL_OVFEO_Pos) \
|
|
| (CONF_TCC0_TRGEO << TCC_EVCTRL_TRGEO_Pos) | (CONF_TCC0_CNTEO << TCC_EVCTRL_CNTEO_Pos) \
|
|
| (CONF_TCC0_MCEO0 << TCC_EVCTRL_MCEO0_Pos) | (CONF_TCC0_MCEI0 << TCC_EVCTRL_MCEI0_Pos) \
|
|
| (CONF_TCC0_MCEO1 << TCC_EVCTRL_MCEO1_Pos) | (CONF_TCC0_MCEI1 << TCC_EVCTRL_MCEI1_Pos) \
|
|
| (CONF_TCC0_MCEO2 << TCC_EVCTRL_MCEO2_Pos) | (CONF_TCC0_MCEI2 << TCC_EVCTRL_MCEI2_Pos) \
|
|
| (CONF_TCC0_MCEO3 << TCC_EVCTRL_MCEO3_Pos) | (CONF_TCC0_MCEI3 << TCC_EVCTRL_MCEI3_Pos) \
|
|
| (CONF_TCC0_TCEI0 << TCC_EVCTRL_TCEI0_Pos) | (CONF_TCC0_TCEI1 << TCC_EVCTRL_TCEI1_Pos) \
|
|
| (CONF_TCC0_TCINV0 << TCC_EVCTRL_TCINV0_Pos) | (CONF_TCC0_TCINV1 << TCC_EVCTRL_TCINV1_Pos) \
|
|
| TCC_EVCTRL_EVACT1(CONF_TCC0_EVACT1) | TCC_EVCTRL_EVACT0(CONF_TCC0_EVACT0)
|
|
|
|
// <<< end of configuration section >>>
|
|
|
|
#endif // HPL_TCC_CONFIG_H
|