770 lines
21 KiB
C
770 lines
21 KiB
C
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/**
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* \file
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*
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* \brief SAM Analog Digital Converter
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <hpl_adc_async.h>
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#include <hpl_adc_dma.h>
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#include <hpl_adc_sync.h>
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#include <utils_assert.h>
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#include <utils_repeat_macro.h>
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#include <hpl_adc_config.h>
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#ifndef CONF_ADC_0_ENABLE
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#define CONF_ADC_0_ENABLE 0
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#endif
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#ifndef CONF_ADC_1_ENABLE
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#define CONF_ADC_1_ENABLE 0
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#endif
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/**
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* \brief Macro is used to fill ADC configuration structure based on its number
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*
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* \param[in] n The number of structures
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*/
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#define ADC_CONFIGURATION(n) \
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{ \
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(n), \
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(CONF_ADC_##n##_RUNSTDBY << ADC_CTRLA_RUNSTDBY_Pos) | (CONF_ADC_##n##_ONDEMAND << ADC_CTRLA_ONDEMAND_Pos), \
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ADC_CTRLB_PRESCALER(CONF_ADC_##n##_PRESCALER), \
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(CONF_ADC_##n##_REFCOMP << ADC_REFCTRL_REFCOMP_Pos) | ADC_REFCTRL_REFSEL(CONF_ADC_##n##_REFSEL), \
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(CONF_ADC_##n##_WINMONEO << ADC_EVCTRL_WINMONEO_Pos) \
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| (CONF_ADC_##n##_RESRDYEO << ADC_EVCTRL_RESRDYEO_Pos) \
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| (CONF_ADC_##n##_STARTINV << ADC_EVCTRL_STARTINV_Pos) \
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| (CONF_ADC_##n##_FLUSHINV << ADC_EVCTRL_FLUSHINV_Pos) \
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| (CONF_ADC_##n##_STARTEI << ADC_EVCTRL_STARTEI_Pos) \
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| (CONF_ADC_##n##_FLUSHEI << ADC_EVCTRL_FLUSHEI_Pos), \
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ADC_INPUTCTRL_MUXNEG(CONF_ADC_##n##_MUXNEG) | ADC_INPUTCTRL_MUXPOS(CONF_ADC_##n##_MUXPOS), \
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ADC_CTRLC_WINMODE(CONF_ADC_##n##_WINMODE) | ADC_CTRLC_RESSEL(CONF_ADC_##n##_RESSEL) \
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| (CONF_ADC_##n##_CORREN << ADC_CTRLC_CORREN_Pos) | (CONF_ADC_##n##_FREERUN << ADC_CTRLC_FREERUN_Pos) \
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| (CONF_ADC_##n##_LEFTADJ << ADC_CTRLC_LEFTADJ_Pos) \
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| (CONF_ADC_##n##_DIFFMODE << ADC_CTRLC_DIFFMODE_Pos), \
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ADC_AVGCTRL_ADJRES(CONF_ADC_##n##_ADJRES) | ADC_AVGCTRL_SAMPLENUM(CONF_ADC_##n##_SAMPLENUM), \
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(CONF_ADC_##n##_OFFCOMP << ADC_SAMPCTRL_OFFCOMP_Pos) | ADC_SAMPCTRL_SAMPLEN(CONF_ADC_##n##_SAMPLEN), \
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ADC_WINLT_WINLT(CONF_ADC_##n##_WINLT), ADC_WINUT_WINUT(CONF_ADC_##n##_WINUT), \
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ADC_GAINCORR_GAINCORR(CONF_ADC_##n##_GAINCORR), ADC_OFFSETCORR_OFFSETCORR(CONF_ADC_##n##_OFFSETCORR), \
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CONF_ADC_##n##_DBGRUN << ADC_DBGCTRL_DBGRUN_Pos, ADC_SEQCTRL_SEQEN(CONF_ADC_##n##_SEQEN), \
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}
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/**
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* \brief ADC configuration
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*/
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struct adc_configuration {
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uint8_t number;
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hri_adc_ctrla_reg_t ctrl_a;
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hri_adc_ctrlb_reg_t ctrl_b;
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hri_adc_refctrl_reg_t ref_ctrl;
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hri_adc_evctrl_reg_t ev_ctrl;
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hri_adc_inputctrl_reg_t input_ctrl;
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hri_adc_ctrlc_reg_t ctrl_c;
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hri_adc_avgctrl_reg_t avg_ctrl;
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hri_adc_sampctrl_reg_t samp_ctrl;
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hri_adc_winlt_reg_t win_lt;
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hri_adc_winut_reg_t win_ut;
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hri_adc_gaincorr_reg_t gain_corr;
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hri_adc_offsetcorr_reg_t offset_corr;
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hri_adc_dbgctrl_reg_t dbg_ctrl;
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hri_adc_seqctrl_reg_t seq_ctrl;
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};
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#define ADC_AMOUNT (CONF_ADC_0_ENABLE + CONF_ADC_1_ENABLE)
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/**
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* \brief Array of ADC configurations
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*/
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static const struct adc_configuration _adcs[] = {
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#if CONF_ADC_0_ENABLE == 1
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ADC_CONFIGURATION(0),
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#endif
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#if CONF_ADC_1_ENABLE == 1
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ADC_CONFIGURATION(1),
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#endif
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};
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static void _adc_set_reference_source(void *const hw, const adc_reference_t reference);
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/**
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* \brief Retrieve ordinal number of the given adc hardware instance
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*/
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static uint8_t _adc_get_hardware_index(const void *const hw)
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{
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(void)hw;
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return 0;
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}
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/** \brief Return the pointer to register settings of specific ADC
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* \param[in] hw_addr The hardware register base address.
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* \return Pointer to register settings of specific ADC.
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*/
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static uint8_t _adc_get_regs(const uint32_t hw_addr)
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{
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uint8_t n = _adc_get_hardware_index((const void *)hw_addr);
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uint8_t i;
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for (i = 0; i < sizeof(_adcs) / sizeof(struct adc_configuration); i++) {
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if (_adcs[i].number == n) {
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return i;
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}
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}
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ASSERT(false);
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return 0;
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}
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/**
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* \brief Retrieve IRQ number for the given hardware instance
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*/
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static uint8_t _adc_get_irq_num(const struct _adc_async_device *const device)
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{
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(void)device;
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return ADC_IRQn;
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}
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/**
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* \brief Init irq param with the given afec hardware instance
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*/
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static void _adc_init_irq_param(const void *const hw, struct _adc_async_device *dev)
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{
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}
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/**
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* \brief Initialize ADC
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*
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* \param[in] hw The pointer to hardware instance
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* \param[in] i The number of hardware instance
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*/
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static int32_t _adc_init(void *const hw, const uint8_t i)
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{
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uint16_t calib_reg = 0;
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calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC_FUSES_BIASREFBUF_ADDR >> ADC_FUSES_BIASREFBUF_Pos))
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| ADC_CALIB_BIASCOMP((*(uint32_t *)ADC_FUSES_BIASCOMP_ADDR >> ADC_FUSES_BIASCOMP_Pos));
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ASSERT(hw == ADC);
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if (!hri_adc_is_syncing(hw, ADC_SYNCBUSY_SWRST)) {
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if (hri_adc_get_CTRLA_reg(hw, ADC_CTRLA_ENABLE)) {
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hri_adc_clear_CTRLA_ENABLE_bit(hw);
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hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_ENABLE);
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}
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hri_adc_write_CTRLA_reg(hw, ADC_CTRLA_SWRST);
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}
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hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
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hri_adc_write_CALIB_reg(hw, calib_reg);
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hri_adc_write_CTRLB_reg(hw, _adcs[i].ctrl_b);
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hri_adc_write_REFCTRL_reg(hw, _adcs[i].ref_ctrl);
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hri_adc_write_EVCTRL_reg(hw, _adcs[i].ev_ctrl);
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hri_adc_write_INPUTCTRL_reg(hw, _adcs[i].input_ctrl);
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hri_adc_write_CTRLC_reg(hw, _adcs[i].ctrl_c);
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hri_adc_write_AVGCTRL_reg(hw, _adcs[i].avg_ctrl);
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hri_adc_write_SAMPCTRL_reg(hw, _adcs[i].samp_ctrl);
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hri_adc_write_WINLT_reg(hw, _adcs[i].win_lt);
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hri_adc_write_WINUT_reg(hw, _adcs[i].win_ut);
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hri_adc_write_GAINCORR_reg(hw, _adcs[i].gain_corr);
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hri_adc_write_OFFSETCORR_reg(hw, _adcs[i].offset_corr);
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hri_adc_write_DBGCTRL_reg(hw, _adcs[i].dbg_ctrl);
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hri_adc_write_SEQCTRL_reg(hw, _adcs[i].seq_ctrl);
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hri_adc_write_CTRLA_reg(hw, _adcs[i].ctrl_a);
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return ERR_NONE;
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}
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/**
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* \brief De-initialize ADC
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*
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* \param[in] hw The pointer to hardware instance
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*/
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static inline void _adc_deinit(void *hw)
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{
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hri_adc_clear_CTRLA_ENABLE_bit(hw);
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hri_adc_set_CTRLA_SWRST_bit(hw);
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}
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/**
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* \brief Initialize ADC
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*/
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int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw)
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{
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ASSERT(device);
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device->hw = hw;
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return _adc_init(hw, _adc_get_regs((uint32_t)hw));
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}
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/**
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* \brief Initialize ADC
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*/
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int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw)
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{
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int32_t init_status;
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ASSERT(device);
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init_status = _adc_init(hw, _adc_get_regs((uint32_t)hw));
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if (init_status) {
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return init_status;
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}
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device->hw = hw;
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_adc_init_irq_param(hw, device);
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NVIC_DisableIRQ(_adc_get_irq_num(device));
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NVIC_ClearPendingIRQ(_adc_get_irq_num(device));
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NVIC_EnableIRQ(_adc_get_irq_num(device));
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return ERR_NONE;
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}
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/**
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* \brief Initialize ADC
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*/
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int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw)
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{
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ASSERT(device);
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device->hw = hw;
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return _adc_init(hw, _adc_get_regs((uint32_t)hw));
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}
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/**
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* \brief De-initialize ADC
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*/
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void _adc_sync_deinit(struct _adc_sync_device *const device)
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{
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_adc_deinit(device->hw);
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}
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/**
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* \brief De-initialize ADC
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*/
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void _adc_async_deinit(struct _adc_async_device *const device)
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{
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NVIC_DisableIRQ(_adc_get_irq_num(device));
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NVIC_ClearPendingIRQ(_adc_get_irq_num(device));
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_adc_deinit(device->hw);
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}
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/**
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* \brief De-initialize ADC
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*/
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void _adc_dma_deinit(struct _adc_dma_device *const device)
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{
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_adc_deinit(device->hw);
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}
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/**
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* \brief Enable ADC
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*/
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void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_set_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Enable ADC
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*/
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void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_set_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Enable ADC
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*/
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void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_set_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Disable ADC
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*/
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void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Disable ADC
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*/
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void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Disable ADC
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*/
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void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Return address of ADC DMA source
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*/
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uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device)
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{
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return (uint32_t) & (((Adc *)(device->hw))->RESULT.reg);
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}
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/**
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* \brief Retrieve ADC conversion data size
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*/
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uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device)
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{
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return hri_adc_read_CTRLC_RESSEL_bf(device->hw) == ADC_CTRLC_RESSEL_8BIT_Val ? 1 : 2;
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}
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/**
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* \brief Retrieve ADC conversion data size
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*/
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uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device)
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{
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return hri_adc_read_CTRLC_RESSEL_bf(device->hw) == ADC_CTRLC_RESSEL_8BIT_Val ? 1 : 2;
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}
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/**
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* \brief Retrieve ADC conversion data size
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*/
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uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device)
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{
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return hri_adc_read_CTRLC_RESSEL_bf(device->hw) == ADC_CTRLC_RESSEL_8BIT_Val ? 1 : 2;
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}
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/**
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* \brief Check if conversion is done
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*/
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bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel)
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{
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(void)channel;
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return hri_adc_get_interrupt_RESRDY_bit(device->hw);
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}
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/**
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* \brief Check if conversion is done
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*/
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bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel)
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{
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(void)channel;
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return hri_adc_get_interrupt_RESRDY_bit(device->hw);
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}
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/**
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* \brief Check if conversion is done
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*/
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bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device)
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{
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return hri_adc_get_interrupt_RESRDY_bit(device->hw);
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}
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/**
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* \brief Make conversion
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*/
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void _adc_sync_convert(struct _adc_sync_device *const device)
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{
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hri_adc_set_SWTRIG_START_bit(device->hw);
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}
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/**
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* \brief Make conversion
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*/
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void _adc_async_convert(struct _adc_async_device *const device)
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{
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hri_adc_set_SWTRIG_START_bit(device->hw);
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}
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/**
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* \brief Make conversion
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*/
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void _adc_dma_convert(struct _adc_dma_device *const device)
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{
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hri_adc_set_SWTRIG_START_bit(device->hw);
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}
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/**
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* \brief Retrieve the conversion result
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*/
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uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel)
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{
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(void)channel;
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return hri_adc_read_RESULT_reg(device->hw);
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}
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/**
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* \brief Retrieve the conversion result
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*/
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uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel)
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{
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(void)channel;
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return hri_adc_read_RESULT_reg(device->hw);
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}
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/**
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* \brief Set reference source
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*/
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void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference)
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{
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_adc_set_reference_source(device->hw, reference);
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}
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/**
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* \brief Set reference source
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*/
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void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference)
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{
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_adc_set_reference_source(device->hw, reference);
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}
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/**
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* \brief Set reference source
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*/
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void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference)
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{
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_adc_set_reference_source(device->hw, reference);
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}
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/**
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* \brief Set resolution
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*/
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void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution)
|
|
{
|
|
hri_adc_write_CTRLC_RESSEL_bf(device->hw, resolution);
|
|
}
|
|
|
|
/**
|
|
* \brief Set resolution
|
|
*/
|
|
void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution)
|
|
{
|
|
hri_adc_write_CTRLC_RESSEL_bf(device->hw, resolution);
|
|
}
|
|
|
|
/**
|
|
* \brief Set resolution
|
|
*/
|
|
void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution)
|
|
{
|
|
hri_adc_write_CTRLC_RESSEL_bf(device->hw, resolution);
|
|
}
|
|
|
|
/**
|
|
* \brief Set channels input sources
|
|
*/
|
|
void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
|
|
const adc_neg_input_t neg_input, const uint8_t channel)
|
|
{
|
|
(void)channel;
|
|
|
|
hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
|
|
hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
|
|
}
|
|
|
|
/**
|
|
* \brief Set channels input sources
|
|
*/
|
|
void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
|
|
const adc_neg_input_t neg_input, const uint8_t channel)
|
|
{
|
|
(void)channel;
|
|
|
|
hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
|
|
hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
|
|
}
|
|
|
|
/**
|
|
* \brief Set channels input source
|
|
*/
|
|
void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
|
|
const adc_neg_input_t neg_input, const uint8_t channel)
|
|
{
|
|
(void)channel;
|
|
|
|
hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
|
|
hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
|
|
}
|
|
|
|
/**
|
|
* \brief Set thresholds
|
|
*/
|
|
void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
|
|
const adc_threshold_t up_threshold)
|
|
{
|
|
hri_adc_write_WINLT_reg(device->hw, low_threshold);
|
|
hri_adc_write_WINUT_reg(device->hw, up_threshold);
|
|
}
|
|
|
|
/**
|
|
* \brief Set thresholds
|
|
*/
|
|
void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
|
|
const adc_threshold_t up_threshold)
|
|
{
|
|
hri_adc_write_WINLT_reg(device->hw, low_threshold);
|
|
hri_adc_write_WINUT_reg(device->hw, up_threshold);
|
|
}
|
|
|
|
/**
|
|
* \brief Set thresholds
|
|
*/
|
|
void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
|
|
const adc_threshold_t up_threshold)
|
|
{
|
|
hri_adc_write_WINLT_reg(device->hw, low_threshold);
|
|
hri_adc_write_WINUT_reg(device->hw, up_threshold);
|
|
}
|
|
|
|
/**
|
|
* \brief Set gain
|
|
*/
|
|
void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain)
|
|
{
|
|
(void)device, (void)channel, (void)gain;
|
|
}
|
|
|
|
/**
|
|
* \brief Set gain
|
|
*/
|
|
void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain)
|
|
{
|
|
(void)device, (void)channel, (void)gain;
|
|
}
|
|
|
|
/**
|
|
* \brief Set gain
|
|
*/
|
|
void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain)
|
|
{
|
|
(void)device, (void)channel, (void)gain;
|
|
}
|
|
|
|
/**
|
|
* \brief Set conversion mode
|
|
*/
|
|
void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode)
|
|
{
|
|
if (ADC_CONVERSION_MODE_FREERUN == mode) {
|
|
hri_adc_set_CTRLC_FREERUN_bit(device->hw);
|
|
} else {
|
|
hri_adc_clear_CTRLC_FREERUN_bit(device->hw);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Set conversion mode
|
|
*/
|
|
void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode)
|
|
{
|
|
if (ADC_CONVERSION_MODE_FREERUN == mode) {
|
|
hri_adc_set_CTRLC_FREERUN_bit(device->hw);
|
|
} else {
|
|
hri_adc_clear_CTRLC_FREERUN_bit(device->hw);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Set conversion mode
|
|
*/
|
|
void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode)
|
|
{
|
|
if (ADC_CONVERSION_MODE_FREERUN == mode) {
|
|
hri_adc_set_CTRLC_FREERUN_bit(device->hw);
|
|
} else {
|
|
hri_adc_clear_CTRLC_FREERUN_bit(device->hw);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Set differential mode
|
|
*/
|
|
void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
|
|
const enum adc_differential_mode mode)
|
|
{
|
|
(void)channel;
|
|
|
|
if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
|
|
hri_adc_set_CTRLC_DIFFMODE_bit(device->hw);
|
|
} else {
|
|
hri_adc_clear_CTRLC_DIFFMODE_bit(device->hw);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Set differential mode
|
|
*/
|
|
void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
|
|
const enum adc_differential_mode mode)
|
|
{
|
|
(void)channel;
|
|
|
|
if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
|
|
hri_adc_set_CTRLC_DIFFMODE_bit(device->hw);
|
|
} else {
|
|
hri_adc_clear_CTRLC_DIFFMODE_bit(device->hw);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Set differential mode
|
|
*/
|
|
void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
|
|
const enum adc_differential_mode mode)
|
|
{
|
|
(void)channel;
|
|
|
|
if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
|
|
hri_adc_set_CTRLC_DIFFMODE_bit(device->hw);
|
|
} else {
|
|
hri_adc_clear_CTRLC_DIFFMODE_bit(device->hw);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Set window mode
|
|
*/
|
|
void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode)
|
|
{
|
|
hri_adc_write_CTRLC_WINMODE_bf(device->hw, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Set window mode
|
|
*/
|
|
void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode)
|
|
{
|
|
hri_adc_write_CTRLC_WINMODE_bf(device->hw, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Set window mode
|
|
*/
|
|
void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode)
|
|
{
|
|
hri_adc_write_CTRLC_WINMODE_bf(device->hw, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Retrieve threshold state
|
|
*/
|
|
void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state)
|
|
{
|
|
*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
|
|
}
|
|
|
|
/**
|
|
* \brief Retrieve threshold state
|
|
*/
|
|
void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state)
|
|
{
|
|
*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
|
|
}
|
|
|
|
/**
|
|
* \brief Retrieve threshold state
|
|
*/
|
|
void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state)
|
|
{
|
|
*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
|
|
}
|
|
|
|
/**
|
|
* \brief Enable/disable ADC channel interrupt
|
|
*/
|
|
void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
|
|
const enum _adc_async_callback_type type, const bool state)
|
|
{
|
|
(void)channel;
|
|
|
|
void *const hw = device->hw;
|
|
|
|
if (ADC_ASYNC_DEVICE_MONITOR_CB == type) {
|
|
hri_adc_write_INTEN_WINMON_bit(hw, state);
|
|
} else if (ADC_ASYNC_DEVICE_ERROR_CB == type) {
|
|
hri_adc_write_INTEN_OVERRUN_bit(hw, state);
|
|
} else if (ADC_ASYNC_DEVICE_CONVERT_CB == type) {
|
|
hri_adc_write_INTEN_RESRDY_bit(hw, state);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Retrieve ADC sync helper functions
|
|
*/
|
|
void *_adc_get_adc_sync(void)
|
|
{
|
|
return (void *)NULL;
|
|
}
|
|
|
|
/**
|
|
* \brief Retrieve ADC async helper functions
|
|
*/
|
|
void *_adc_get_adc_async(void)
|
|
{
|
|
return (void *)NULL;
|
|
}
|
|
|
|
/**
|
|
* \brief Set ADC reference source
|
|
*
|
|
* \param[in] hw The pointer to hardware instance
|
|
* \param[in] reference The reference to set
|
|
*/
|
|
static void _adc_set_reference_source(void *const hw, const adc_reference_t reference)
|
|
{
|
|
bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw);
|
|
|
|
hri_adc_clear_CTRLA_ENABLE_bit(hw);
|
|
hri_adc_write_REFCTRL_REFSEL_bf(hw, reference);
|
|
|
|
if (enabled) {
|
|
hri_adc_set_CTRLA_ENABLE_bit(hw);
|
|
}
|
|
}
|