337 lines
11 KiB
C
337 lines
11 KiB
C
/**
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* \file
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*
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* \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality
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* Implementation.
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <utils_assert.h>
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#include <hpl_slcd_sync.h>
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#include <hpl_slcd_config.h>
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#include <hpl_slcd_cm_7_seg_mapping.h>
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#include <hpl_slcd_cm_14_seg_mapping.h>
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static int32_t _slcd_sync_set_segment(struct _slcd_sync_device *dev, const uint32_t com, const uint32_t seg,
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const bool on);
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/**
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* \brief SLCD configuration type
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*/
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struct slcd_configuration {
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hri_slcd_ctrla_reg_t ctrla; /*!< Control A Register */
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hri_slcd_ctrlb_reg_t ctrlb; /*!< Control B Register */
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hri_slcd_ctrlc_reg_t ctrlc; /*!< Control C Register */
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hri_slcd_ctrld_reg_t ctrld; /*!< Control D Register */
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};
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/**
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* \brief Array of AC configurations
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*/
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static struct slcd_configuration _slcd
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= {SLCD_CTRLA_DUTY(CONF_SLCD_COM_NUM) | CONF_SLCD_WMOD << SLCD_CTRLA_WMOD_Pos
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| CONF_SLCD_RUNSTDBY << SLCD_CTRLA_RUNSTDBY_Pos | SLCD_CTRLA_PRESC(CONF_SLCD_PRESC)
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| SLCD_CTRLA_CKDIV(CONF_SLCD_CKDIV) | SLCD_CTRLA_BIAS(CONF_SLCD_BIAS)
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| CONF_SLCD_XVLCD << SLCD_CTRLA_XVLCD_Pos | SLCD_CTRLA_PRF(CONF_SLCD_PRF) | SLCD_CTRLA_RRF(CONF_SLCD_RRF),
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CONF_SLCD_BBEN << SLCD_CTRLB_BBEN_Pos | SLCD_CTRLB_BBD(CONF_SLCD_BBD - 1),
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SLCD_CTRLC_CTST(CONF_SLCD_CONTRAST_ADJUST),
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SLCD_CTRLD_DISPEN};
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static const struct slcd_char_setting cm_setting[] = SLCD_CHAR_SETTING_TABLE;
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static const struct slcd_char_mapping cm7_lut[] = SLCD_SEG7_LUT;
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static const struct slcd_char_mapping cm14_lut[] = SLCD_SEG14_LUT;
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/**
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* \brief Initialize SLCD Device Descriptor
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*/
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int32_t _slcd_sync_init(struct _slcd_sync_device *dev, void *const hw)
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{
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if (!hri_slcd_is_syncing(hw, SLCD_SYNCBUSY_SWRST)) {
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if (hri_slcd_get_CTRLA_ENABLE_bit(hw)) {
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hri_slcd_clear_CTRLA_ENABLE_bit(hw);
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hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_ENABLE);
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}
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hri_slcd_write_CTRLA_reg(hw, SLCD_CTRLA_SWRST);
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}
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hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST);
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dev->hw = hw;
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hri_slcd_write_CTRLA_reg(hw, _slcd.ctrla);
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hri_slcd_write_CTRLB_reg(hw, _slcd.ctrlb);
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hri_slcd_write_CTRLC_reg(hw, _slcd.ctrlc);
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hri_slcd_write_CTRLD_reg(hw, _slcd.ctrld);
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hri_slcd_write_LPENL_reg(hw, CONF_SLCD_LPENL);
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hri_slcd_write_LPENH_reg(hw, CONF_SLCD_LPENH);
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hri_slcd_write_SDATAL0_reg(hw, 0);
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hri_slcd_write_SDATAH0_reg(hw, 0);
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hri_slcd_write_SDATAL1_reg(hw, 0);
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hri_slcd_write_SDATAH1_reg(hw, 0);
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hri_slcd_write_SDATAL2_reg(hw, 0);
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hri_slcd_write_SDATAH2_reg(hw, 0);
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hri_slcd_write_SDATAL3_reg(hw, 0);
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hri_slcd_write_SDATAH3_reg(hw, 0);
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hri_slcd_write_SDATAL4_reg(hw, 0);
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hri_slcd_write_SDATAH4_reg(hw, 0);
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hri_slcd_write_SDATAL5_reg(hw, 0);
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hri_slcd_write_SDATAH5_reg(hw, 0);
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hri_slcd_write_SDATAL6_reg(hw, 0);
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hri_slcd_write_SDATAH6_reg(hw, 0);
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hri_slcd_write_SDATAL7_reg(hw, 0);
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hri_slcd_write_SDATAH7_reg(hw, 0);
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hri_slcd_set_BCFG_MODE_bit(dev->hw);
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return ERR_NONE;
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}
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/**
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* \brief DeInitialize SLCD Device Descriptor
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*/
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int32_t _slcd_sync_deinit(struct _slcd_sync_device *dev)
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{
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hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw);
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hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE);
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hri_slcd_set_CTRLA_SWRST_bit(dev->hw);
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dev->hw = NULL;
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return ERR_NONE;
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}
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/**
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* \brief Enable SLCD driver
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*
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* \param[in] dev SLCD device descriptor to be enabled
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*/
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int32_t _slcd_sync_enable(struct _slcd_sync_device *dev)
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{
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hri_slcd_set_CTRLA_ENABLE_bit(dev->hw);
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return ERR_NONE;
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}
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/**
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* \brief Disable SLCD driver
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*/
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int32_t _slcd_sync_disable(struct _slcd_sync_device *dev)
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{
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hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw);
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return ERR_NONE;
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}
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/**
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* \brief Turn on a Segment
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*/
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int32_t _slcd_sync_seg_on(struct _slcd_sync_device *dev, uint32_t seg)
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{
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return _slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), true);
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}
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/**
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* \brief Turn off a Segment
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*/
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int32_t _slcd_sync_seg_off(struct _slcd_sync_device *dev, uint32_t seg)
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{
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return _slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), false);
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}
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/**
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* \brief Blink a Segment
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*/
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int32_t _slcd_sync_seg_blink(struct _slcd_sync_device *dev, uint32_t seg, const uint32_t period)
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{
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if ((SLCD_COMNUM(seg) >= CONF_SLCD_COM_NUM) || (SLCD_SEGNUM(seg) >= CONF_SLCD_SEG_NUM)) {
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return ERR_INVALID_ARG;
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}
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/* COM[0..7], Seg[0,1] support blink */
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if (SLCD_SEGNUM(seg) >= 2) {
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return ERR_INVALID_ARG;
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}
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/* Verify period */
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if (period > SLCD_FC_MAX_MS || period < SLCD_FC_MIN_MS) {
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return ERR_INVALID_ARG;
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}
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/* Set Period, use Frame Counter 0 for blink */
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hri_slcd_clear_CTRLD_FC0EN_bit(dev->hw);
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hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD);
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if (period <= SLCD_FC_BYPASS_MAX_MS) {
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hri_slcd_set_FC0_reg(dev->hw, SLCD_FC0_PB | ((period / (1000 / SLCD_FRAME_FREQUENCY)) - 1));
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} else {
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hri_slcd_set_FC0_reg(dev->hw, (((period / (1000 / SLCD_FRAME_FREQUENCY)) / 8 - 1)));
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}
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hri_slcd_set_CTRLD_FC0EN_bit(dev->hw);
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/* Set Blink Segments */
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_slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), true);
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hri_slcd_clear_CTRLD_BLINK_bit(dev->hw);
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hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw);
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hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE);
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/* Update BCFG */
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if (SLCD_SEGNUM(seg) == 0) {
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hri_slcd_set_BCFG_BSS0_bf(dev->hw, 1 << SLCD_COMNUM(seg));
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} else {
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hri_slcd_set_BCFG_BSS1_bf(dev->hw, 1 << SLCD_COMNUM(seg));
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}
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hri_slcd_set_CTRLA_ENABLE_bit(dev->hw);
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hri_slcd_set_CTRLD_BLINK_bit(dev->hw);
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return ERR_NONE;
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}
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/**
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* \brief Displays a character
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*/
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int32_t _slcd_sync_write_char(struct _slcd_sync_device *dev, const uint8_t character, uint32_t index)
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{
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uint32_t i;
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uint32_t data = ~0;
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if (cm_setting[index].size == 7) {
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for (i = 0; i<sizeof(cm7_lut)>> 2; i++) {
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if (cm7_lut[i].character == character) {
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data = cm7_lut[i].mapping;
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break;
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}
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}
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} else if (cm_setting[index].size == 14) {
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for (i = 0; i<sizeof(cm14_lut)>> 2; i++) {
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if (cm14_lut[i].character == character) {
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data = cm14_lut[i].mapping;
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break;
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}
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}
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}
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if (data == 0xFFFFFFFF) {
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return ERR_INVALID_ARG;
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}
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hri_slcd_write_CMCFG_NSEG_bf(dev->hw, cm_setting[index].nseg);
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hri_slcd_write_CMINDEX_CINDEX_bf(dev->hw, cm_setting[index].com_index);
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hri_slcd_write_CMINDEX_SINDEX_bf(dev->hw, cm_setting[index].seg_index);
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if (cm_setting[index].size == 7) {
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hri_slcd_write_CMDMASK_reg(dev->hw, SEG7_MASK);
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} else if (cm_setting[index].size == 14) {
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hri_slcd_write_CMDMASK_reg(dev->hw, SEG14_MASK);
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}
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while (hri_slcd_get_STATUS_CMWRBUSY_bit(dev->hw))
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;
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hri_slcd_write_CMDATA_reg(dev->hw, data);
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return ERR_NONE;
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}
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/**
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* \brief Start animation play by a segment array
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*/
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int32_t _slcd_sync_start_animation(struct _slcd_sync_device *dev, const uint32_t segs[], uint32_t len,
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const uint32_t period)
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{
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uint32_t i;
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uint32_t csrlen = 0;
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if (len > 16) {
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return ERR_INVALID_ARG;
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}
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/* COM[0..7], Seg[2,3] support animation */
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for (i = 0; i < len; i++) {
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if ((SLCD_SEGNUM(segs[i]) != 2 && SLCD_SEGNUM(segs[i]) != 3)) {
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return ERR_INVALID_ARG;
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}
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}
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/* Verify period */
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if (period > SLCD_FC_MAX_MS || period < SLCD_FC_MIN_MS) {
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return ERR_INVALID_ARG;
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}
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/* Set Period */
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_slcd_sync_set_animation_period(dev, period);
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/* Set animation segments */
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hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw);
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hri_slcd_clear_CTRLD_CSREN_bit(dev->hw);
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hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE | SLCD_SYNCBUSY_CTRLD);
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hri_slcd_set_CSRCFG_FCS_bf(dev->hw, 1);
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hri_slcd_write_CSRCFG_DATA_bf(dev->hw, 0);
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for (i = 0; i < len; i++) {
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hri_slcd_set_CSRCFG_DATA_bf(dev->hw, (1 << ((SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2))));
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if (((SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2)) > csrlen) {
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csrlen = (SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2);
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}
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}
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hri_slcd_set_CSRCFG_SIZE_bf(dev->hw, csrlen + 1);
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hri_slcd_set_BCFG_MODE_bit(dev->hw);
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hri_slcd_set_CTRLD_CSREN_bit(dev->hw);
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hri_slcd_set_CTRLA_ENABLE_bit(dev->hw);
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return ERR_NONE;
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}
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/**
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* \brief Stop animation play by a segment array
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*/
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int32_t _slcd_sync_stop_animation(struct _slcd_sync_device *dev, const uint32_t segs[], uint32_t len)
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{
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/* Not used because of the current version is not supported, Reserved */
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(void)segs;
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(void)len;
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hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD);
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hri_slcd_clear_CTRLD_CSREN_bit(dev->hw);
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return ERR_NONE;
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}
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/**
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* \brief Set animation Frequency
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*/
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int32_t _slcd_sync_set_animation_period(struct _slcd_sync_device *dev, const uint32_t period)
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{
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hri_slcd_clear_CTRLD_FC1EN_bit(dev->hw);
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hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD);
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/* Use Frame Counter 1 for blink */
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if (period <= SLCD_FC_BYPASS_MAX_MS) {
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hri_slcd_set_FC1_reg(dev->hw, SLCD_FC1_PB | ((period / (1000 / SLCD_FRAME_FREQUENCY)) - 1));
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} else {
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hri_slcd_set_FC1_reg(dev->hw, (((period / (1000 / SLCD_FRAME_FREQUENCY)) / 8 - 1)));
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}
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hri_slcd_set_CTRLD_FC1EN_bit(dev->hw);
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return ERR_NONE;
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}
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static int32_t _slcd_sync_set_segment(struct _slcd_sync_device *dev, const uint32_t com, const uint32_t seg,
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const bool on)
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{
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if ((SLCD_COMNUM(seg) >= CONF_SLCD_COM_NUM) || (SLCD_SEGNUM(seg) >= CONF_SLCD_SEG_NUM)) {
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return ERR_INVALID_ARG;
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}
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/* Use register instead hri interface to optimization code */
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if (on) {
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((uint32_t *)&(((Slcd *)dev->hw)->SDATAL0))[(com * 2) + (seg >> 5)]
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|= (seg < 32) ? (1 << seg) : (1 << (seg >> 5));
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} else {
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((uint32_t *)&(((Slcd *)dev->hw)->SDATAL0))[(com * 2) + (seg >> 5)]
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&= ~((seg < 32) ? (1 << seg) : (1 << (seg >> 5)));
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}
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return ERR_NONE;
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}
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