350 lines
8.3 KiB
C
350 lines
8.3 KiB
C
/**
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* \file
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*
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* \brief SAM TCC
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*
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* Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <compiler.h>
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#include <hpl_pwm.h>
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#include <hpl_tcc.h>
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#include <hpl_tcc_config.h>
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#include <hpl_timer.h>
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#include <utils.h>
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#include <utils_assert.h>
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/**
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* \brief TCC configuration type
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*/
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struct tcc_cfg {
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void * hw; /*!< instance of TCC */
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IRQn_Type irq;
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hri_tcc_ctrla_reg_t ctrl_a;
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hri_tcc_ctrlbset_reg_t ctrl_b;
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hri_tcc_dbgctrl_reg_t dbg_ctrl;
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hri_tcc_evctrl_reg_t event_ctrl;
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hri_tcc_cc_reg_t cc0;
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hri_tcc_cc_reg_t cc1;
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hri_tcc_cc_reg_t cc2;
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hri_tcc_cc_reg_t cc3;
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hri_tcc_per_reg_t per;
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};
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/**
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* \brief pwm configuration type
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*/
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struct tcc_pwm_cfg {
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void * hw; /*!< instance of TCC */
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IRQn_Type irq;
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uint8_t sel_ch;
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uint32_t period;
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uint32_t duty_cycle;
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uint32_t wave;
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};
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/**
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* \internal Retrieve configuration
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*
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* \param[in] hw The pointer of TCC base address
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*
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* \return The configuration
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*/
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static struct tcc_cfg *_get_tcc_cfg(void *hw);
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/**
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* \brief Array of TCC configurations
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*/
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static struct tcc_cfg _cfgs[1] = {
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{(void *)TCC0,
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TCC0_IRQn,
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CONF_TCC0_CTRLA,
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CONF_TCC0_CTRLB,
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CONF_TCC0_DBGCTRL,
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CONF_TCC0_EVCTRL,
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CONF_TCC0_CC0,
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CONF_TCC0_CC1,
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CONF_TCC0_CC2,
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CONF_TCC0_CC3,
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CONF_TCC0_PER},
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};
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/**
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* \internal Retrieve configuration
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*
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* \param[in] hw The pointer of TCC base address
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*
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* \return The configuration
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*/
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static struct tcc_pwm_cfg *_get_tcc_pwm_cfg(void *hw);
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/**
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* \brief Array of PWM configurations
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*/
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static struct tcc_pwm_cfg _cfgs_pwm[1] = {
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{(void *)TCC0,
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TCC0_IRQn,
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CONF_TCC0_SEL_CH,
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CONF_TCC0_PER_REG,
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CONF_TCC0_CCX_REG,
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(CONF_TCC0_WAVEGEN << TCC_WAVE_WAVEGEN_Pos)},
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};
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/* Renamed access REG name PERB -> PERBUF */
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#define hri_tcc_write_PERB_reg hri_tcc_write_PERBUF_reg
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#define hri_tcc_read_PERB_reg hri_tcc_read_PERBUF_reg
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/** Renamed access REG name CCB -> CCBUF */
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#define hri_tcc_write_CCB_reg hri_tcc_write_CCBUF_reg
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#define hri_tcc_read_CCB_reg hri_tcc_read_CCBUF_reg
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static struct _pwm_device *_tcc0_dev = NULL;
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/**
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* \brief Init irq param with the given tcc hardware instance
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*/
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static void _tcc_init_irq_param(const void *const hw, void *dev)
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{
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if (hw == TCC0) {
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_tcc0_dev = (struct _pwm_device *)dev;
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}
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}
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/**
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* \brief Initialize TCC for PWM mode
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*/
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int32_t _pwm_init(struct _pwm_device *const device, void *const hw)
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{
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struct tcc_cfg *cfg = _get_tcc_cfg(hw);
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if (cfg == NULL) {
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return ERR_NOT_FOUND;
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}
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struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
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if (cfg_pwm == NULL) {
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return ERR_NOT_FOUND;
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}
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device->hw = hw;
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if (!hri_tcc_is_syncing(hw, TCC_SYNCBUSY_SWRST)) {
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if (hri_tcc_get_CTRLA_reg(hw, TCC_CTRLA_ENABLE)) {
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hri_tcc_clear_CTRLA_ENABLE_bit(hw);
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hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_ENABLE);
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}
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hri_tcc_write_CTRLA_reg(hw, TCC_CTRLA_SWRST);
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}
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hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
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hri_tcc_write_CTRLA_reg(hw, cfg->ctrl_a);
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hri_tcc_set_CTRLB_reg(hw, cfg->ctrl_b);
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hri_tcc_write_DBGCTRL_reg(hw, cfg->dbg_ctrl);
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hri_tcc_write_EVCTRL_reg(hw, cfg->event_ctrl);
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hri_tcc_write_WAVE_reg(hw, cfg_pwm->wave);
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hri_tcc_write_PER_reg(hw, cfg_pwm->period);
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cfg->per = cfg_pwm->period;
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switch (cfg_pwm->sel_ch) {
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case 0:
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cfg->cc0 = cfg_pwm->duty_cycle;
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hri_tcc_write_CC_reg(hw, 0, cfg->cc0);
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break;
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case 1:
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cfg->cc1 = cfg_pwm->duty_cycle;
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hri_tcc_write_CC_reg(hw, 1, cfg->cc1);
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break;
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case 2:
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cfg->cc2 = cfg_pwm->duty_cycle;
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hri_tcc_write_CC_reg(hw, 2, cfg->cc2);
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break;
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case 3:
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cfg->cc3 = cfg_pwm->duty_cycle;
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hri_tcc_write_CC_reg(hw, 3, cfg->cc3);
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break;
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default:
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return ERR_NO_RESOURCE;
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break;
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}
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hri_tcc_clear_CTRLB_LUPD_bit(hw);
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_tcc_init_irq_param(hw, (void *)device);
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NVIC_DisableIRQ((IRQn_Type)cfg_pwm->irq);
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NVIC_ClearPendingIRQ((IRQn_Type)cfg_pwm->irq);
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NVIC_EnableIRQ((IRQn_Type)cfg_pwm->irq);
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return ERR_NONE;
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}
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/**
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* \brief De-initialize TCC for PWM mode
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*/
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void _pwm_deinit(struct _pwm_device *const device)
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{
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void *const hw = device->hw;
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struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
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if (cfg_pwm != NULL) {
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NVIC_DisableIRQ((IRQn_Type)cfg_pwm->irq);
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hri_tcc_clear_CTRLA_ENABLE_bit(hw);
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hri_tcc_set_CTRLA_SWRST_bit(hw);
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}
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}
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/**
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* \brief Start PWM
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*/
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void _pwm_enable(struct _pwm_device *const device)
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{
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hri_tcc_set_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Stop PWM
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*/
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void _pwm_disable(struct _pwm_device *const device)
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{
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hri_tcc_clear_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Set PWM parameter
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*/
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void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle)
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{
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void *const hw = device->hw;
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struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
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if (cfg_pwm != NULL) {
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hri_tcc_write_PERB_reg(hw, period);
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hri_tcc_write_CCB_reg(hw, cfg_pwm->sel_ch, duty_cycle);
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;
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}
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}
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/**
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* \brief Get pwm waveform period value
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*/
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pwm_period_t _pwm_get_period(const struct _pwm_device *const device)
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{
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return (pwm_period_t)(hri_tcc_read_PERB_reg(device->hw));
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}
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/**
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* \brief Get pwm waveform duty cycle
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*/
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uint32_t _pwm_get_duty(const struct _pwm_device *const device)
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{
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void *const hw = device->hw;
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struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
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if (cfg_pwm == NULL) {
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return ERR_NOT_FOUND;
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}
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uint32_t per = hri_tcc_read_PERB_reg(hw);
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uint32_t duty_cycle = hri_tcc_read_CCB_reg(hw, cfg_pwm->sel_ch);
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return ((duty_cycle * 1000) / per);
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}
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/**
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* \brief Check if PWM is running
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*/
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bool _pwm_is_enabled(const struct _pwm_device *const device)
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{
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return hri_tcc_get_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Enable/disable PWM interrupt
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*/
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void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable)
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{
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ASSERT(device);
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if (PWM_DEVICE_PERIOD_CB == type) {
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hri_tcc_write_INTEN_OVF_bit(device->hw, disable);
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} else if (PWM_DEVICE_ERROR_CB == type) {
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hri_tcc_write_INTEN_ERR_bit(device->hw, disable);
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}
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}
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/**
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* \brief Retrieve timer helper functions
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*/
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struct _timer_hpl_interface *_tcc_get_timer(void)
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{
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return NULL;
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}
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/**
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* \brief Retrieve pwm helper functions
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*/
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struct _pwm_hpl_interface *_tcc_get_pwm(void)
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{
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return NULL;
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}
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/**
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* \internal TC interrupt handler for PWM
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*
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* \param[in] instance TC instance number
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*/
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static void tcc_pwm_interrupt_handler(struct _pwm_device *device)
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{
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void *const hw = device->hw;
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if (hri_tcc_get_interrupt_OVF_bit(hw)) {
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hri_tcc_clear_interrupt_OVF_bit(hw);
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if (NULL != device->callback.pwm_period_cb) {
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device->callback.pwm_period_cb(device);
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}
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}
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if (hri_tcc_get_INTEN_ERR_bit(hw)) {
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hri_tcc_clear_interrupt_ERR_bit(hw);
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if (NULL != device->callback.pwm_error_cb) {
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device->callback.pwm_error_cb(device);
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}
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}
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}
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/**
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* \brief TCC interrupt handler
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*/
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void TCC0_Handler(void)
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{
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tcc_pwm_interrupt_handler(_tcc0_dev);
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}
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static struct tcc_cfg *_get_tcc_cfg(void *hw)
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{
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uint8_t i;
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for (i = 0; i < ARRAY_SIZE(_cfgs); i++) {
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if (_cfgs[i].hw == hw) {
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return &(_cfgs[i]);
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}
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}
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return NULL;
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}
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static struct tcc_pwm_cfg *_get_tcc_pwm_cfg(void *hw)
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{
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uint8_t i;
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for (i = 0; i < ARRAY_SIZE(_cfgs_pwm); i++) {
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if (_cfgs_pwm[i].hw == hw) {
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return &(_cfgs_pwm[i]);
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}
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}
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return NULL;
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}
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