b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
1234 lines
40 KiB
C
1234 lines
40 KiB
C
/**
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* \file
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*
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* \brief SAM OSC32KCTRL
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*
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* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAML22_OSC32KCTRL_COMPONENT_
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#ifndef _HRI_OSC32KCTRL_L22_H_INCLUDED_
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#define _HRI_OSC32KCTRL_L22_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS)
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#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define OSC32KCTRL_CRITICAL_SECTION_ENTER()
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#define OSC32KCTRL_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint16_t hri_osc32kctrl_xosc32k_reg_t;
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typedef uint32_t hri_osc32kctrl_intenset_reg_t;
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typedef uint32_t hri_osc32kctrl_intflag_reg_t;
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typedef uint32_t hri_osc32kctrl_osculp32k_reg_t;
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typedef uint32_t hri_osc32kctrl_status_reg_t;
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typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t;
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typedef uint8_t hri_osc32kctrl_evctrl_reg_t;
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typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t;
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typedef uint8_t hri_osc32kctrl_slcdctrl_reg_t;
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static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw)
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{
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return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
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}
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static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw)
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{
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((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
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}
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static inline bool hri_osc32kctrl_get_INTFLAG_CLKFAIL_bit(const void *const hw)
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{
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return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos;
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}
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static inline void hri_osc32kctrl_clear_INTFLAG_CLKFAIL_bit(const void *const hw)
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{
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((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL;
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}
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static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw)
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{
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return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
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}
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static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw)
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{
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((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
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}
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static inline bool hri_osc32kctrl_get_interrupt_CLKFAIL_bit(const void *const hw)
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{
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return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos;
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}
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static inline void hri_osc32kctrl_clear_interrupt_CLKFAIL_bit(const void *const hw)
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{
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((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL;
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}
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static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw,
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hri_osc32kctrl_intflag_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Osc32kctrl *)hw)->INTFLAG.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw)
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{
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return ((Osc32kctrl *)hw)->INTFLAG.reg;
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}
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static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask)
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{
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((Osc32kctrl *)hw)->INTFLAG.reg = mask;
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}
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static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw)
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{
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((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
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}
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static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw)
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{
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return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos;
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}
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static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value)
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{
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if (value == 0x0) {
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((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
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} else {
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((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
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}
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}
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static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw)
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{
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((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
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}
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static inline void hri_osc32kctrl_set_INTEN_CLKFAIL_bit(const void *const hw)
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{
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((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL;
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}
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static inline bool hri_osc32kctrl_get_INTEN_CLKFAIL_bit(const void *const hw)
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{
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return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_CLKFAIL) >> OSC32KCTRL_INTENSET_CLKFAIL_Pos;
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}
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static inline void hri_osc32kctrl_write_INTEN_CLKFAIL_bit(const void *const hw, bool value)
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{
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if (value == 0x0) {
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((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL;
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} else {
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((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL;
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}
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}
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static inline void hri_osc32kctrl_clear_INTEN_CLKFAIL_bit(const void *const hw)
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{
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((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL;
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}
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static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
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{
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((Osc32kctrl *)hw)->INTENSET.reg = mask;
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}
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static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw,
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hri_osc32kctrl_intenset_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Osc32kctrl *)hw)->INTENSET.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw)
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{
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return ((Osc32kctrl *)hw)->INTENSET.reg;
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}
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static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data)
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{
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((Osc32kctrl *)hw)->INTENSET.reg = data;
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((Osc32kctrl *)hw)->INTENCLR.reg = ~data;
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}
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static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
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{
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((Osc32kctrl *)hw)->INTENCLR.reg = mask;
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}
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static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw)
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{
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return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos;
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}
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static inline bool hri_osc32kctrl_get_STATUS_CLKFAIL_bit(const void *const hw)
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{
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return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKFAIL) >> OSC32KCTRL_STATUS_CLKFAIL_Pos;
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}
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static inline bool hri_osc32kctrl_get_STATUS_CLKSW_bit(const void *const hw)
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{
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return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKSW) >> OSC32KCTRL_STATUS_CLKSW_Pos;
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}
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static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw,
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hri_osc32kctrl_status_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Osc32kctrl *)hw)->STATUS.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw)
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{
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return ((Osc32kctrl *)hw)->STATUS.reg;
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}
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static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw,
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hri_osc32kctrl_rtcctrl_reg_t mask)
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{
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uint8_t tmp;
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tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
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tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
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return tmp;
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}
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static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
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{
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uint8_t tmp;
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
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tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk;
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tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data);
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((Osc32kctrl *)hw)->RTCCTRL.reg = tmp;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask);
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw)
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{
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uint8_t tmp;
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tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
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tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
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return tmp;
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}
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static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->RTCCTRL.reg |= mask;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw,
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hri_osc32kctrl_rtcctrl_reg_t mask)
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{
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uint8_t tmp;
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tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->RTCCTRL.reg = data;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw)
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{
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return ((Osc32kctrl *)hw)->RTCCTRL.reg;
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}
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static inline void hri_osc32kctrl_set_SLCDCTRL_SLCDSEL_bit(const void *const hw)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->SLCDCTRL.reg |= OSC32KCTRL_SLCDCTRL_SLCDSEL;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_osc32kctrl_get_SLCDCTRL_SLCDSEL_bit(const void *const hw)
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{
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uint8_t tmp;
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tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg;
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tmp = (tmp & OSC32KCTRL_SLCDCTRL_SLCDSEL) >> OSC32KCTRL_SLCDCTRL_SLCDSEL_Pos;
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return (bool)tmp;
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}
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static inline void hri_osc32kctrl_write_SLCDCTRL_SLCDSEL_bit(const void *const hw, bool value)
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{
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uint8_t tmp;
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg;
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tmp &= ~OSC32KCTRL_SLCDCTRL_SLCDSEL;
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tmp |= value << OSC32KCTRL_SLCDCTRL_SLCDSEL_Pos;
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((Osc32kctrl *)hw)->SLCDCTRL.reg = tmp;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_osc32kctrl_clear_SLCDCTRL_SLCDSEL_bit(const void *const hw)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->SLCDCTRL.reg &= ~OSC32KCTRL_SLCDCTRL_SLCDSEL;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_osc32kctrl_toggle_SLCDCTRL_SLCDSEL_bit(const void *const hw)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->SLCDCTRL.reg ^= OSC32KCTRL_SLCDCTRL_SLCDSEL;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_osc32kctrl_set_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->SLCDCTRL.reg |= mask;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_osc32kctrl_slcdctrl_reg_t hri_osc32kctrl_get_SLCDCTRL_reg(const void *const hw,
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hri_osc32kctrl_slcdctrl_reg_t mask)
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{
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uint8_t tmp;
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tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_osc32kctrl_write_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t data)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->SLCDCTRL.reg = data;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_osc32kctrl_clear_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->SLCDCTRL.reg &= ~mask;
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|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->SLCDCTRL.reg ^= mask;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_osc32kctrl_slcdctrl_reg_t hri_osc32kctrl_read_SLCDCTRL_reg(const void *const hw)
|
|
{
|
|
return ((Osc32kctrl *)hw)->SLCDCTRL.reg;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw)
|
|
{
|
|
uint16_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value)
|
|
{
|
|
uint16_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp &= ~OSC32KCTRL_XOSC32K_ENABLE;
|
|
tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos;
|
|
((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw)
|
|
{
|
|
uint16_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value)
|
|
{
|
|
uint16_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp &= ~OSC32KCTRL_XOSC32K_XTALEN;
|
|
tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos;
|
|
((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw)
|
|
{
|
|
uint16_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value)
|
|
{
|
|
uint16_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp &= ~OSC32KCTRL_XOSC32K_EN32K;
|
|
tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos;
|
|
((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw)
|
|
{
|
|
uint16_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value)
|
|
{
|
|
uint16_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp &= ~OSC32KCTRL_XOSC32K_EN1K;
|
|
tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos;
|
|
((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw)
|
|
{
|
|
uint16_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value)
|
|
{
|
|
uint16_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
|
|
tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
|
|
((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw)
|
|
{
|
|
uint16_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value)
|
|
{
|
|
uint16_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
|
|
tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
|
|
((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw)
|
|
{
|
|
uint16_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value)
|
|
{
|
|
uint16_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
|
|
tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
|
|
((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask);
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw,
|
|
hri_osc32kctrl_xosc32k_reg_t mask)
|
|
{
|
|
uint16_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
|
|
{
|
|
uint16_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk;
|
|
tmp |= OSC32KCTRL_XOSC32K_STARTUP(data);
|
|
((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask);
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask);
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw)
|
|
{
|
|
uint16_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg |= mask;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw,
|
|
hri_osc32kctrl_xosc32k_reg_t mask)
|
|
{
|
|
uint16_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg = data;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->XOSC32K.reg ^= mask;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw)
|
|
{
|
|
return ((Osc32kctrl *)hw)->XOSC32K.reg;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw)
|
|
{
|
|
uint8_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
|
|
tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value)
|
|
{
|
|
uint8_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
|
|
tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN;
|
|
tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos;
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw)
|
|
{
|
|
uint8_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
|
|
tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value)
|
|
{
|
|
uint8_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
|
|
tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK;
|
|
tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos;
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw)
|
|
{
|
|
uint8_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
|
|
tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value)
|
|
{
|
|
uint8_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
|
|
tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
|
|
tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg |= mask;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw,
|
|
hri_osc32kctrl_cfdctrl_reg_t mask)
|
|
{
|
|
uint8_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg = data;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw)
|
|
{
|
|
return ((Osc32kctrl *)hw)->CFDCTRL.reg;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw)
|
|
{
|
|
uint8_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
|
|
tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value)
|
|
{
|
|
uint8_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
|
|
tmp &= ~OSC32KCTRL_EVCTRL_CFDEO;
|
|
tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos;
|
|
((Osc32kctrl *)hw)->EVCTRL.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->EVCTRL.reg |= mask;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw,
|
|
hri_osc32kctrl_evctrl_reg_t mask)
|
|
{
|
|
uint8_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->EVCTRL.reg = data;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->EVCTRL.reg ^= mask;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw)
|
|
{
|
|
return ((Osc32kctrl *)hw)->EVCTRL.reg;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
|
|
tmp &= ~OSC32KCTRL_OSCULP32K_EN32K;
|
|
tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos;
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
|
|
tmp &= ~OSC32KCTRL_OSCULP32K_EN1K;
|
|
tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos;
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
|
|
tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
|
|
tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask);
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw,
|
|
hri_osc32kctrl_osculp32k_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
|
|
tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
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tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk;
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tmp |= OSC32KCTRL_OSCULP32K_CALIB(data);
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((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask);
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask);
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
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{
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uint32_t tmp;
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tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
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tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
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return tmp;
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}
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static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
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{
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OSC32KCTRL_CRITICAL_SECTION_ENTER();
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((Osc32kctrl *)hw)->OSCULP32K.reg |= mask;
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OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw,
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hri_osc32kctrl_osculp32k_reg_t mask)
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|
{
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uint32_t tmp;
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tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
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|
{
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|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
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|
((Osc32kctrl *)hw)->OSCULP32K.reg = data;
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|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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|
}
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|
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static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
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|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
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|
((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask;
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|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
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|
}
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|
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static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
|
|
{
|
|
OSC32KCTRL_CRITICAL_SECTION_ENTER();
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|
((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask;
|
|
OSC32KCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw)
|
|
{
|
|
return ((Osc32kctrl *)hw)->OSCULP32K.reg;
|
|
}
|
|
|
|
#ifdef __cplusplus
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|
}
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|
#endif
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|
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#endif /* _HRI_OSC32KCTRL_L22_H_INCLUDED */
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#endif /* _SAML22_OSC32KCTRL_COMPONENT_ */
|