b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
552 lines
14 KiB
C
552 lines
14 KiB
C
/**
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* \file
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*
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* \brief SAM MTB
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*
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* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAML22_MTB_COMPONENT_
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#ifndef _HRI_MTB_L22_H_INCLUDED_
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#define _HRI_MTB_L22_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_MTB_CRITICAL_SECTIONS)
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#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define MTB_CRITICAL_SECTION_ENTER()
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#define MTB_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint32_t hri_mtb_authstatus_reg_t;
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typedef uint32_t hri_mtb_base_reg_t;
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typedef uint32_t hri_mtb_cid0_reg_t;
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typedef uint32_t hri_mtb_cid1_reg_t;
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typedef uint32_t hri_mtb_cid2_reg_t;
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typedef uint32_t hri_mtb_cid3_reg_t;
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typedef uint32_t hri_mtb_claimset_reg_t;
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typedef uint32_t hri_mtb_devarch_reg_t;
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typedef uint32_t hri_mtb_devid_reg_t;
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typedef uint32_t hri_mtb_devtype_reg_t;
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typedef uint32_t hri_mtb_flow_reg_t;
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typedef uint32_t hri_mtb_itctrl_reg_t;
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typedef uint32_t hri_mtb_lockaccess_reg_t;
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typedef uint32_t hri_mtb_lockstatus_reg_t;
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typedef uint32_t hri_mtb_master_reg_t;
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typedef uint32_t hri_mtb_pid0_reg_t;
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typedef uint32_t hri_mtb_pid1_reg_t;
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typedef uint32_t hri_mtb_pid2_reg_t;
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typedef uint32_t hri_mtb_pid3_reg_t;
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typedef uint32_t hri_mtb_pid4_reg_t;
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typedef uint32_t hri_mtb_pid5_reg_t;
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typedef uint32_t hri_mtb_pid6_reg_t;
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typedef uint32_t hri_mtb_pid7_reg_t;
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typedef uint32_t hri_mtb_position_reg_t;
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static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
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{
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((Mtb *)hw)->CLAIMSET.reg = mask;
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}
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static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->CLAIMSET.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw)
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{
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return ((Mtb *)hw)->CLAIMSET.reg;
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}
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static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data)
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{
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((Mtb *)hw)->CLAIMSET.reg = data;
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((Mtb *)hw)->CLAIMCLR.reg = ~data;
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}
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static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
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{
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((Mtb *)hw)->CLAIMCLR.reg = mask;
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}
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static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->BASE.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw)
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{
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return ((Mtb *)hw)->BASE.reg;
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}
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static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->LOCKSTATUS.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw)
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{
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return ((Mtb *)hw)->LOCKSTATUS.reg;
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}
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static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->AUTHSTATUS.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw)
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{
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return ((Mtb *)hw)->AUTHSTATUS.reg;
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}
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static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->DEVARCH.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw)
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{
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return ((Mtb *)hw)->DEVARCH.reg;
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}
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static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->DEVID.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw)
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{
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return ((Mtb *)hw)->DEVID.reg;
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}
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static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->DEVTYPE.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw)
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{
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return ((Mtb *)hw)->DEVTYPE.reg;
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}
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static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->PID4.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw)
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{
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return ((Mtb *)hw)->PID4.reg;
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}
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static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->PID5.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw)
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{
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return ((Mtb *)hw)->PID5.reg;
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}
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static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->PID6.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw)
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{
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return ((Mtb *)hw)->PID6.reg;
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}
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static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->PID7.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw)
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{
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return ((Mtb *)hw)->PID7.reg;
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}
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static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->PID0.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw)
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{
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return ((Mtb *)hw)->PID0.reg;
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}
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static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->PID1.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw)
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{
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return ((Mtb *)hw)->PID1.reg;
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}
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static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->PID2.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw)
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{
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return ((Mtb *)hw)->PID2.reg;
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}
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static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->PID3.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw)
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{
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return ((Mtb *)hw)->PID3.reg;
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}
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static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->CID0.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw)
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{
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return ((Mtb *)hw)->CID0.reg;
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}
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static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->CID1.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw)
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{
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return ((Mtb *)hw)->CID1.reg;
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}
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static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->CID2.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw)
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{
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return ((Mtb *)hw)->CID2.reg;
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}
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static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->CID3.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw)
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{
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return ((Mtb *)hw)->CID3.reg;
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}
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static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->POSITION.reg |= mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->POSITION.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->POSITION.reg = data;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->POSITION.reg &= ~mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->POSITION.reg ^= mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw)
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{
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return ((Mtb *)hw)->POSITION.reg;
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}
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static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->MASTER.reg |= mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->MASTER.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->MASTER.reg = data;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->MASTER.reg &= ~mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->MASTER.reg ^= mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw)
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{
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return ((Mtb *)hw)->MASTER.reg;
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}
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static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->FLOW.reg |= mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->FLOW.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->FLOW.reg = data;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->FLOW.reg &= ~mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->FLOW.reg ^= mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw)
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{
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return ((Mtb *)hw)->FLOW.reg;
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}
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static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->ITCTRL.reg |= mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Mtb *)hw)->ITCTRL.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->ITCTRL.reg = data;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->ITCTRL.reg &= ~mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->ITCTRL.reg ^= mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw)
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{
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return ((Mtb *)hw)->ITCTRL.reg;
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}
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static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
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{
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MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->LOCKACCESS.reg |= mask;
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MTB_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
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|
{
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|
uint32_t tmp;
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tmp = ((Mtb *)hw)->LOCKACCESS.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data)
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|
{
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|
MTB_CRITICAL_SECTION_ENTER();
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((Mtb *)hw)->LOCKACCESS.reg = data;
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|
MTB_CRITICAL_SECTION_LEAVE();
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}
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|
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static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
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|
{
|
|
MTB_CRITICAL_SECTION_ENTER();
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|
((Mtb *)hw)->LOCKACCESS.reg &= ~mask;
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|
MTB_CRITICAL_SECTION_LEAVE();
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|
}
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|
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static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
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|
{
|
|
MTB_CRITICAL_SECTION_ENTER();
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|
((Mtb *)hw)->LOCKACCESS.reg ^= mask;
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|
MTB_CRITICAL_SECTION_LEAVE();
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|
}
|
|
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|
static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw)
|
|
{
|
|
return ((Mtb *)hw)->LOCKACCESS.reg;
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|
}
|
|
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|
#ifdef __cplusplus
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|
}
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|
#endif
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|
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#endif /* _HRI_MTB_L22_H_INCLUDED */
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#endif /* _SAML22_MTB_COMPONENT_ */
|