b8de35658f
* Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths
499 lines
17 KiB
C
499 lines
17 KiB
C
/**
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* \file
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*
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* \brief SAM SystemControl
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAML22_SystemControl_COMPONENT_
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#ifndef _HRI_SystemControl_L22_H_INCLUDED_
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#define _HRI_SystemControl_L22_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS)
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#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define SystemControl_CRITICAL_SECTION_ENTER()
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#define SystemControl_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint32_t hri_systemcontrol_aircr_reg_t;
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typedef uint32_t hri_systemcontrol_ccr_reg_t;
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typedef uint32_t hri_systemcontrol_cpuid_reg_t;
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typedef uint32_t hri_systemcontrol_dfsr_reg_t;
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typedef uint32_t hri_systemcontrol_icsr_reg_t;
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typedef uint32_t hri_systemcontrol_scr_reg_t;
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typedef uint32_t hri_systemcontrol_shcsr_reg_t;
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typedef uint32_t hri_systemcontrol_shpr2_reg_t;
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typedef uint32_t hri_systemcontrol_shpr3_reg_t;
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typedef uint32_t hri_systemcontrol_vtor_reg_t;
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw,
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hri_systemcontrol_cpuid_reg_t mask)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw,
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hri_systemcontrol_cpuid_reg_t mask)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4;
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}
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static inline hri_systemcontrol_cpuid_reg_t
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hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw,
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hri_systemcontrol_cpuid_reg_t mask)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20;
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}
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static inline hri_systemcontrol_cpuid_reg_t
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hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw,
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hri_systemcontrol_cpuid_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->CPUID.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->CPUID.reg;
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}
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static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_UNALIGN_TRP) >> 3;
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}
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static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_STKALIGN) >> 9;
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}
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static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw,
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hri_systemcontrol_ccr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->CCR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->CCR.reg;
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}
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static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ICSR.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw,
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hri_systemcontrol_icsr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->ICSR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ICSR.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ICSR.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ICSR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->ICSR.reg;
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}
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static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->VTOR.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw,
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hri_systemcontrol_vtor_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->VTOR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->VTOR.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->VTOR.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->VTOR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->VTOR.reg;
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}
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static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->AIRCR.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw,
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hri_systemcontrol_aircr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->AIRCR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->AIRCR.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->AIRCR.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->AIRCR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->AIRCR.reg;
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}
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static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SCR.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw,
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hri_systemcontrol_scr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->SCR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SCR.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SCR.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SCR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->SCR.reg;
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}
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static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHPR2.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw,
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hri_systemcontrol_shpr2_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->SHPR2.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHPR2.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHPR2.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHPR2.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->SHPR2.reg;
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}
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static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHPR3.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw,
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hri_systemcontrol_shpr3_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->SHPR3.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHPR3.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHPR3.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHPR3.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->SHPR3.reg;
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}
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static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHCSR.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const hw,
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hri_systemcontrol_shcsr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->SHCSR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHCSR.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHCSR.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SHCSR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->SHCSR.reg;
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}
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static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->DFSR.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const hw,
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hri_systemcontrol_dfsr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->DFSR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->DFSR.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->DFSR.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->DFSR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->DFSR.reg;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HRI_SystemControl_L22_H_INCLUDED */
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#endif /* _SAML22_SystemControl_COMPONENT_ */
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