95 lines
2.7 KiB
C
95 lines
2.7 KiB
C
#include <stdlib.h>
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#include <string.h>
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#include <stdio.h>
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#include "watch_storage.h"
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#define RWWEE_ADDR_START NVMCTRL_RWW_EEPROM_ADDR
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#define RWWEE_ADDR_END (NVMCTRL_RWW_EEPROM_ADDR + NVMCTRL_PAGE_SIZE * NVMCTRL_RWWEE_PAGES)
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#define NVM_MEMORY ((volatile uint16_t *)FLASH_ADDR)
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static bool _is_valid_address(uint32_t addr, uint32_t size) {
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if ((addr < NVMCTRL_RWW_EEPROM_ADDR) || (addr > (NVMCTRL_RWW_EEPROM_ADDR + NVMCTRL_PAGE_SIZE * NVMCTRL_RWWEE_PAGES))) {
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return false;
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}
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if ((addr + size > (NVMCTRL_RWW_EEPROM_ADDR + NVMCTRL_PAGE_SIZE * NVMCTRL_RWWEE_PAGES))) {
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return false;
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}
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return true;
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}
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bool watch_storage_read(uint32_t row, uint32_t offset, uint8_t *buffer, uint32_t size) {
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uint32_t address = RWWEE_ADDR_START + row * NVMCTRL_ROW_SIZE + offset;
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if (!_is_valid_address(address, size)) return false;
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uint32_t nvm_address = address / 2;
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uint32_t i;
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uint16_t data;
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watch_storage_sync();
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if (address % 2) {
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data = NVM_MEMORY[nvm_address++];
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buffer[0] = data >> 8;
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i = 1;
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} else {
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i = 0;
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}
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while (i < size) {
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data = NVM_MEMORY[nvm_address++];
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buffer[i] = (data & 0xFF);
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if (i < (size - 1)) {
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buffer[i + 1] = (data >> 8);
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}
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i += 2;
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}
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return true;
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}
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bool watch_storage_write(uint32_t row, uint32_t offset, const uint8_t *buffer, uint32_t size) {
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uint32_t address = RWWEE_ADDR_START + row * NVMCTRL_ROW_SIZE + offset;
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if (!_is_valid_address(address, size)) return false;
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watch_storage_sync();
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uint32_t nvm_address = address / 2;
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uint16_t i, data;
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hri_nvmctrl_write_CTRLA_reg(NVMCTRL, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY);
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watch_storage_sync();
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for (i = 0; i < size; i += 2) {
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data = buffer[i];
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if (i < NVMCTRL_PAGE_SIZE - 1) {
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data |= (buffer[i + 1] << 8);
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}
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NVM_MEMORY[nvm_address++] = data;
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}
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hri_nvmctrl_write_ADDR_reg(NVMCTRL, address / 2);
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hri_nvmctrl_write_CTRLA_reg(NVMCTRL, NVMCTRL_CTRLA_CMD_RWWEEWP | NVMCTRL_CTRLA_CMDEX_KEY);
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return true;
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}
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bool watch_storage_erase(uint32_t row) {
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uint32_t address = RWWEE_ADDR_START + row * NVMCTRL_ROW_SIZE;
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if (!_is_valid_address(address, NVMCTRL_ROW_SIZE)) return false;
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watch_storage_sync();
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hri_nvmctrl_write_ADDR_reg(NVMCTRL, address / 2);
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hri_nvmctrl_write_CTRLA_reg(NVMCTRL, NVMCTRL_CTRLA_CMD_RWWEEER | NVMCTRL_CTRLA_CMDEX_KEY);
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return true;
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}
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bool watch_storage_sync(void) {
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while (!hri_nvmctrl_get_interrupt_READY_bit(NVMCTRL)) {
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// wait for flash to become ready
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}
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hri_nvmctrl_clear_STATUS_reg(NVMCTRL, NVMCTRL_STATUS_MASK);
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return true;
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}
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