89 lines
3.1 KiB
C
89 lines
3.1 KiB
C
/**
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* \file
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*
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* \brief SAM 32k Oscillators Controller.
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*
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* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <hpl_init.h>
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#include <compiler.h>
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#include <hpl_osc32kctrl_config.h>
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/**
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* \brief Initialize 32 kHz clock sources
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*/
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void _osc32kctrl_init_sources(void)
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{
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void * hw = (void *)OSC32KCTRL;
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uint16_t calib = 0;
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#if CONF_XOSC32K_CONFIG == 1
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hri_osc32kctrl_write_XOSC32K_reg(
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hw,
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OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
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| (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
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| (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos)
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| (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos)
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| (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos));
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hri_osc32kctrl_write_CFDCTRL_reg(hw,
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(CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
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| (CONF_XOSC32K_SWBEN << OSC32KCTRL_CFDCTRL_SWBACK_Pos));
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hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos));
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#endif
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#if CONF_OSCULP32K_CONFIG == 1
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calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
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hri_osc32kctrl_write_OSCULP32K_reg(hw,
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#if CONF_OSC32K_CALIB_ENABLE == 1
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OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB)
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#else
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OSC32KCTRL_OSCULP32K_CALIB(calib)
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#endif
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);
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#endif
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#if CONF_XOSC32K_CONFIG
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#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0
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while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw))
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;
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#endif
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#if CONF_OSCULP32K_ULP32KSW == 1
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hri_osc32kctrl_set_OSCULP32K_reg(hw, OSC32KCTRL_OSCULP32K_ULP32KSW);
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while (!hri_osc32kctrl_get_STATUS_ULP32KSW_bit(hw))
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;
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#endif
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#endif
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hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
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hri_osc32kctrl_write_SLCDCTRL_SLCDSEL_bit(hw, CONF_SLCDCTRL_SRC);
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(void)calib;
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}
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