WIP simple C-based library for hacking on the watch
This commit is contained in:
Joey Castillo
54
Smol Watch Project/My Project/Config/RTE_Components.h
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54
Smol Watch Project/My Project/Config/RTE_Components.h
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/**
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* \file
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*
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* \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
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*
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* Copyright (c) 2012 Atmel Corporation. All rights reserved.
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*
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* \acme_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \acme_license_stop
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*
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* Project: My Project
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* Target: ATSAML22J18A
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*
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**/
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#ifndef RTE_COMPONENTS_H
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#define RTE_COMPONENTS_H
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#define ATMEL_START
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#endif /* RTE_COMPONENTS_H */
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305
Smol Watch Project/My Project/Config/hpl_adc_config.h
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305
Smol Watch Project/My Project/Config/hpl_adc_config.h
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/* Auto-generated config file hpl_adc_config.h */
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#ifndef HPL_ADC_CONFIG_H
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#define HPL_ADC_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#ifndef CONF_ADC_0_ENABLE
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#define CONF_ADC_0_ENABLE 1
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#endif
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// <h> Basic Configuration
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// <o> Conversion Result Resolution
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// <0x0=>12-bit
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// <0x1=>16-bit (averaging must be enabled)
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// <0x2=>10-bit
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// <0x3=>8-bit
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// <i> Defines the bit resolution for the ADC sample values (RESSEL)
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// <id> adc_resolution
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#ifndef CONF_ADC_0_RESSEL
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#define CONF_ADC_0_RESSEL 0x0
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#endif
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// <o> Reference Selection
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// <0x0=>Internal bandgap reference
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// <0x1=>1/1.6 VDDANA
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// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
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// <0x3=>External reference A
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// <0x4=>External reference B
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// <0x5=>VDDANA
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// <i> Select the reference for the ADC (REFSEL)
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// <id> adc_reference
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#ifndef CONF_ADC_0_REFSEL
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#define CONF_ADC_0_REFSEL 0x0
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#endif
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// <o> Prescaler configuration
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// <0x0=>Peripheral clock divided by 2
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// <0x1=>Peripheral clock divided by 4
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// <0x2=>Peripheral clock divided by 8
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// <0x3=>Peripheral clock divided by 16
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// <0x4=>Peripheral clock divided by 32
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// <0x5=>Peripheral clock divided by 64
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// <0x6=>Peripheral clock divided by 128
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// <0x7=>Peripheral clock divided by 256
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// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
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// <id> adc_prescaler
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#ifndef CONF_ADC_0_PRESCALER
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#define CONF_ADC_0_PRESCALER 0x0
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#endif
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// <q> Free Running Mode
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// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
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// <id> adc_freerunning_mode
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#ifndef CONF_ADC_0_FREERUN
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#define CONF_ADC_0_FREERUN 0
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#endif
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// <q> Differential Mode
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// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
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// <id> adc_differential_mode
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#ifndef CONF_ADC_0_DIFFMODE
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#define CONF_ADC_0_DIFFMODE 0
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#endif
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// <o> Positive Mux Input Selection
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// <0x00=>ADC AIN0 pin
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// <0x01=>ADC AIN1 pin
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// <0x02=>ADC AIN2 pin
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// <0x03=>ADC AIN3 pin
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// <0x04=>ADC AIN4 pin
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// <0x05=>ADC AIN5 pin
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// <0x06=>ADC AIN6 pin
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// <0x07=>ADC AIN7 pin
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// <0x08=>ADC AIN8 pin
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// <0x09=>ADC AIN9 pin
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// <0x0A=>ADC AIN10 pin
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// <0x0B=>ADC AIN11 pin
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// <0x0C=>ADC AIN12 pin
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// <0x0D=>ADC AIN13 pin
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// <0x0E=>ADC AIN14 pin
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// <0x0F=>ADC AIN15 pin
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// <0x10=>ADC AIN16 pin
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// <0x11=>ADC AIN17 pin
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// <0x12=>ADC AIN18 pin
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// <0x13=>ADC AIN19 pin
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// <0x18=>Temperature reference
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// <0x19=>Bandgap voltage
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// <0x1A=>1/4 scaled core supply
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// <0x1B=>1/4 scaled I/O supply
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// <0x1D=>1/4 Scaled VBAT Supply
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// <0x1E=>CTAT Output
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// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
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// <id> adc_pinmux_positive
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#ifndef CONF_ADC_0_MUXPOS
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#define CONF_ADC_0_MUXPOS 0x0
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#endif
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// <o> Negative Mux Input Selection
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// <0x00=>ADC AIN0 pin
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// <0x01=>ADC AIN1 pin
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// <0x02=>ADC AIN2 pin
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// <0x03=>ADC AIN3 pin
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// <0x04=>ADC AIN4 pin
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// <0x05=>ADC AIN5 pin
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// <0x06=>ADC AIN6 pin
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// <0x07=>ADC AIN7 pin
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// <0x18=>Internal ground
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// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
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// <id> adc_pinmux_negative
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#ifndef CONF_ADC_0_MUXNEG
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#define CONF_ADC_0_MUXNEG 0x0
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#endif
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// </h>
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// <e> Advanced Configuration
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// <id> adc_advanced_settings
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#ifndef CONF_ADC_0_ADVANCED
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#define CONF_ADC_0_ADVANCED 0
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#endif
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// <q> Run in standby
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// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
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// <id> adc_arch_runstdby
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#ifndef CONF_ADC_0_RUNSTDBY
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#define CONF_ADC_0_RUNSTDBY 0
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#endif
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// <q>Debug Run
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// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
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// <id> adc_arch_dbgrun
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#ifndef CONF_ADC_0_DBGRUN
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#define CONF_ADC_0_DBGRUN 0
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#endif
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// <q> On Demand Control
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// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
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// <id> adc_arch_ondemand
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#ifndef CONF_ADC_0_ONDEMAND
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#define CONF_ADC_0_ONDEMAND 0
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#endif
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// <q> Left-Adjusted Result
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// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
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// <id> adc_arch_leftadj
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#ifndef CONF_ADC_0_LEFTADJ
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#define CONF_ADC_0_LEFTADJ 0
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#endif
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// <q> Reference Buffer Offset Compensation Enable
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// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
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// <id> adc_arch_refcomp
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#ifndef CONF_ADC_0_REFCOMP
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#define CONF_ADC_0_REFCOMP 0
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#endif
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// <q>Comparator Offset Compensation Enable
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// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
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// <id> adc_arch_offcomp
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#ifndef CONF_ADC_0_OFFCOMP
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#define CONF_ADC_0_OFFCOMP 0
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#endif
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// <q> Digital Correction Logic Enabled
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// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
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// <id> adc_arch_corren
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#ifndef CONF_ADC_0_CORREN
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#define CONF_ADC_0_CORREN 0
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#endif
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// <o> Offset Correction Value <0-4095>
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// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
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// <id> adc_arch_offsetcorr
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#ifndef CONF_ADC_0_OFFSETCORR
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#define CONF_ADC_0_OFFSETCORR 0
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#endif
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// <o> Gain Correction Value <0-4095>
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// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
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// <id> adc_arch_gaincorr
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#ifndef CONF_ADC_0_GAINCORR
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#define CONF_ADC_0_GAINCORR 0
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#endif
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// <o> Adjusting Result / Division Coefficient <0-7>
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// <i> These bits define the division coefficient in 2n steps. (ADJRES)
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// <id> adc_arch_adjres
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#ifndef CONF_ADC_0_ADJRES
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#define CONF_ADC_0_ADJRES 0x0
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#endif
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// <o.0..10> Number of Samples to be Collected
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// <0x0=>1 sample
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// <0x1=>2 samples
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// <0x2=>4 samples
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// <0x3=>8 samples
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// <0x4=>16 samples
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// <0x5=>32 samples
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// <0x6=>64 samples
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// <0x7=>128 samples
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// <0x8=>256 samples
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// <0x9=>512 samples
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// <0xA=>1024 samples
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// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
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// <id> adc_arch_samplenum
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#ifndef CONF_ADC_0_SAMPLENUM
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#define CONF_ADC_0_SAMPLENUM 0x0
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#endif
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// <o> Sampling Time Length <0-63>
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// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
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// <id> adc_arch_samplen
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#ifndef CONF_ADC_0_SAMPLEN
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#define CONF_ADC_0_SAMPLEN 0
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#endif
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// <o> Window Monitor Mode
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// <0x0=>No window mode
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// <0x1=>Mode 1: RESULT above lower threshold
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// <0x2=>Mode 2: RESULT beneath upper threshold
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// <0x3=>Mode 3: RESULT inside lower and upper threshold
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// <0x4=>Mode 4: RESULT outside lower and upper threshold
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// <i> These bits enable and define the window monitor mode. (WINMODE)
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// <id> adc_arch_winmode
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#ifndef CONF_ADC_0_WINMODE
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#define CONF_ADC_0_WINMODE 0x0
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#endif
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// <o> Window Monitor Lower Threshold <0-65535>
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// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
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// <id> adc_arch_winlt
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#ifndef CONF_ADC_0_WINLT
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#define CONF_ADC_0_WINLT 0
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#endif
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// <o> Window Monitor Upper Threshold <0-65535>
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// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
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// <id> adc_arch_winut
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#ifndef CONF_ADC_0_WINUT
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#define CONF_ADC_0_WINUT 0
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#endif
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// <o> Bitmask for positive input sequence <0-4294967295>
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// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
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// <id> adc_arch_seqen
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#ifndef CONF_ADC_0_SEQEN
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#define CONF_ADC_0_SEQEN 0x0
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#endif
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// </e>
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||||
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// <e> Event Control
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// <id> adc_arch_event_settings
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#ifndef CONF_ADC_0_EVENT_CONTROL
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#define CONF_ADC_0_EVENT_CONTROL 0
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#endif
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// <q> Window Monitor Event Out
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// <i> Enables event output on window event (WINMONEO)
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// <id> adc_arch_winmoneo
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#ifndef CONF_ADC_0_WINMONEO
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#define CONF_ADC_0_WINMONEO 0
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#endif
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||||
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||||
// <q> Result Ready Event Out
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// <i> Enables event output on result ready event (RESRDEO)
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// <id> adc_arch_resrdyeo
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#ifndef CONF_ADC_0_RESRDYEO
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#define CONF_ADC_0_RESRDYEO 0
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#endif
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||||
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||||
// <q> Invert flush Event Signal
|
||||
// <i> Invert the flush event input signal (FLUSHINV)
|
||||
// <id> adc_arch_flushinv
|
||||
#ifndef CONF_ADC_0_FLUSHINV
|
||||
#define CONF_ADC_0_FLUSHINV 0
|
||||
#endif
|
||||
|
||||
// <q> Trigger Flush On Event
|
||||
// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
|
||||
// <id> adc_arch_flushei
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#ifndef CONF_ADC_0_FLUSHEI
|
||||
#define CONF_ADC_0_FLUSHEI 0
|
||||
#endif
|
||||
|
||||
// <q> Invert Start Conversion Event Signal
|
||||
// <i> Invert the start conversion event input signal (STARTINV)
|
||||
// <id> adc_arch_startinv
|
||||
#ifndef CONF_ADC_0_STARTINV
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||||
#define CONF_ADC_0_STARTINV 0
|
||||
#endif
|
||||
|
||||
// <q> Trigger Conversion On Event
|
||||
// <i> Trigger a conversion on event. (STARTEI)
|
||||
// <id> adc_arch_startei
|
||||
#ifndef CONF_ADC_0_STARTEI
|
||||
#define CONF_ADC_0_STARTEI 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_ADC_CONFIG_H
|
||||
3122
Smol Watch Project/My Project/Config/hpl_dmac_config.h
Normal file
3122
Smol Watch Project/My Project/Config/hpl_dmac_config.h
Normal file
File diff suppressed because it is too large
Load Diff
730
Smol Watch Project/My Project/Config/hpl_eic_config.h
Normal file
730
Smol Watch Project/My Project/Config/hpl_eic_config.h
Normal file
@@ -0,0 +1,730 @@
|
||||
/* Auto-generated config file hpl_eic_config.h */
|
||||
#ifndef HPL_EIC_CONFIG_H
|
||||
#define HPL_EIC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Basic Settings
|
||||
// <o> Clock Selection
|
||||
// <i> Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or
|
||||
// <i> either by CLK_ULP32K when power consumption is the priority.
|
||||
// <0x0=> Clocked by GCLK
|
||||
// <0x1=> Clocked by ULPOSC32K
|
||||
// <id> eic_arch_cksel
|
||||
#ifndef CONF_EIC_CKSEL
|
||||
#define CONF_EIC_CKSEL 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Non-Maskable Interrupt Control
|
||||
// <id> eic_arch_nmi_ctrl
|
||||
#ifndef CONF_EIC_ENABLE_NMI_CTRL
|
||||
#define CONF_EIC_ENABLE_NMI_CTRL 0
|
||||
#endif
|
||||
|
||||
// <q> Non-Maskable Interrupt Filter Enable
|
||||
// <i> Indicates whether the mon-maskable interrupt filter is enabled or not
|
||||
// <id> eic_arch_nmifilten
|
||||
#ifndef CONF_EIC_NMIFILTEN
|
||||
#define CONF_EIC_NMIFILTEN 0
|
||||
#endif
|
||||
|
||||
// <y> Non-Maskable Interrupt Sense
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines non-maskable interrupt sense
|
||||
// <id> eic_arch_nmisense
|
||||
#ifndef CONF_EIC_NMISENSE
|
||||
#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the interrupt detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_nmiasynch
|
||||
#ifndef CONF_EIC_NMIASYNCH
|
||||
#define CONF_EIC_NMIASYNCH 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 0 Settings
|
||||
// <id> eic_arch_enable_irq_setting0
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING0 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 0 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 0 filter is enabled or not
|
||||
// <id> eic_arch_filten0
|
||||
#ifndef CONF_EIC_FILTEN0
|
||||
#define CONF_EIC_FILTEN0 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 0 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 0 event output is enabled or not
|
||||
// <id> eic_arch_extinteo0
|
||||
#ifndef CONF_EIC_EXTINTEO0
|
||||
#define CONF_EIC_EXTINTEO0 0
|
||||
#endif
|
||||
|
||||
// <y> Input 0 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense0
|
||||
#ifndef CONF_EIC_SENSE0
|
||||
#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 0 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch0
|
||||
#ifndef CONF_EIC_ASYNCH0
|
||||
#define CONF_EIC_ASYNCH0 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 1 Settings
|
||||
// <id> eic_arch_enable_irq_setting1
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING1 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 1 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 1 filter is enabled or not
|
||||
// <id> eic_arch_filten1
|
||||
#ifndef CONF_EIC_FILTEN1
|
||||
#define CONF_EIC_FILTEN1 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 1 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 1 event output is enabled or not
|
||||
// <id> eic_arch_extinteo1
|
||||
#ifndef CONF_EIC_EXTINTEO1
|
||||
#define CONF_EIC_EXTINTEO1 0
|
||||
#endif
|
||||
|
||||
// <y> Input 1 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense1
|
||||
#ifndef CONF_EIC_SENSE1
|
||||
#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 1 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch1
|
||||
#ifndef CONF_EIC_ASYNCH1
|
||||
#define CONF_EIC_ASYNCH1 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 2 Settings
|
||||
// <id> eic_arch_enable_irq_setting2
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING2 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 2 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 2 filter is enabled or not
|
||||
// <id> eic_arch_filten2
|
||||
#ifndef CONF_EIC_FILTEN2
|
||||
#define CONF_EIC_FILTEN2 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 2 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 2 event output is enabled or not
|
||||
// <id> eic_arch_extinteo2
|
||||
#ifndef CONF_EIC_EXTINTEO2
|
||||
#define CONF_EIC_EXTINTEO2 0
|
||||
#endif
|
||||
|
||||
// <y> Input 2 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense2
|
||||
#ifndef CONF_EIC_SENSE2
|
||||
#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 2 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch2
|
||||
#ifndef CONF_EIC_ASYNCH2
|
||||
#define CONF_EIC_ASYNCH2 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 3 Settings
|
||||
// <id> eic_arch_enable_irq_setting3
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING3 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 3 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 3 filter is enabled or not
|
||||
// <id> eic_arch_filten3
|
||||
#ifndef CONF_EIC_FILTEN3
|
||||
#define CONF_EIC_FILTEN3 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 3 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 3 event output is enabled or not
|
||||
// <id> eic_arch_extinteo3
|
||||
#ifndef CONF_EIC_EXTINTEO3
|
||||
#define CONF_EIC_EXTINTEO3 0
|
||||
#endif
|
||||
|
||||
// <y> Input 3 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense3
|
||||
#ifndef CONF_EIC_SENSE3
|
||||
#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 3 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch3
|
||||
#ifndef CONF_EIC_ASYNCH3
|
||||
#define CONF_EIC_ASYNCH3 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 4 Settings
|
||||
// <id> eic_arch_enable_irq_setting4
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING4 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 4 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 4 filter is enabled or not
|
||||
// <id> eic_arch_filten4
|
||||
#ifndef CONF_EIC_FILTEN4
|
||||
#define CONF_EIC_FILTEN4 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 4 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 4 event output is enabled or not
|
||||
// <id> eic_arch_extinteo4
|
||||
#ifndef CONF_EIC_EXTINTEO4
|
||||
#define CONF_EIC_EXTINTEO4 0
|
||||
#endif
|
||||
|
||||
// <y> Input 4 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense4
|
||||
#ifndef CONF_EIC_SENSE4
|
||||
#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 4 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch4
|
||||
#ifndef CONF_EIC_ASYNCH4
|
||||
#define CONF_EIC_ASYNCH4 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 5 Settings
|
||||
// <id> eic_arch_enable_irq_setting5
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING5 1
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 5 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 5 filter is enabled or not
|
||||
// <id> eic_arch_filten5
|
||||
#ifndef CONF_EIC_FILTEN5
|
||||
#define CONF_EIC_FILTEN5 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 5 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 5 event output is enabled or not
|
||||
// <id> eic_arch_extinteo5
|
||||
#ifndef CONF_EIC_EXTINTEO5
|
||||
#define CONF_EIC_EXTINTEO5 0
|
||||
#endif
|
||||
|
||||
// <y> Input 5 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense5
|
||||
#ifndef CONF_EIC_SENSE5
|
||||
#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_RISE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 5 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch5
|
||||
#ifndef CONF_EIC_ASYNCH5
|
||||
#define CONF_EIC_ASYNCH5 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 6 Settings
|
||||
// <id> eic_arch_enable_irq_setting6
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING6 1
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 6 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 6 filter is enabled or not
|
||||
// <id> eic_arch_filten6
|
||||
#ifndef CONF_EIC_FILTEN6
|
||||
#define CONF_EIC_FILTEN6 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 6 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 6 event output is enabled or not
|
||||
// <id> eic_arch_extinteo6
|
||||
#ifndef CONF_EIC_EXTINTEO6
|
||||
#define CONF_EIC_EXTINTEO6 0
|
||||
#endif
|
||||
|
||||
// <y> Input 6 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense6
|
||||
#ifndef CONF_EIC_SENSE6
|
||||
#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_RISE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 6 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch6
|
||||
#ifndef CONF_EIC_ASYNCH6
|
||||
#define CONF_EIC_ASYNCH6 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 7 Settings
|
||||
// <id> eic_arch_enable_irq_setting7
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING7 1
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 7 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 7 filter is enabled or not
|
||||
// <id> eic_arch_filten7
|
||||
#ifndef CONF_EIC_FILTEN7
|
||||
#define CONF_EIC_FILTEN7 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 7 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 7 event output is enabled or not
|
||||
// <id> eic_arch_extinteo7
|
||||
#ifndef CONF_EIC_EXTINTEO7
|
||||
#define CONF_EIC_EXTINTEO7 0
|
||||
#endif
|
||||
|
||||
// <y> Input 7 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense7
|
||||
#ifndef CONF_EIC_SENSE7
|
||||
#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_RISE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 7 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch7
|
||||
#ifndef CONF_EIC_ASYNCH7
|
||||
#define CONF_EIC_ASYNCH7 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 8 Settings
|
||||
// <id> eic_arch_enable_irq_setting8
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING8
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING8 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 8 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 8 filter is enabled or not
|
||||
// <id> eic_arch_filten8
|
||||
#ifndef CONF_EIC_FILTEN8
|
||||
#define CONF_EIC_FILTEN8 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 8 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 8 event output is enabled or not
|
||||
// <id> eic_arch_extinteo8
|
||||
#ifndef CONF_EIC_EXTINTEO8
|
||||
#define CONF_EIC_EXTINTEO8 0
|
||||
#endif
|
||||
|
||||
// <y> Input 8 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense8
|
||||
#ifndef CONF_EIC_SENSE8
|
||||
#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 8 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch8
|
||||
#ifndef CONF_EIC_ASYNCH8
|
||||
#define CONF_EIC_ASYNCH8 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 9 Settings
|
||||
// <id> eic_arch_enable_irq_setting9
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING9
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING9 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 9 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 9 filter is enabled or not
|
||||
// <id> eic_arch_filten9
|
||||
#ifndef CONF_EIC_FILTEN9
|
||||
#define CONF_EIC_FILTEN9 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 9 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 9 event output is enabled or not
|
||||
// <id> eic_arch_extinteo9
|
||||
#ifndef CONF_EIC_EXTINTEO9
|
||||
#define CONF_EIC_EXTINTEO9 0
|
||||
#endif
|
||||
|
||||
// <y> Input 9 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense9
|
||||
#ifndef CONF_EIC_SENSE9
|
||||
#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 9 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch9
|
||||
#ifndef CONF_EIC_ASYNCH9
|
||||
#define CONF_EIC_ASYNCH9 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 10 Settings
|
||||
// <id> eic_arch_enable_irq_setting10
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING10
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING10 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 10 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 10 filter is enabled or not
|
||||
// <id> eic_arch_filten10
|
||||
#ifndef CONF_EIC_FILTEN10
|
||||
#define CONF_EIC_FILTEN10 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 10 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 10 event output is enabled or not
|
||||
// <id> eic_arch_extinteo10
|
||||
#ifndef CONF_EIC_EXTINTEO10
|
||||
#define CONF_EIC_EXTINTEO10 0
|
||||
#endif
|
||||
|
||||
// <y> Input 10 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense10
|
||||
#ifndef CONF_EIC_SENSE10
|
||||
#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 10 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch10
|
||||
#ifndef CONF_EIC_ASYNCH10
|
||||
#define CONF_EIC_ASYNCH10 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 11 Settings
|
||||
// <id> eic_arch_enable_irq_setting11
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING11
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING11 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 11 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 11 filter is enabled or not
|
||||
// <id> eic_arch_filten11
|
||||
#ifndef CONF_EIC_FILTEN11
|
||||
#define CONF_EIC_FILTEN11 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 11 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 11 event output is enabled or not
|
||||
// <id> eic_arch_extinteo11
|
||||
#ifndef CONF_EIC_EXTINTEO11
|
||||
#define CONF_EIC_EXTINTEO11 0
|
||||
#endif
|
||||
|
||||
// <y> Input 11 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense11
|
||||
#ifndef CONF_EIC_SENSE11
|
||||
#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 11 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch11
|
||||
#ifndef CONF_EIC_ASYNCH11
|
||||
#define CONF_EIC_ASYNCH11 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 12 Settings
|
||||
// <id> eic_arch_enable_irq_setting12
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING12
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING12 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 12 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 12 filter is enabled or not
|
||||
// <id> eic_arch_filten12
|
||||
#ifndef CONF_EIC_FILTEN12
|
||||
#define CONF_EIC_FILTEN12 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 12 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 12 event output is enabled or not
|
||||
// <id> eic_arch_extinteo12
|
||||
#ifndef CONF_EIC_EXTINTEO12
|
||||
#define CONF_EIC_EXTINTEO12 0
|
||||
#endif
|
||||
|
||||
// <y> Input 12 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense12
|
||||
#ifndef CONF_EIC_SENSE12
|
||||
#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 12 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch12
|
||||
#ifndef CONF_EIC_ASYNCH12
|
||||
#define CONF_EIC_ASYNCH12 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 13 Settings
|
||||
// <id> eic_arch_enable_irq_setting13
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING13
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING13 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 13 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 13 filter is enabled or not
|
||||
// <id> eic_arch_filten13
|
||||
#ifndef CONF_EIC_FILTEN13
|
||||
#define CONF_EIC_FILTEN13 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 13 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 13 event output is enabled or not
|
||||
// <id> eic_arch_extinteo13
|
||||
#ifndef CONF_EIC_EXTINTEO13
|
||||
#define CONF_EIC_EXTINTEO13 0
|
||||
#endif
|
||||
|
||||
// <y> Input 13 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense13
|
||||
#ifndef CONF_EIC_SENSE13
|
||||
#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 13 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch13
|
||||
#ifndef CONF_EIC_ASYNCH13
|
||||
#define CONF_EIC_ASYNCH13 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 14 Settings
|
||||
// <id> eic_arch_enable_irq_setting14
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING14
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING14 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 14 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 14 filter is enabled or not
|
||||
// <id> eic_arch_filten14
|
||||
#ifndef CONF_EIC_FILTEN14
|
||||
#define CONF_EIC_FILTEN14 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 14 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 14 event output is enabled or not
|
||||
// <id> eic_arch_extinteo14
|
||||
#ifndef CONF_EIC_EXTINTEO14
|
||||
#define CONF_EIC_EXTINTEO14 0
|
||||
#endif
|
||||
|
||||
// <y> Input 14 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense14
|
||||
#ifndef CONF_EIC_SENSE14
|
||||
#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 14 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch14
|
||||
#ifndef CONF_EIC_ASYNCH14
|
||||
#define CONF_EIC_ASYNCH14 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Interrupt 15 Settings
|
||||
// <id> eic_arch_enable_irq_setting15
|
||||
#ifndef CONF_EIC_ENABLE_IRQ_SETTING15
|
||||
#define CONF_EIC_ENABLE_IRQ_SETTING15 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 15 Filter Enable
|
||||
// <i> Indicates whether the external interrupt 15 filter is enabled or not
|
||||
// <id> eic_arch_filten15
|
||||
#ifndef CONF_EIC_FILTEN15
|
||||
#define CONF_EIC_FILTEN15 0
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 15 Event Output Enable
|
||||
// <i> Indicates whether the external interrupt 15 event output is enabled or not
|
||||
// <id> eic_arch_extinteo15
|
||||
#ifndef CONF_EIC_EXTINTEO15
|
||||
#define CONF_EIC_EXTINTEO15 0
|
||||
#endif
|
||||
|
||||
// <y> Input 15 Sense Configuration
|
||||
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
|
||||
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
|
||||
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
|
||||
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
|
||||
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
|
||||
// <i> This defines input sense trigger
|
||||
// <id> eic_arch_sense15
|
||||
#ifndef CONF_EIC_SENSE15
|
||||
#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val
|
||||
#endif
|
||||
|
||||
// <q> External Interrupt 15 Asynchronous Edge Detection Mode
|
||||
// <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
|
||||
// <id> eic_arch_asynch15
|
||||
#ifndef CONF_EIC_ASYNCH15
|
||||
#define CONF_EIC_ASYNCH15 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
#define CONFIG_EIC_EXTINT_MAP {5, PIN_PB05}, {6, PIN_PA22}, {7, PIN_PA23},
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_EIC_CONFIG_H
|
||||
383
Smol Watch Project/My Project/Config/hpl_gclk_config.h
Normal file
383
Smol Watch Project/My Project/Config/hpl_gclk_config.h
Normal file
@@ -0,0 +1,383 @@
|
||||
/* Auto-generated config file hpl_gclk_config.h */
|
||||
#ifndef HPL_GCLK_CONFIG_H
|
||||
#define HPL_GCLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> Generic clock generator 0 configuration
|
||||
// <i> Indicates whether generic clock 0 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_0
|
||||
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_0_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 0 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
|
||||
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
||||
// <i> This defines the clock source for generic clock generator 0
|
||||
// <id> gclk_gen_0_oscillator
|
||||
#ifndef CONF_GCLK_GEN_0_SOURCE
|
||||
#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_0_runstdby
|
||||
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_0_div_sel
|
||||
#ifndef CONF_GCLK_GEN_0_DIVSEL
|
||||
#define CONF_GCLK_GEN_0_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_0_oe
|
||||
#ifndef CONF_GCLK_GEN_0_OE
|
||||
#define CONF_GCLK_GEN_0_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_0_oov
|
||||
#ifndef CONF_GCLK_GEN_0_OOV
|
||||
#define CONF_GCLK_GEN_0_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_0_idc
|
||||
#ifndef CONF_GCLK_GEN_0_IDC
|
||||
#define CONF_GCLK_GEN_0_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_0_enable
|
||||
#ifndef CONF_GCLK_GEN_0_GENEN
|
||||
#define CONF_GCLK_GEN_0_GENEN 1
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_0_div
|
||||
#ifndef CONF_GCLK_GEN_0_DIV
|
||||
#define CONF_GCLK_GEN_0_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 1 configuration
|
||||
// <i> Indicates whether generic clock 1 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_1
|
||||
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_1_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 1 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
|
||||
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
||||
// <i> This defines the clock source for generic clock generator 1
|
||||
// <id> gclk_gen_1_oscillator
|
||||
#ifndef CONF_GCLK_GEN_1_SOURCE
|
||||
#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_1_runstdby
|
||||
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_1_div_sel
|
||||
#ifndef CONF_GCLK_GEN_1_DIVSEL
|
||||
#define CONF_GCLK_GEN_1_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_1_oe
|
||||
#ifndef CONF_GCLK_GEN_1_OE
|
||||
#define CONF_GCLK_GEN_1_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_1_oov
|
||||
#ifndef CONF_GCLK_GEN_1_OOV
|
||||
#define CONF_GCLK_GEN_1_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_1_idc
|
||||
#ifndef CONF_GCLK_GEN_1_IDC
|
||||
#define CONF_GCLK_GEN_1_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_1_enable
|
||||
#ifndef CONF_GCLK_GEN_1_GENEN
|
||||
#define CONF_GCLK_GEN_1_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_1_div
|
||||
#ifndef CONF_GCLK_GEN_1_DIV
|
||||
#define CONF_GCLK_GEN_1_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 2 configuration
|
||||
// <i> Indicates whether generic clock 2 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_2
|
||||
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_2_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 2 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
|
||||
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
||||
// <i> This defines the clock source for generic clock generator 2
|
||||
// <id> gclk_gen_2_oscillator
|
||||
#ifndef CONF_GCLK_GEN_2_SOURCE
|
||||
#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_2_runstdby
|
||||
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_2_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_2_div_sel
|
||||
#ifndef CONF_GCLK_GEN_2_DIVSEL
|
||||
#define CONF_GCLK_GEN_2_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_2_oe
|
||||
#ifndef CONF_GCLK_GEN_2_OE
|
||||
#define CONF_GCLK_GEN_2_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_2_oov
|
||||
#ifndef CONF_GCLK_GEN_2_OOV
|
||||
#define CONF_GCLK_GEN_2_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_2_idc
|
||||
#ifndef CONF_GCLK_GEN_2_IDC
|
||||
#define CONF_GCLK_GEN_2_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_2_enable
|
||||
#ifndef CONF_GCLK_GEN_2_GENEN
|
||||
#define CONF_GCLK_GEN_2_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_2_div
|
||||
#ifndef CONF_GCLK_GEN_2_DIV
|
||||
#define CONF_GCLK_GEN_2_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 3 configuration
|
||||
// <i> Indicates whether generic clock 3 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_3
|
||||
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_3_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 3 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
|
||||
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
||||
// <i> This defines the clock source for generic clock generator 3
|
||||
// <id> gclk_gen_3_oscillator
|
||||
#ifndef CONF_GCLK_GEN_3_SOURCE
|
||||
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_3_runstdby
|
||||
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_3_RUNSTDBY 1
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_3_div_sel
|
||||
#ifndef CONF_GCLK_GEN_3_DIVSEL
|
||||
#define CONF_GCLK_GEN_3_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_3_oe
|
||||
#ifndef CONF_GCLK_GEN_3_OE
|
||||
#define CONF_GCLK_GEN_3_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_3_oov
|
||||
#ifndef CONF_GCLK_GEN_3_OOV
|
||||
#define CONF_GCLK_GEN_3_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_3_idc
|
||||
#ifndef CONF_GCLK_GEN_3_IDC
|
||||
#define CONF_GCLK_GEN_3_IDC 1
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_3_enable
|
||||
#ifndef CONF_GCLK_GEN_3_GENEN
|
||||
#define CONF_GCLK_GEN_3_GENEN 1
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_3_div
|
||||
#ifndef CONF_GCLK_GEN_3_DIV
|
||||
#define CONF_GCLK_GEN_3_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 4 configuration
|
||||
// <i> Indicates whether generic clock 4 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_4
|
||||
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_4_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 4 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
|
||||
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
||||
// <i> This defines the clock source for generic clock generator 4
|
||||
// <id> gclk_gen_4_oscillator
|
||||
#ifndef CONF_GCLK_GEN_4_SOURCE
|
||||
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_4_runstdby
|
||||
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_4_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_4_div_sel
|
||||
#ifndef CONF_GCLK_GEN_4_DIVSEL
|
||||
#define CONF_GCLK_GEN_4_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_4_oe
|
||||
#ifndef CONF_GCLK_GEN_4_OE
|
||||
#define CONF_GCLK_GEN_4_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_4_oov
|
||||
#ifndef CONF_GCLK_GEN_4_OOV
|
||||
#define CONF_GCLK_GEN_4_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_4_idc
|
||||
#ifndef CONF_GCLK_GEN_4_IDC
|
||||
#define CONF_GCLK_GEN_4_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_4_enable
|
||||
#ifndef CONF_GCLK_GEN_4_GENEN
|
||||
#define CONF_GCLK_GEN_4_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_4_div
|
||||
#ifndef CONF_GCLK_GEN_4_DIV
|
||||
#define CONF_GCLK_GEN_4_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_GCLK_CONFIG_H
|
||||
85
Smol Watch Project/My Project/Config/hpl_mclk_config.h
Normal file
85
Smol Watch Project/My Project/Config/hpl_mclk_config.h
Normal file
@@ -0,0 +1,85 @@
|
||||
/* Auto-generated config file hpl_mclk_config.h */
|
||||
#ifndef HPL_MCLK_CONFIG_H
|
||||
#define HPL_MCLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// <e> System Configuration
|
||||
// <i> Indicates whether configuration for system is enabled or not
|
||||
// <id> enable_cpu_clock
|
||||
#ifndef CONF_SYSTEM_CONFIG
|
||||
#define CONF_SYSTEM_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Basic settings
|
||||
// <y> CPU Clock source
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <i> This defines the clock source for the CPU
|
||||
// <id> cpu_clock_source
|
||||
#ifndef CONF_CPU_SRC
|
||||
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> CPU Clock Division Factor
|
||||
// <MCLK_CPUDIV_CPUDIV_DIV1_Val"> 1
|
||||
// <MCLK_CPUDIV_CPUDIV_DIV2_Val"> 2
|
||||
// <MCLK_CPUDIV_CPUDIV_DIV4_Val"> 4
|
||||
// <MCLK_CPUDIV_CPUDIV_DIV8_Val"> 8
|
||||
// <MCLK_CPUDIV_CPUDIV_DIV16_Val"> 16
|
||||
// <MCLK_CPUDIV_CPUDIV_DIV32_Val"> 32
|
||||
// <MCLK_CPUDIV_CPUDIV_DIV64_Val"> 64
|
||||
// <MCLK_CPUDIV_CPUDIV_DIV128_Val"> 128
|
||||
// <i> Prescalar for CPU clock
|
||||
// <id> cpu_div
|
||||
#ifndef CONF_MCLK_CPUDIV
|
||||
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val
|
||||
#endif
|
||||
|
||||
// <y> Backup Clock Division
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
|
||||
// <id> mclk_arch_bupdiv
|
||||
#ifndef CONF_MCLK_BUPDIV
|
||||
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <h> NVM Settings
|
||||
// <o> NVM Wait States
|
||||
// <i> These bits select the number of wait states for a read operation.
|
||||
// <0=> 0
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
// <10=> 10
|
||||
// <11=> 11
|
||||
// <12=> 12
|
||||
// <13=> 13
|
||||
// <14=> 14
|
||||
// <15=> 15
|
||||
// <id> nvm_wait_states
|
||||
#ifndef CONF_NVM_WAIT_STATE
|
||||
#define CONF_NVM_WAIT_STATE 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_MCLK_CONFIG_H
|
||||
173
Smol Watch Project/My Project/Config/hpl_osc32kctrl_config.h
Normal file
173
Smol Watch Project/My Project/Config/hpl_osc32kctrl_config.h
Normal file
@@ -0,0 +1,173 @@
|
||||
/* Auto-generated config file hpl_osc32kctrl_config.h */
|
||||
#ifndef HPL_OSC32KCTRL_CONFIG_H
|
||||
#define HPL_OSC32KCTRL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> RTC Source configuration
|
||||
// <id> enable_rtc_source
|
||||
#ifndef CONF_RTCCTRL_CONFIG
|
||||
#define CONF_RTCCTRL_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> RTC source control
|
||||
// <y> RTC Clock Source Selection
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <i> This defines the clock source for RTC
|
||||
// <id> rtc_source_oscillator
|
||||
#ifndef CONF_RTCCTRL_SRC
|
||||
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <q> Use 1 kHz output
|
||||
// <id> rtc_1khz_selection
|
||||
#ifndef CONF_RTCCTRL_1KHZ
|
||||
|
||||
#define CONF_RTCCTRL_1KHZ 1
|
||||
|
||||
#endif
|
||||
|
||||
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
|
||||
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
|
||||
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
|
||||
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
|
||||
#else
|
||||
#error unexpected CONF_RTCCTRL_SRC
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
// <e> SLCD Source configuration
|
||||
// <id> enable_slcd_source
|
||||
#ifndef CONF_SLCDCTRL_CONFIG
|
||||
#define CONF_SLCDCTRL_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> SLCD source control
|
||||
// <y> SLCD Clock Source Selection
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <i> This defines the clock source for SLCD
|
||||
// <id> slcd_source_oscillator
|
||||
#ifndef CONF_SLCDCTRL_SRC
|
||||
#define CONF_SLCDCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
// <e> 32kHz External Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for External 32K Osc is enabled or not
|
||||
// <id> enable_xosc32k
|
||||
#ifndef CONF_XOSC32K_CONFIG
|
||||
#define CONF_XOSC32K_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> 32kHz External Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
|
||||
// <id> xosc32k_arch_enable
|
||||
#ifndef CONF_XOSC32K_ENABLE
|
||||
#define CONF_XOSC32K_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>62592us
|
||||
// <0x1=>125092us
|
||||
// <0x2=>500092us
|
||||
// <0x3=>1000092us
|
||||
// <0x4=>2000092us
|
||||
// <0x5=>4000092us
|
||||
// <0x6=>8000092us
|
||||
// <id> xosc32k_arch_startup
|
||||
#ifndef CONF_XOSC32K_STARTUP
|
||||
#define CONF_XOSC32K_STARTUP 0x0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc32k_arch_ondemand
|
||||
#ifndef CONF_XOSC32K_ONDEMAND
|
||||
#define CONF_XOSC32K_ONDEMAND 1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc32k_arch_runstdby
|
||||
#ifndef CONF_XOSC32K_RUNSTDBY
|
||||
#define CONF_XOSC32K_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> 1kHz Output Enable
|
||||
// <i> Indicates whether 1kHz Output is enabled or not
|
||||
// <id> xosc32k_arch_en1k
|
||||
#ifndef CONF_XOSC32K_EN1K
|
||||
#define CONF_XOSC32K_EN1K 1
|
||||
#endif
|
||||
|
||||
// <q> 32kHz Output Enable
|
||||
// <i> Indicates whether 32kHz Output is enabled or not
|
||||
// <id> xosc32k_arch_en32k
|
||||
#ifndef CONF_XOSC32K_EN32K
|
||||
#define CONF_XOSC32K_EN32K 1
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc32k_arch_swben
|
||||
#ifndef CONF_XOSC32K_SWBEN
|
||||
#define CONF_XOSC32K_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc32k_arch_cfden
|
||||
#ifndef CONF_XOSC32K_CFDEN
|
||||
#define CONF_XOSC32K_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector Event Out
|
||||
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
|
||||
// <id> xosc32k_arch_cfdeo
|
||||
#ifndef CONF_XOSC32K_CFDEO
|
||||
#define CONF_XOSC32K_CFDEO 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN32/XOUT32 Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc32k_arch_xtalen
|
||||
#ifndef CONF_XOSC32K_XTALEN
|
||||
#define CONF_XOSC32K_XTALEN 1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for OSCULP32K is enabled or not
|
||||
// <id> enable_osculp32k
|
||||
#ifndef CONF_OSCULP32K_CONFIG
|
||||
#define CONF_OSCULP32K_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> 32kHz Ultra Low Power Internal Oscillator Control
|
||||
|
||||
// <q> Oscillator Calibration Control
|
||||
// <i> Indicates whether Oscillator Calibration is enabled or not
|
||||
// <id> osculp32k_calib_enable
|
||||
#ifndef CONF_OSCULP32K_CALIB_ENABLE
|
||||
#define CONF_OSCULP32K_CALIB_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Oscillator Calibration <0x0-0x1F>
|
||||
// <id> osculp32k_calib
|
||||
#ifndef CONF_OSCULP32K_CALIB
|
||||
#define CONF_OSCULP32K_CALIB 0x0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_OSC32KCTRL_CONFIG_H
|
||||
483
Smol Watch Project/My Project/Config/hpl_oscctrl_config.h
Normal file
483
Smol Watch Project/My Project/Config/hpl_oscctrl_config.h
Normal file
@@ -0,0 +1,483 @@
|
||||
/* Auto-generated config file hpl_oscctrl_config.h */
|
||||
#ifndef HPL_OSCCTRL_CONFIG_H
|
||||
#define HPL_OSCCTRL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for XOSC is enabled or not
|
||||
// <id> enable_xosc
|
||||
#ifndef CONF_XOSC_CONFIG
|
||||
#define CONF_XOSC_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <o> Frequency <400000-32000000>
|
||||
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||
// <id> xosc_frequency
|
||||
#ifndef CONF_XOSC_FREQUENCY
|
||||
#define CONF_XOSC_FREQUENCY 400000
|
||||
#endif
|
||||
|
||||
// <h> External Multipurpose Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
|
||||
// <id> xosc_arch_enable
|
||||
#ifndef CONF_XOSC_ENABLE
|
||||
#define CONF_XOSC_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>31us
|
||||
// <0x1=>61us
|
||||
// <0x2=>122us
|
||||
// <0x3=>244us
|
||||
// <0x4=>488us
|
||||
// <0x5=>977us
|
||||
// <0x6=>1953us
|
||||
// <0x7=>3906us
|
||||
// <0x8=>7813us
|
||||
// <0x9=>15625us
|
||||
// <0xA=>31250us
|
||||
// <0xB=>62500us
|
||||
// <0xC=>125000us
|
||||
// <0xD=>250000us
|
||||
// <0xE=>500000us
|
||||
// <0xF=>1000000us
|
||||
// <id> xosc_arch_startup
|
||||
#ifndef CONF_XOSC_STARTUP
|
||||
#define CONF_XOSC_STARTUP 0x0
|
||||
#endif
|
||||
|
||||
// <q> Automatic Amplitude Gain Control
|
||||
// <i> Indicates whether Automatic Amplitude Gain Control is enabled or not
|
||||
// <id> xosc_arch_ampgc
|
||||
#ifndef CONF_XOSC_AMPGC
|
||||
#define CONF_XOSC_AMPGC 0
|
||||
#endif
|
||||
|
||||
// <o> External Multipurpose Crystal Oscillator Gain
|
||||
// <0x0=>2MHz
|
||||
// <0x1=>4MHz
|
||||
// <0x2=>8MHz
|
||||
// <0x3=>16MHz
|
||||
// <0x4=>30MHz
|
||||
// <id> xosc_arch_gain
|
||||
#ifndef CONF_XOSC_GAIN
|
||||
#define CONF_XOSC_GAIN 0x0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc_arch_ondemand
|
||||
#ifndef CONF_XOSC_ONDEMAND
|
||||
#define CONF_XOSC_ONDEMAND 1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc_arch_runstdby
|
||||
#ifndef CONF_XOSC_RUNSTDBY
|
||||
#define CONF_XOSC_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc_arch_swben
|
||||
#ifndef CONF_XOSC_SWBEN
|
||||
#define CONF_XOSC_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc_arch_cfden
|
||||
#ifndef CONF_XOSC_CFDEN
|
||||
#define CONF_XOSC_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector Event Out
|
||||
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
|
||||
// <id> xosc_arch_cfdeo
|
||||
#ifndef CONF_XOSC_CFDEO
|
||||
#define CONF_XOSC_CFDEO 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN/XOUT Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc_arch_xtalen
|
||||
#ifndef CONF_XOSC_XTALEN
|
||||
#define CONF_XOSC_XTALEN 0
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
// <e> 16MHz Internal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for OSC8M is enabled or not
|
||||
// <id> enable_osc16m
|
||||
#ifndef CONF_OSC16M_CONFIG
|
||||
#define CONF_OSC16M_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> 16MHz Internal Oscillator Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether 16MHz Internal Oscillator is enabled or not
|
||||
// <id> osc16m_arch_enable
|
||||
#ifndef CONF_OSC16M_ENABLE
|
||||
#define CONF_OSC16M_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> osc16m_arch_ondemand
|
||||
#ifndef CONF_OSC16M_ONDEMAND
|
||||
#define CONF_OSC16M_ONDEMAND 1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> osc16m_arch_runstdby
|
||||
#ifndef CONF_OSC16M_RUNSTDBY
|
||||
#define CONF_OSC16M_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <y> Oscillator Frequency Selection(Mhz)
|
||||
// <OSCCTRL_OSC16MCTRL_FSEL_4_Val"> 4
|
||||
// <OSCCTRL_OSC16MCTRL_FSEL_8_Val"> 8
|
||||
// <OSCCTRL_OSC16MCTRL_FSEL_12_Val"> 12
|
||||
// <OSCCTRL_OSC16MCTRL_FSEL_16_Val"> 16
|
||||
// <i> This defines the oscillator frequency (Mhz)
|
||||
// <id> osc16m_freq
|
||||
#ifndef CONF_OSC16M_FSEL
|
||||
#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val
|
||||
#endif
|
||||
|
||||
// <q> Oscillator Calibration Control
|
||||
// <i> Indicates whether Oscillator Calibration is enabled or not
|
||||
// <id> osc16m_arch_calib_enable
|
||||
#ifndef CONF_OSC16M_CALIB_ENABLE
|
||||
#define CONF_OSC16M_CALIB_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> 4MHz Frequency Calibration <0x0-0x3F>
|
||||
// <id> osc16m_arch_4m_fcal
|
||||
#ifndef CONF_OSC16M_FCAL
|
||||
#define CONF_OSC16M_4M_FCAL 0
|
||||
#endif
|
||||
|
||||
// <o> 4MHz Temperature Calibration <0x0-0x3F>
|
||||
// <id> osc16m_arch_4m_tcal
|
||||
#ifndef CONF_OSC16M_TCAL
|
||||
#define CONF_OSC16M_4M_TCAL 0
|
||||
#endif
|
||||
|
||||
// <o> 8MHz Frequency Calibration <0x0-0x3F>
|
||||
// <id> osc16m_arch_8m_fcal
|
||||
#ifndef CONF_OSC16M_FCAL
|
||||
#define CONF_OSC16M_8M_FCAL 0
|
||||
#endif
|
||||
|
||||
// <o> 8MHz Temperature Calibration <0x0-0x3F>
|
||||
// <id> osc16m_arch_8m_tcal
|
||||
#ifndef CONF_OSC16M_TCAL
|
||||
#define CONF_OSC16M_8M_TCAL 0
|
||||
#endif
|
||||
|
||||
// <o> 12MHz Frequency Calibration <0x0-0x3F>
|
||||
// <id> osc16m_arch_12m_fcal
|
||||
#ifndef CONF_OSC16M_FCAL
|
||||
#define CONF_OSC16M_12M_FCAL 0
|
||||
#endif
|
||||
|
||||
// <o> 12MHz Temperature Calibration <0x0-0x3F>
|
||||
// <id> osc16m_arch_12m_tcal
|
||||
#ifndef CONF_OSC16M_TCAL
|
||||
#define CONF_OSC16M_12M_TCAL 0
|
||||
#endif
|
||||
|
||||
// <o> 16MHz Frequency Calibration <0x0-0x3F>
|
||||
// <id> osc16m_arch_fcal
|
||||
#ifndef CONF_OSC16M_FCAL
|
||||
#define CONF_OSC16M_16M_FCAL 0
|
||||
#endif
|
||||
|
||||
// <o> 16MHz Temperature Calibration <0x0-0x3F>
|
||||
// <id> osc16m_arch_16m_tcal
|
||||
#ifndef CONF_OSC16M_TCAL
|
||||
#define CONF_OSC16M_16M_TCAL 0
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
// <e> DFLL Configuration
|
||||
// <i> Indicates whether configuration for DFLL is enabled or not
|
||||
// <id> enable_dfll48m
|
||||
#ifndef CONF_DFLL_CONFIG
|
||||
#define CONF_DFLL_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <i> Select the clock source.
|
||||
// <id> dfll48m_ref_clock
|
||||
#ifndef CONF_DFLL_GCLK
|
||||
#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
// <h> Digital Frequency Locked Loop Control
|
||||
// <q> DFLL Enable
|
||||
// <i> Indicates whether DFLL is enabled or not
|
||||
// <id> dfll48m_arch_enable
|
||||
#ifndef CONF_DFLL_ENABLE
|
||||
#define CONF_DFLL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> Wait Lock
|
||||
// <i> Indicates whether Wait Lock is enabled or not
|
||||
// <id> dfll_arch_waitlock
|
||||
#ifndef CONF_DFLL_WAITLOCK
|
||||
#define CONF_DFLL_WAITLOCK 0
|
||||
#endif
|
||||
|
||||
// <q> Bypass Coarse Lock
|
||||
// <i> Indicates whether Bypass Coarse Lock is enabled or not
|
||||
// <id> dfll_arch_bplckc
|
||||
#ifndef CONF_DFLL_BPLCKC
|
||||
#define CONF_DFLL_BPLCKC 0
|
||||
#endif
|
||||
|
||||
// <q> Quick Lock Disable
|
||||
// <i> Indicates whether Quick Lock Disable is enabled or not
|
||||
// <id> dfll_arch_qldis
|
||||
#ifndef CONF_DFLL_QLDIS
|
||||
#define CONF_DFLL_QLDIS 0
|
||||
#endif
|
||||
|
||||
// <q> Chill Cycle Disable
|
||||
// <i> Indicates whether Chill Cycle Disable is enabled or not
|
||||
// <id> dfll_arch_ccdis
|
||||
#ifndef CONF_DFLL_CCDIS
|
||||
#define CONF_DFLL_CCDIS 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> dfll_arch_ondemand
|
||||
#ifndef CONF_DFLL_ONDEMAND
|
||||
#define CONF_DFLL_ONDEMAND 1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> dfll_arch_runstdby
|
||||
#ifndef CONF_DFLL_RUNSTDBY
|
||||
#define CONF_DFLL_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> USB Clock Recovery Mode
|
||||
// <i> Indicates whether USB Clock Recovery Mode is enabled or not
|
||||
// <id> dfll_arch_usbcrm
|
||||
#ifndef CONF_DFLL_USBCRM
|
||||
#define CONF_DFLL_USBCRM 0
|
||||
#endif
|
||||
|
||||
// <q> Lose Lock After Wake
|
||||
// <i> Indicates whether Lose Lock After Wake is enabled or not
|
||||
// <id> dfll_arch_llaw
|
||||
#ifndef CONF_DFLL_LLAW
|
||||
#define CONF_DFLL_LLAW 0
|
||||
#endif
|
||||
|
||||
// <q> Stable DFLL Frequency
|
||||
// <i> Indicates whether Stable DFLL Frequency is enabled or not
|
||||
// <id> dfll_arch_stable
|
||||
#ifndef CONF_DFLL_STABLE
|
||||
#define CONF_DFLL_STABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Operating Mode Selection
|
||||
// <0=>Open Loop Mode
|
||||
// <1=>Closed Loop Mode
|
||||
// <id> dfll48m_mode
|
||||
#ifndef CONF_DFLL_MODE
|
||||
#define CONF_DFLL_MODE 0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Maximum Step <0x0-0x1F>
|
||||
// <id> dfll_arch_cstep
|
||||
#ifndef CONF_DFLL_CSTEP
|
||||
#define CONF_DFLL_CSTEP 1
|
||||
#endif
|
||||
|
||||
// <o> Fine Maximum Step <0x0-0x3FF>
|
||||
// <id> dfll_arch_fstep
|
||||
#ifndef CONF_DFLL_FSTEP
|
||||
#define CONF_DFLL_FSTEP 1
|
||||
#endif
|
||||
|
||||
// <o> DFLL Multiply Factor <0x0-0xFFFF>
|
||||
// <id> dfll48m_mul
|
||||
#ifndef CONF_DFLL_MUL
|
||||
#define CONF_DFLL_MUL 0
|
||||
#endif
|
||||
|
||||
// <e> DFLL Calibration Overwrite
|
||||
// <i> Indicates whether Overwrite Calibration value of DFLL
|
||||
// <id> dfll_arch_calibration
|
||||
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
|
||||
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Value <0x0-0x3F>
|
||||
// <id> dfll_arch_coarse
|
||||
#ifndef CONF_DFLL_COARSE
|
||||
#define CONF_DFLL_COARSE (0x1f / 4)
|
||||
#endif
|
||||
|
||||
// <o> Fine Value <0x0-0x3FF>
|
||||
// <id> dfll_arch_fine
|
||||
#ifndef CONF_DFLL_FINE
|
||||
#define CONF_DFLL_FINE (0x200)
|
||||
#endif
|
||||
|
||||
//</e>
|
||||
|
||||
//</h>
|
||||
|
||||
//</e>
|
||||
|
||||
// <e> DPLL Configuration
|
||||
// <i> Indicates whether configuration for DPLL is enabled or not
|
||||
// <id> enable_fdpll96m
|
||||
#ifndef CONF_DPLL_CONFIG
|
||||
#define CONF_DPLL_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <i> Select the clock source.
|
||||
// <id> fdpll96m_ref_clock
|
||||
#ifndef CONF_DPLL_GCLK
|
||||
#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K
|
||||
|
||||
#endif
|
||||
|
||||
// <h> Digital Phase Locked Loop Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
|
||||
// <id> fdpll96m_arch_enable
|
||||
#ifndef CONF_DPLL_ENABLE
|
||||
#define CONF_DPLL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> fdpll96m_arch_ondemand
|
||||
#ifndef CONF_DPLL_ONDEMAND
|
||||
#define CONF_DPLL_ONDEMAND 1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> fdpll96m_arch_runstdby
|
||||
#ifndef CONF_DPLL_RUNSTDBY
|
||||
#define CONF_DPLL_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Fractional Part <0x0-0xF>
|
||||
// <id> fdpll96m_ldrfrac
|
||||
#ifndef CONF_DPLL_LDRFRAC
|
||||
#define CONF_DPLL_LDRFRAC 0xd
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Integer Part <0x0-0xFFF>
|
||||
// <id> fdpll96m_ldr
|
||||
#ifndef CONF_DPLL_LDR
|
||||
#define CONF_DPLL_LDR 0x5b7
|
||||
#endif
|
||||
|
||||
// <o> Clock Divider <0x0-0x3FF>
|
||||
// <id> fdpll96m_clock_div
|
||||
#ifndef CONF_DPLL_DIV
|
||||
#define CONF_DPLL_DIV 0
|
||||
#endif
|
||||
|
||||
// <q> Lock Bypass
|
||||
// <i> Indicates whether Lock Bypass is enabled or not
|
||||
// <id> fdpll96m_arch_lbypass
|
||||
#ifndef CONF_DPLL_LBYPASS
|
||||
#define CONF_DPLL_LBYPASS 0
|
||||
#endif
|
||||
|
||||
// <o> Lock Time
|
||||
// <0=>No time-out, automatic lock
|
||||
// <4=>The Time-out if no lock within 8 ms
|
||||
// <5=>The Time-out if no lock within 9 ms
|
||||
// <6=>The Time-out if no lock within 10 ms
|
||||
// <7=>The Time-out if no lock within 11 ms
|
||||
// <id> fdpll96m_arch_ltime
|
||||
#ifndef CONF_DPLL_LTIME
|
||||
#define CONF_DPLL_LTIME 0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0=>XOSC32K clock reference
|
||||
// <1=>XOSC clock reference
|
||||
// <2=>GCLK clock reference
|
||||
// <id> fdpll96m_arch_refclk
|
||||
#ifndef CONF_DPLL_REFCLK
|
||||
#define CONF_DPLL_REFCLK 0
|
||||
#endif
|
||||
|
||||
// <q> Wake Up Fast
|
||||
// <i> Indicates whether Wake Up Fast is enabled or not
|
||||
// <id> fdpll96m_arch_wuf
|
||||
#ifndef CONF_DPLL_WUF
|
||||
#define CONF_DPLL_WUF 0
|
||||
#endif
|
||||
|
||||
// <q> Low-Power Enable
|
||||
// <i> Indicates whether Low-Power Enable is enabled or not
|
||||
// <id> fdpll96m_arch_lpen
|
||||
#ifndef CONF_DPLL_LPEN
|
||||
#define CONF_DPLL_LPEN 0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0=>Default filter mode
|
||||
// <1=>Low bandwidth filter
|
||||
// <2=>High bandwidth filter
|
||||
// <3=>High damping filter
|
||||
// <id> fdpll96m_arch_filter
|
||||
#ifndef CONF_DPLL_FILTER
|
||||
#define CONF_DPLL_FILTER 0
|
||||
#endif
|
||||
|
||||
// <y> Output Clock Prescaler
|
||||
// <OSCCTRL_DPLLPRESC_PRESC_DIV1_Val"> 1
|
||||
// <OSCCTRL_DPLLPRESC_PRESC_DIV2_Val"> 2
|
||||
// <OSCCTRL_DPLLPRESC_PRESC_DIV4_Val"> 4
|
||||
// <id> fdpll96m_presc
|
||||
#ifndef CONF_DPLL_PRESC
|
||||
#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_OSCCTRL_CONFIG_H
|
||||
284
Smol Watch Project/My Project/Config/hpl_port_config.h
Normal file
284
Smol Watch Project/My Project/Config/hpl_port_config.h
Normal file
@@ -0,0 +1,284 @@
|
||||
/* Auto-generated config file hpl_port_config.h */
|
||||
#ifndef HPL_PORT_CONFIG_H
|
||||
#define HPL_PORT_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> PORT Input Event 0 configuration
|
||||
// <id> enable_port_input_event_0
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_0
|
||||
#define CONF_PORT_EVCTRL_PORT_0 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 0 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
|
||||
// <id> porta_input_event_enable_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_0
|
||||
#define CONF_PORTA_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 0
|
||||
// <id> porta_event_action_0
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_0
|
||||
#define CONF_PORTA_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
|
||||
// <id> portb_input_event_enable_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_0
|
||||
#define CONF_PORTB_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 0
|
||||
// <id> portb_event_action_0
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_0
|
||||
#define CONF_PORTB_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 1 configuration
|
||||
// <id> enable_port_input_event_1
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_1
|
||||
#define CONF_PORT_EVCTRL_PORT_1 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 1 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
|
||||
// <id> porta_input_event_enable_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_1
|
||||
#define CONF_PORTA_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 1
|
||||
// <id> porta_event_action_1
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_1
|
||||
#define CONF_PORTA_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
|
||||
// <id> portb_input_event_enable_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_1
|
||||
#define CONF_PORTB_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 1
|
||||
// <id> portb_event_action_1
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_1
|
||||
#define CONF_PORTB_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 2 configuration
|
||||
// <id> enable_port_input_event_2
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_2
|
||||
#define CONF_PORT_EVCTRL_PORT_2 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 2 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
|
||||
// <id> porta_input_event_enable_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_2
|
||||
#define CONF_PORTA_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 2
|
||||
// <id> porta_event_action_2
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_2
|
||||
#define CONF_PORTA_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
|
||||
// <id> portb_input_event_enable_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_2
|
||||
#define CONF_PORTB_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 2
|
||||
// <id> portb_event_action_2
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_2
|
||||
#define CONF_PORTB_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 3 configuration
|
||||
// <id> enable_port_input_event_3
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_3
|
||||
#define CONF_PORT_EVCTRL_PORT_3 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 3 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
|
||||
// <id> porta_input_event_enable_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_3
|
||||
#define CONF_PORTA_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 3
|
||||
// <id> porta_event_action_3
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_3
|
||||
#define CONF_PORTA_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
|
||||
// <id> portb_input_event_enable_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_3
|
||||
#define CONF_PORTB_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 3
|
||||
// <id> portb_event_action_3
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_3
|
||||
#define CONF_PORTB_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
#define CONF_PORTA_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
|
||||
#define CONF_PORTB_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_PORT_CONFIG_H
|
||||
318
Smol Watch Project/My Project/Config/hpl_rtc_config.h
Normal file
318
Smol Watch Project/My Project/Config/hpl_rtc_config.h
Normal file
@@ -0,0 +1,318 @@
|
||||
/* Auto-generated config file hpl_rtc_config.h */
|
||||
#ifndef HPL_RTC_CONFIG_H
|
||||
#define HPL_RTC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Basic settings
|
||||
|
||||
#ifndef CONF_RTC_ENABLE
|
||||
#define CONF_RTC_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <q> Force reset RTC on initialization
|
||||
// <i> Force RTC to reset on initialization.
|
||||
// <i> Note that the previous power down data in RTC is lost if it's enabled.
|
||||
// <id> rtc_arch_init_reset
|
||||
#ifndef CONF_RTC_INIT_RESET
|
||||
#define CONF_RTC_INIT_RESET 1
|
||||
#endif
|
||||
|
||||
// <o> Prescaler configuration
|
||||
// <0x0=>OFF(Peripheral clock divided by 1)
|
||||
// <0x1=>Peripheral clock divided by 1
|
||||
// <0x2=>Peripheral clock divided by 2
|
||||
// <0x3=>Peripheral clock divided by 4
|
||||
// <0x4=>Peripheral clock divided by 8
|
||||
// <0x5=>Peripheral clock divided by 16
|
||||
// <0x6=>Peripheral clock divided by 32
|
||||
// <0x7=>Peripheral clock divided by 64
|
||||
// <0x8=>Peripheral clock divided by 128
|
||||
// <0x9=>Peripheral clock divided by 256
|
||||
// <0xA=>Peripheral clock divided by 512
|
||||
// <0xB=>Peripheral clock divided by 1024
|
||||
// <i> These bits define the RTC clock relative to the peripheral clock
|
||||
// <id> rtc_arch_prescaler
|
||||
#ifndef CONF_RTC_PRESCALER
|
||||
|
||||
#define CONF_RTC_PRESCALER 0xb
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef CONF_RTC_COMP_VAL
|
||||
|
||||
#define CONF_RTC_COMP_VAL 0
|
||||
|
||||
#endif
|
||||
|
||||
// <e> RTC Tamper Input 0 settings
|
||||
// <id> tamper_input_0_settings
|
||||
#ifndef CONF_TAMPER_INPUT_0_SETTINGS
|
||||
#define CONF_TAMPER_INPUT_0_SETTINGS 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Level Settings
|
||||
// <i> Indicates Tamper input 0 level
|
||||
// <id> tamper_level_0
|
||||
#ifndef CONF_RTC_TAMP_LVL_0
|
||||
#define CONF_RTC_TAMP_LVL_0 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Input Action
|
||||
// <0x0=>OFF(Disabled)
|
||||
// <0x1=>Wake and Set Tamper Flag
|
||||
// <0x2=>Capture Timestamp and Set Tamper Flag
|
||||
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
|
||||
// <i> These bits define the RTC Tamper Input Action to be performed
|
||||
// <id> rtc_tamper_input_action_0
|
||||
#ifndef CONF_RTC_TAMPER_INACT_0
|
||||
#define CONF_RTC_TAMPER_INACT_0 0
|
||||
#endif
|
||||
|
||||
// <q> Debounce Enable for Tamper Input
|
||||
// <i> Indicates Debounce should be enabled for Tamper input 0
|
||||
// <id> tamper_debounce_enable_0
|
||||
#ifndef CONF_RTC_TAMP_DEBNC_0
|
||||
#define CONF_RTC_TAMP_DEBNC_0 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> RTC Tamper Input 1 settings
|
||||
// <id> tamper_input_1_settings
|
||||
#ifndef CONF_TAMPER_INPUT_1_SETTINGS
|
||||
#define CONF_TAMPER_INPUT_1_SETTINGS 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Level Settings
|
||||
// <i> Indicates Tamper input 1 level
|
||||
// <id> tamper_level_1
|
||||
#ifndef CONF_RTC_TAMP_LVL_1
|
||||
#define CONF_RTC_TAMP_LVL_1 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Input Action
|
||||
// <0x0=>OFF(Disabled)
|
||||
// <0x1=>Wake and Set Tamper Flag
|
||||
// <0x2=>Capture Timestamp and Set Tamper Flag
|
||||
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
|
||||
// <i> These bits define the RTC Tamper Input Action to be performed
|
||||
// <id> rtc_tamper_input_action_1
|
||||
#ifndef CONF_RTC_TAMPER_INACT_1
|
||||
#define CONF_RTC_TAMPER_INACT_1 0
|
||||
#endif
|
||||
|
||||
// <q> Debounce Enable for Tamper Input
|
||||
// <i> Indicates Debounce should be enabled for Tamper input 1
|
||||
// <id> tamper_debounce_enable_1
|
||||
#ifndef CONF_RTC_TAMP_DEBNC_1
|
||||
#define CONF_RTC_TAMP_DEBNC_1 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> RTC Tamper Input 2 settings
|
||||
// <id> tamper_input_2_settings
|
||||
#ifndef CONF_TAMPER_INPUT_2_SETTINGS
|
||||
#define CONF_TAMPER_INPUT_2_SETTINGS 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Level Settings
|
||||
// <i> Indicates Tamper input 2 level
|
||||
// <id> tamper_level_2
|
||||
#ifndef CONF_RTC_TAMP_LVL_2
|
||||
#define CONF_RTC_TAMP_LVL_2 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Input Action
|
||||
// <0x0=>OFF(Disabled)
|
||||
// <0x1=>Wake and Set Tamper Flag
|
||||
// <0x2=>Capture Timestamp and Set Tamper Flag
|
||||
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
|
||||
// <i> These bits define the RTC Tamper Input Action to be performed
|
||||
// <id> rtc_tamper_input_action_2
|
||||
#ifndef CONF_RTC_TAMPER_INACT_2
|
||||
#define CONF_RTC_TAMPER_INACT_2 0
|
||||
#endif
|
||||
|
||||
// <q> Debounce Enable for Tamper Input
|
||||
// <i> Indicates Debounce should be enabled for Tamper input 2
|
||||
// <id> tamper_debounce_enable_2
|
||||
#ifndef CONF_RTC_TAMP_DEBNC_2
|
||||
#define CONF_RTC_TAMP_DEBNC_2 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> RTC Tamper Input 3 settings
|
||||
// <id> tamper_input_3_settings
|
||||
#ifndef CONF_TAMPER_INPUT_3_SETTINGS
|
||||
#define CONF_TAMPER_INPUT_3_SETTINGS 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Level Settings
|
||||
// <i> Indicates Tamper input 3 level
|
||||
// <id> tamper_level_3
|
||||
#ifndef CONF_RTC_TAMP_LVL_3
|
||||
#define CONF_RTC_TAMP_LVL_3 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Input Action
|
||||
// <0x0=>OFF(Disabled)
|
||||
// <0x1=>Wake and Set Tamper Flag
|
||||
// <0x2=>Capture Timestamp and Set Tamper Flag
|
||||
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
|
||||
// <i> These bits define the RTC Tamper Input Action to be performed
|
||||
// <id> rtc_tamper_input_action_3
|
||||
#ifndef CONF_RTC_TAMPER_INACT_3
|
||||
#define CONF_RTC_TAMPER_INACT_3 0
|
||||
#endif
|
||||
|
||||
// <q> Debounce Enable for Tamper Input
|
||||
// <i> Indicates Debounce should be enabled for Tamper input 3
|
||||
// <id> tamper_debounce_enable_3
|
||||
#ifndef CONF_RTC_TAMP_DEBNC_3
|
||||
#define CONF_RTC_TAMP_DEBNC_3 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> RTC Tamper Input 4 settings
|
||||
// <id> tamper_input_4_settings
|
||||
#ifndef CONF_TAMPER_INPUT_4_SETTINGS
|
||||
#define CONF_TAMPER_INPUT_4_SETTINGS 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Level Settings
|
||||
// <i> Indicates Tamper input 4 level
|
||||
// <id> tamper_level_4
|
||||
#ifndef CONF_RTC_TAMP_LVL_4
|
||||
#define CONF_RTC_TAMP_LVL_4 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Input Action
|
||||
// <0x0=>OFF(Disabled)
|
||||
// <0x1=>Wake and Set Tamper Flag
|
||||
// <0x2=>Capture Timestamp and Set Tamper Flag
|
||||
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
|
||||
// <i> These bits define the RTC Tamper Input Action to be performed
|
||||
// <id> rtc_tamper_input_action_4
|
||||
#ifndef CONF_RTC_TAMPER_INACT_4
|
||||
#define CONF_RTC_TAMPER_INACT_4 0
|
||||
#endif
|
||||
|
||||
// <q> Debounce Enable for Tamper Input
|
||||
// <i> Indicates Debounce should be enabled for Tamper input 4
|
||||
// <id> tamper_debounce_enable_4
|
||||
#ifndef CONF_RTC_TAMP_DEBNC_4
|
||||
#define CONF_RTC_TAMP_DEBNC_4 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o> RTC Tamper Active Layer Frequency Prescalar
|
||||
// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2
|
||||
// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4
|
||||
// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8
|
||||
// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16
|
||||
// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32
|
||||
// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64
|
||||
// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128
|
||||
// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256
|
||||
// <i> These bits define the RTC Tamper Active Layer Frequecny Prescalar
|
||||
// <id> rtc_tamper_active_layer_frequency_prescalar
|
||||
#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES
|
||||
#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Debounce Frequency Prescalar
|
||||
// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2
|
||||
// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4
|
||||
// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8
|
||||
// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16
|
||||
// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32
|
||||
// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64
|
||||
// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128
|
||||
// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256
|
||||
// <i> These bits define the RTC Debounce Frequency Prescalar
|
||||
// <id> rtc_tamper_debounce_frequency_prescalar
|
||||
#ifndef CONF_RTC_TAMP_DEBF_PRES
|
||||
#define CONF_RTC_TAMP_DEBF_PRES 0
|
||||
#endif
|
||||
|
||||
// <e> Event control
|
||||
// <id> rtc_event_control
|
||||
#ifndef CONF_RTC_EVENT_CONTROL_ENABLE
|
||||
#define CONF_RTC_EVENT_CONTROL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> Periodic Interval 0 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated
|
||||
// <id> rtc_pereo0
|
||||
#ifndef CONF_RTC_PEREO0
|
||||
#define CONF_RTC_PEREO0 0
|
||||
#endif
|
||||
// <q> Periodic Interval 1 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated
|
||||
// <id> rtc_pereo1
|
||||
#ifndef CONF_RTC_PEREO1
|
||||
#define CONF_RTC_PEREO1 0
|
||||
#endif
|
||||
// <q> Periodic Interval 2 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated
|
||||
// <id> rtc_pereo2
|
||||
#ifndef CONF_RTC_PEREO2
|
||||
#define CONF_RTC_PEREO2 0
|
||||
#endif
|
||||
// <q> Periodic Interval 3 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated
|
||||
// <id> rtc_pereo3
|
||||
#ifndef CONF_RTC_PEREO3
|
||||
#define CONF_RTC_PEREO3 0
|
||||
#endif
|
||||
// <q> Periodic Interval 4 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated
|
||||
// <id> rtc_pereo4
|
||||
#ifndef CONF_RTC_PEREO4
|
||||
#define CONF_RTC_PEREO4 0
|
||||
#endif
|
||||
// <q> Periodic Interval 5 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated
|
||||
// <id> rtc_pereo5
|
||||
#ifndef CONF_RTC_PEREO5
|
||||
#define CONF_RTC_PEREO5 0
|
||||
#endif
|
||||
// <q> Periodic Interval 6 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated
|
||||
// <id> rtc_pereo6
|
||||
#ifndef CONF_RTC_PEREO6
|
||||
#define CONF_RTC_PEREO6 0
|
||||
#endif
|
||||
// <q> Periodic Interval 7 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated
|
||||
// <id> rtc_pereo7
|
||||
#ifndef CONF_RTC_PEREO7
|
||||
#define CONF_RTC_PEREO7 0
|
||||
#endif
|
||||
|
||||
// <q> Compare 0 Event Output
|
||||
// <i> This bit indicates whether Compare O event is enabled and will be generated
|
||||
// <id> rtc_cmpeo0
|
||||
#ifndef CONF_RTC_COMPE0
|
||||
#define CONF_RTC_COMPE0 0
|
||||
#endif
|
||||
|
||||
// <q> Overflow Event Output
|
||||
// <i> This bit indicates whether Overflow event is enabled and will be generated
|
||||
// <id> rtc_ovfeo
|
||||
#ifndef CONF_RTC_OVFEO
|
||||
#define CONF_RTC_OVFEO 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_RTC_CONFIG_H
|
||||
144
Smol Watch Project/My Project/Config/hpl_sercom_config.h
Normal file
144
Smol Watch Project/My Project/Config/hpl_sercom_config.h
Normal file
@@ -0,0 +1,144 @@
|
||||
/* Auto-generated config file hpl_sercom_config.h */
|
||||
#ifndef HPL_SERCOM_CONFIG_H
|
||||
#define HPL_SERCOM_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
|
||||
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_1_I2CM_ENABLE
|
||||
#define CONF_SERCOM_1_I2CM_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <h> Basic
|
||||
|
||||
// <o> I2C Bus clock speed (Hz) <1-400000>
|
||||
// <i> I2C Bus clock (SCL) speed measured in Hz
|
||||
// <id> i2c_master_baud_rate
|
||||
#ifndef CONF_SERCOM_1_I2CM_BAUD
|
||||
#define CONF_SERCOM_1_I2CM_BAUD 100000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced
|
||||
// <id> i2c_master_advanced
|
||||
#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG
|
||||
#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <o> TRise (ns) <0-300>
|
||||
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
|
||||
// <i> Standard Fast Mode: typical 215ns, max 300ns
|
||||
// <i> Fast Mode +: typical 60ns, max 100ns
|
||||
// <i> High Speed Mode: typical 20ns, max 40ns
|
||||
// <id> i2c_master_arch_trise
|
||||
|
||||
#ifndef CONF_SERCOM_1_I2CM_TRISE
|
||||
#define CONF_SERCOM_1_I2CM_TRISE 215
|
||||
#endif
|
||||
|
||||
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
|
||||
// <i> This enables the master SCL low extend time-out
|
||||
// <id> i2c_master_arch_mexttoen
|
||||
#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN
|
||||
#define CONF_SERCOM_1_I2CM_MEXTTOEN 0
|
||||
#endif
|
||||
|
||||
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
|
||||
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
|
||||
// <id> i2c_master_arch_sexttoen
|
||||
#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN
|
||||
#define CONF_SERCOM_1_I2CM_SEXTTOEN 0
|
||||
#endif
|
||||
|
||||
// <q> SCL Low Time-Out (LOWTOUT)
|
||||
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
|
||||
// <id> i2c_master_arch_lowtout
|
||||
#ifndef CONF_SERCOM_1_I2CM_LOWTOUT
|
||||
#define CONF_SERCOM_1_I2CM_LOWTOUT 0
|
||||
#endif
|
||||
|
||||
// <o> Inactive Time-Out (INACTOUT)
|
||||
// <0x0=>Disabled
|
||||
// <0x1=>5-6 SCL cycle time-out(50-60us)
|
||||
// <0x2=>10-11 SCL cycle time-out(100-110us)
|
||||
// <0x3=>20-21 SCL cycle time-out(200-210us)
|
||||
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
|
||||
// <id> i2c_master_arch_inactout
|
||||
#ifndef CONF_SERCOM_1_I2CM_INACTOUT
|
||||
#define CONF_SERCOM_1_I2CM_INACTOUT 0x0
|
||||
#endif
|
||||
|
||||
// <o> SDA Hold Time (SDAHOLD)
|
||||
// <0=>Disabled
|
||||
// <1=>50-100ns hold time
|
||||
// <2=>300-600ns hold time
|
||||
// <3=>400-800ns hold time
|
||||
// <i> Defines the SDA hold time with respect to the negative edge of SCL
|
||||
// <id> i2c_master_arch_sdahold
|
||||
#ifndef CONF_SERCOM_1_I2CM_SDAHOLD
|
||||
#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Determine if the module shall run in standby sleep mode
|
||||
// <id> i2c_master_arch_runstdby
|
||||
#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY
|
||||
#define CONF_SERCOM_1_I2CM_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> i2c_master_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE
|
||||
#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
#ifndef CONF_SERCOM_1_I2CM_SPEED
|
||||
#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
|
||||
#endif
|
||||
#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300
|
||||
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
|
||||
#undef CONF_SERCOM_1_I2CM_TRISE
|
||||
#define CONF_SERCOM_1_I2CM_TRISE 215U
|
||||
#endif
|
||||
|
||||
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
|
||||
// BAUD + BAUDLOW = --------------------------------------------------------------------
|
||||
// i2c_scl_freq
|
||||
// BAUD: register value low [7:0]
|
||||
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
|
||||
#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \
|
||||
(((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \
|
||||
- (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \
|
||||
/ 1000U)) \
|
||||
* 10U \
|
||||
+ 5U) \
|
||||
/ (CONF_SERCOM_1_I2CM_BAUD * 10U))
|
||||
#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE
|
||||
#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2)
|
||||
#warning Requested I2C baudrate too low, please check
|
||||
#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF
|
||||
#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1
|
||||
#warning Requested I2C baudrate too high, please check
|
||||
#define CONF_SERCOM_1_I2CM_BAUD_RATE 1
|
||||
#else
|
||||
#define CONF_SERCOM_1_I2CM_BAUD_RATE \
|
||||
((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \
|
||||
? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
|
||||
: (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_SERCOM_CONFIG_H
|
||||
2744
Smol Watch Project/My Project/Config/hpl_slcd_config.h
Normal file
2744
Smol Watch Project/My Project/Config/hpl_slcd_config.h
Normal file
File diff suppressed because it is too large
Load Diff
18
Smol Watch Project/My Project/Config/hpl_systick_config.h
Normal file
18
Smol Watch Project/My Project/Config/hpl_systick_config.h
Normal file
@@ -0,0 +1,18 @@
|
||||
/* Auto-generated config file hpl_systick_config.h */
|
||||
#ifndef HPL_SYSTICK_CONFIG_H
|
||||
#define HPL_SYSTICK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Advanced settings
|
||||
// <q> SysTick exception request
|
||||
// <i> Indicates whether the generation of SysTick exception is enabled or not
|
||||
// <id> systick_arch_tickint
|
||||
#ifndef CONF_SYSTICK_TICKINT
|
||||
#define CONF_SYSTICK_TICKINT 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_SYSTICK_CONFIG_H
|
||||
206
Smol Watch Project/My Project/Config/hpl_tc_config.h
Normal file
206
Smol Watch Project/My Project/Config/hpl_tc_config.h
Normal file
@@ -0,0 +1,206 @@
|
||||
/* Auto-generated config file hpl_tc_config.h */
|
||||
#ifndef HPL_TC_CONFIG_H
|
||||
#define HPL_TC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
#ifndef CONF_TC3_ENABLE
|
||||
#define CONF_TC3_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <h> Basic settings
|
||||
// <o> Prescaler
|
||||
// <0=> No division
|
||||
// <1=> Divide by 2
|
||||
// <2=> Divide by 4
|
||||
// <3=> Divide by 8
|
||||
// <4=> Divide by 16
|
||||
// <5=> Divide by 64
|
||||
// <6=> Divide by 256
|
||||
// <7=> Divide by 1024
|
||||
// <i> This defines the prescaler value
|
||||
// <id> tc_prescaler
|
||||
#ifndef CONF_TC3_PRESCALER
|
||||
#define CONF_TC3_PRESCALER 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <h> PWM Waveform Output settings
|
||||
// <o> Waveform Period Value (uS) <0x00-0xFFFFFFFF>
|
||||
// <i> The unit of this value is us.
|
||||
// <id> tc_arch_wave_per_val
|
||||
#ifndef CONF_TC3_WAVE_PER_VAL
|
||||
#define CONF_TC3_WAVE_PER_VAL 0x3e8
|
||||
#endif
|
||||
|
||||
// <o> Waveform Duty Value (0.1%) <0x00-0x03E8>
|
||||
// <i> The unit of this value is 1/1000.
|
||||
// <id> tc_arch_wave_duty_val
|
||||
#ifndef CONF_TC3_WAVE_DUTY_VAL
|
||||
#define CONF_TC3_WAVE_DUTY_VAL 0x1f4
|
||||
#endif
|
||||
|
||||
/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
|
||||
#if CONF_TC3_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val
|
||||
#define CONF_TC3_CC0 \
|
||||
((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1000000 / (1 << CONF_TC3_PRESCALER) - 1))
|
||||
#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
|
||||
|
||||
#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val
|
||||
#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 64000000 - 1))
|
||||
#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
|
||||
|
||||
#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val
|
||||
#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 256000000 - 1))
|
||||
#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
|
||||
|
||||
#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val
|
||||
#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1024000000 - 1))
|
||||
#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h> Advanced settings
|
||||
// <y> Mode
|
||||
// <TC_CTRLA_MODE_COUNT16_Val"> Counter in 16-bit mode
|
||||
// <TC_CTRLA_MODE_COUNT32_Val"> Counter in 32-bit mode
|
||||
// <i> These bits mode
|
||||
// <id> tc_mode
|
||||
#ifndef CONF_TC3_MODE
|
||||
#define CONF_TC3_MODE TC_CTRLA_MODE_COUNT16_Val
|
||||
#endif
|
||||
|
||||
/* Unused in 16/32 bit PWM mode */
|
||||
#ifndef CONF_TC3_PER
|
||||
#define CONF_TC3_PER 0x32
|
||||
#endif
|
||||
|
||||
// <y> Prescaler and Counter Synchronization Selection
|
||||
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
|
||||
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
|
||||
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
|
||||
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
|
||||
// <id> tc_arch_presync
|
||||
#ifndef CONF_TC3_PRESCSYNC
|
||||
#define CONF_TC3_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
|
||||
#endif
|
||||
|
||||
// <q> Run in standby
|
||||
// <i> Indicates whether the will continue running in standby sleep mode or not
|
||||
// <id> tc_arch_runstdby
|
||||
#ifndef CONF_TC3_RUNSTDBY
|
||||
#define CONF_TC3_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> On-Demand
|
||||
// <i> Indicates whether the TC3's on-demand mode is on or not
|
||||
// <id> tc_arch_ondemand
|
||||
#ifndef CONF_TC3_ONDEMAND
|
||||
#define CONF_TC3_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <o> Auto Lock
|
||||
// <0x0=>The Lock Update bit is not affected on overflow/underflow and re-trigger event
|
||||
// <0x1=>The Lock Update bit is set on each overflow/underflow or re-trigger event
|
||||
// <id> tc_arch_alock
|
||||
#ifndef CONF_TC3_ALOCK
|
||||
#define CONF_TC3_ALOCK 0
|
||||
#endif
|
||||
|
||||
/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
|
||||
//#define CONF_TC3_CAPTEN0 0
|
||||
//#define CONF_TC3_CAPTEN1 0
|
||||
//#define CONF_TC3_COPEN0 0
|
||||
//#define CONF_TC3_COPEN1 0
|
||||
|
||||
/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
|
||||
//#define CONF_TC3_DIR 0
|
||||
//#define CONF_TC3_ONESHOT 0
|
||||
//#define CONF_TC3_LUPD 0
|
||||
|
||||
// <q> Debug Running Mode
|
||||
// <i> Indicates whether the Debug Running Mode is enabled or not
|
||||
// <id> tc_arch_dbgrun
|
||||
#ifndef CONF_TC3_DBGRUN
|
||||
#define CONF_TC3_DBGRUN 0
|
||||
#endif
|
||||
|
||||
// <e> Event control
|
||||
// <id> timer_event_control
|
||||
#ifndef CONF_TC3_EVENT_CONTROL_ENABLE
|
||||
#define CONF_TC3_EVENT_CONTROL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Match or Capture on Channel 0
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_mceo0
|
||||
#ifndef CONF_TC3_MCEO0
|
||||
#define CONF_TC3_MCEO0 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Match or Capture on Channel 1
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_mceo1
|
||||
#ifndef CONF_TC3_MCEO1
|
||||
#define CONF_TC3_MCEO1 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Timer Tick
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_ovfeo
|
||||
#ifndef CONF_TC3_OVFEO
|
||||
#define CONF_TC3_OVFEO 0
|
||||
#endif
|
||||
|
||||
// <q> Event Input
|
||||
// <i> Enable asynchronous input events
|
||||
// <id> tc_arch_tcei
|
||||
#ifndef CONF_TC3_TCEI
|
||||
#define CONF_TC3_TCEI 0
|
||||
#endif
|
||||
|
||||
// <q> Inverted Event Input
|
||||
// <i> Invert the asynchronous input events
|
||||
// <id> tc_arch_tcinv
|
||||
#ifndef CONF_TC3_TCINV
|
||||
#define CONF_TC3_TCINV 0
|
||||
#endif
|
||||
|
||||
// <o> Event action
|
||||
// <0=> Event action disabled
|
||||
// <1=> Start, restart or re-trigger TC on event
|
||||
// <2=> Count on event
|
||||
// <3=> Start on event
|
||||
// <4=> Time stamp capture
|
||||
// <5=> Period captured in CC0, pulse width in CC1
|
||||
// <6=> Period captured in CC1, pulse width in CC0
|
||||
// <7=> Pulse width capture
|
||||
// <i> Event which will be performed on an event
|
||||
//<id> tc_arch_evact
|
||||
#ifndef CONF_TC3_EVACT
|
||||
#define CONF_TC3_EVACT 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
|
||||
//#define CONF_TC3_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val
|
||||
|
||||
/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
|
||||
//#define CONF_TC3_INVEN0 0
|
||||
//#define CONF_TC3_INVEN1 0
|
||||
|
||||
/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
|
||||
//#define CONF_TC3_PERBUF 0
|
||||
|
||||
/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
|
||||
//#define CONF_TC3_CCBUF0 0
|
||||
//#define CONF_TC3_CCBUF1 0
|
||||
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_TC_CONFIG_H
|
||||
547
Smol Watch Project/My Project/Config/hpl_tcc_config.h
Normal file
547
Smol Watch Project/My Project/Config/hpl_tcc_config.h
Normal file
@@ -0,0 +1,547 @@
|
||||
/* Auto-generated config file hpl_tcc_config.h */
|
||||
#ifndef HPL_TCC_CONFIG_H
|
||||
#define HPL_TCC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
#ifndef CONF_TCC0_ENABLE
|
||||
#define CONF_TCC0_ENABLE 1
|
||||
#endif
|
||||
|
||||
#ifndef CONF_TCC0_PWM_ENABLE
|
||||
#define CONF_TCC0_PWM_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <h> Basic settings
|
||||
// <y> TCC0 Prescaler
|
||||
// <TCC_CTRLA_PRESCALER_DIV1_Val"> No division
|
||||
// <TCC_CTRLA_PRESCALER_DIV2_Val"> Divide by 2
|
||||
// <TCC_CTRLA_PRESCALER_DIV4_Val"> Divide by 4
|
||||
// <TCC_CTRLA_PRESCALER_DIV8_Val"> Divide by 8
|
||||
// <TCC_CTRLA_PRESCALER_DIV16_Val"> Divide by 16
|
||||
// <TCC_CTRLA_PRESCALER_DIV64_Val"> Divide by 64
|
||||
// <TCC_CTRLA_PRESCALER_DIV256_Val"> Divide by 256
|
||||
// <TCC_CTRLA_PRESCALER_DIV1024_Val"> Divide by 1024
|
||||
// <i> This defines the TCC0 prescaler value
|
||||
// <id> tcc_prescaler
|
||||
#ifndef CONF_TCC0_PRESCALER
|
||||
#define CONF_TCC0_PRESCALER TCC_CTRLA_PRESCALER_DIV8_Val
|
||||
#endif
|
||||
|
||||
// <hidden>
|
||||
//<o> TCC0 Period Value <0x000000-0xFFFFFF>
|
||||
// <id> tcc_per
|
||||
#ifndef CONF_TCC0_PER
|
||||
#define CONF_TCC0_PER 0x2710
|
||||
#endif
|
||||
// </hidden>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h> PWM Waveform Output settings
|
||||
// <o> TCC0 Waveform Period Value (uS) <0x00-0xFFFFFFFF>
|
||||
// <i> The unit of this value is us.
|
||||
// <id> tcc_arch_wave_per_val
|
||||
#ifndef CONF_TCC0_WAVE_PER_VAL
|
||||
#define CONF_TCC0_WAVE_PER_VAL 0x3e8
|
||||
#endif
|
||||
|
||||
// <o> TCC0 Waveform Duty Value (0.1%) <0x00-0x03E8>
|
||||
// <i> The unit of this value is 1/1000.
|
||||
// <id> tcc_arch_wave_duty_val
|
||||
#ifndef CONF_TCC0_WAVE_DUTY_VAL
|
||||
#define CONF_TCC0_WAVE_DUTY_VAL 0x1f4
|
||||
#endif
|
||||
|
||||
// <o> TCC0 Waveform Channel Select <0x00-0x03>
|
||||
// <i> Index of the Compare Channel register, into which the Waveform Duty Value is written.
|
||||
// <i> Give index of the Compare Channel register here in 0x00-0x03 range.
|
||||
// <id> tcc_arch_sel_ch
|
||||
#ifndef CONF_TCC0_SEL_CH
|
||||
#define CONF_TCC0_SEL_CH 0x1
|
||||
#endif
|
||||
|
||||
/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
|
||||
#if CONF_TCC0_PRESCALER < TCC_CTRLA_PRESCALER_DIV64_Val
|
||||
#define CONF_TCC0_PER_REG \
|
||||
((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1000000 / (1 << CONF_TCC0_PRESCALER) - 1))
|
||||
#define CONF_TCC0_CCX_REG ((uint32_t)(((double)(double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
|
||||
|
||||
#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV64_Val
|
||||
#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 64000000 - 1))
|
||||
#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
|
||||
|
||||
#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV256_Val
|
||||
#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 256000000 - 1))
|
||||
#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
|
||||
|
||||
#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV1024_Val
|
||||
#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1024000000 - 1))
|
||||
#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <h> Advanced settings
|
||||
/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL A register.
|
||||
* May be used by other abstractions based on TC. */
|
||||
//#define CONF_TCC0_RESOLUTION TCC_CTRLA_RESOLUTION_NONE_Val
|
||||
// <q> Run in standby
|
||||
// <i> Indicates whether the TCC0 will continue running in standby sleep mode or not
|
||||
// <id> tcc_arch_runstdby
|
||||
#ifndef CONF_TCC0_RUNSTDBY
|
||||
#define CONF_TCC0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <y> TCC0 Prescaler and Counter Synchronization Selection
|
||||
// <TCC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
|
||||
// <TCC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
|
||||
// <TCC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
|
||||
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock.
|
||||
// <id> tcc_arch_prescsync
|
||||
#ifndef CONF_TCC0_PRESCSYNC
|
||||
#define CONF_TCC0_PRESCSYNC TCC_CTRLA_PRESCSYNC_GCLK_Val
|
||||
#endif
|
||||
|
||||
// <y> TCC0 Waveform Generation Selection
|
||||
// <TCC_WAVE_WAVEGEN_NPWM_Val"> Single-slope PWM
|
||||
// <TCC_WAVE_WAVEGEN_DSCRITICAL_Val"> Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
|
||||
// <TCC_WAVE_WAVEGEN_DSBOTTOM_Val"> Dual-slope, interrupt/event at ZERO (DSBOTTOM)
|
||||
// <TCC_WAVE_WAVEGEN_DSBOTH_Val"> Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
|
||||
// <TCC_WAVE_WAVEGEN_DSTOP_Val"> Dual-slope, interrupt/event at Top (DSTOP)
|
||||
// <id> tcc_arch_wavegen
|
||||
#ifndef CONF_TCC0_WAVEGEN
|
||||
#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_NPWM_Val
|
||||
#endif
|
||||
// <q> TCC0 Auto Lock
|
||||
// <i> Indicates whether the TCC0 Auto Lock is enabled or not
|
||||
// <id> tcc_arch_alock
|
||||
#ifndef CONF_TCC0_ALOCK
|
||||
#define CONF_TCC0_ALOCK 0
|
||||
#endif
|
||||
|
||||
// <q> TCC0 Capture Channel 0 Enable
|
||||
// <i> Indicates whether the TCC0 Capture Channel 0 is enabled or not
|
||||
// <id> tcc_arch_cpten0
|
||||
#ifndef CONF_TCC0_CPTEN0
|
||||
#define CONF_TCC0_CPTEN0 0
|
||||
#endif
|
||||
|
||||
// <q> TCC0 Capture Channel 1 Enable
|
||||
// <i> Indicates whether the TCC0 Capture Channel 1 is enabled or not
|
||||
// <id> tcc_arch_cpten1
|
||||
#ifndef CONF_TCC0_CPTEN1
|
||||
#define CONF_TCC0_CPTEN1 0
|
||||
#endif
|
||||
|
||||
// <q> TCC0 Capture Channel 2 Enable
|
||||
// <i> Indicates whether the TCC0 Capture Channel 2 is enabled or not
|
||||
// <id> tcc_arch_cpten2
|
||||
#ifndef CONF_TCC0_CPTEN2
|
||||
#define CONF_TCC0_CPTEN2 0
|
||||
#endif
|
||||
|
||||
// <q> TCC0 Capture Channel 3 Enable
|
||||
// <i> Indicates whether the TCC0 Capture Channel 3 is enabled or not
|
||||
// <id> tcc_arch_cpten3
|
||||
#ifndef CONF_TCC0_CPTEN3
|
||||
#define CONF_TCC0_CPTEN3 0
|
||||
#endif
|
||||
|
||||
// <hidden>
|
||||
// <q> TCC0 Capture Channel 4 Enable
|
||||
// <i> Indicates whether the TCC0 Capture Channel 4 is enabled or not
|
||||
// <id> tcc_arch_cpten4
|
||||
#ifndef CONF_TCC0_CPTEN4
|
||||
#define CONF_TCC0_CPTEN4 0
|
||||
#endif
|
||||
// </hidden>
|
||||
// <hidden>
|
||||
// <q> TCC0 Capture Channel 5 Enable
|
||||
// <i> Indicates whether the TCC0 Capture Channel 5 is enabled or not
|
||||
// <id> tcc_arch_cpten5
|
||||
#ifndef CONF_TCC0_CPTEN5
|
||||
#define CONF_TCC0_CPTEN5 0
|
||||
#endif
|
||||
// </hidden>
|
||||
// <hidden>
|
||||
// <q> TCC0 Capture Channel 6 Enable
|
||||
// <i> Indicates whether the TCC0 Capture Channel 6 is enabled or not
|
||||
// <id> tcc_arch_cpten6
|
||||
#ifndef CONF_TCC0_CPTEN6
|
||||
#define CONF_TCC0_CPTEN6 0
|
||||
#endif
|
||||
// </hidden>
|
||||
// <hidden>
|
||||
// <q> TCC0 Capture Channel 7 Enable
|
||||
// <i> Indicates whether the TCC0 Capture Channel 7 is enabled or not
|
||||
// <id> tcc_arch_cpten7
|
||||
#ifndef CONF_TCC0_CPTEN7
|
||||
#define CONF_TCC0_CPTEN7 0
|
||||
#endif
|
||||
// </hidden>
|
||||
|
||||
// <q> TCC0 Lock update
|
||||
// <i> Indicates whether the TCC0 Lock update is enabled or not
|
||||
// <id> tcc_arch_lupd
|
||||
#ifndef CONF_TCC0_LUPD
|
||||
#define CONF_TCC0_LUPD 1
|
||||
#endif
|
||||
|
||||
/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register.
|
||||
* May be used by other abstractions based on TC. */
|
||||
//#define CONF_TCC0_DIR 0
|
||||
//#define CONF_TCC0_ONESHOT 0
|
||||
|
||||
/* Commented intentionally. No fault control for timers. */
|
||||
/*#define CONF_TCC0_FAULT_A_SRC TCC_FCTRLA_SRC_DISABLE_Val
|
||||
#define CONF_TCC0_FAULT_A_KEEP 0
|
||||
#define CONF_TCC0_FAULT_A_QUAL 0
|
||||
#define CONF_TCC0_FAULT_A_BLANK TCC_FCTRLA_BLANK_DISABLE_Val
|
||||
#define CONF_TCC0_FAULT_A_RESTART 0
|
||||
#define CONF_TCC0_FAULT_A_HALT TCC_FCTRLA_HALT_DISABLE_Val
|
||||
#define CONF_TCC0_FAULT_A_CHSEL TCC_FCTRLA_CHSEL_CC0_Val
|
||||
#define CONF_TCC0_FAULT_A_CAPTURE TCC_FCTRLA_CAPTURE_DISABLE_Val
|
||||
#define CONF_TCC0_FAULT_A_BLACNKPRESC 0
|
||||
#define CONF_TCC0_FAULT_A_BLANKVAL 0
|
||||
#define CONF_TCC0_FAULT_A_FILTERVAL 0
|
||||
|
||||
#define CONF_TCC0_FAULT_B_SRC TCC_FCTRLB_SRC_DISABLE_Val
|
||||
#define CONF_TCC0_FAULT_B_KEEP 0
|
||||
#define CONF_TCC0_FAULT_B_QUAL 0
|
||||
#define CONF_TCC0_FAULT_B_BLANK TCC_FCTRLB_BLANK_DISABLE_Val
|
||||
#define CONF_TCC0_FAULT_B_RESTART 0
|
||||
#define CONF_TCC0_FAULT_B_HALT TCC_FCTRLB_HALT_DISABLE_Val
|
||||
#define CONF_TCC0_FAULT_B_CHSEL TCC_FCTRLB_CHSEL_CC0_Val
|
||||
#define CONF_TCC0_FAULT_B_CAPTURE TCC_FCTRLB_CAPTURE_DISABLE_Val
|
||||
#define CONF_TCC0_FAULT_B_BLACNKPRESC 0
|
||||
#define CONF_TCC0_FAULT_B_BLANKVAL 0
|
||||
#define CONF_TCC0_FAULT_B_FILTERVAL 0*/
|
||||
|
||||
/* Commented intentionally. No dead-time control for timers. */
|
||||
/*#define CONF_TCC0_OTMX 0
|
||||
#define CONF_TCC0_DTIEN0 0
|
||||
#define CONF_TCC0_DTIEN1 0
|
||||
#define CONF_TCC0_DTIEN2 0
|
||||
#define CONF_TCC0_DTIEN3 0
|
||||
#define CONF_TCC0_DTHS 0*/
|
||||
|
||||
/* Commented intentionally. No driver control for timers. */
|
||||
/*#define CONF_TCC0_NRE0 0
|
||||
#define CONF_TCC0_NRE1 0
|
||||
#define CONF_TCC0_NRE2 0
|
||||
#define CONF_TCC0_NRE3 0
|
||||
#define CONF_TCC0_NRE4 0
|
||||
#define CONF_TCC0_NRE5 0
|
||||
#define CONF_TCC0_NRE6 0
|
||||
#define CONF_TCC0_NRE7 0
|
||||
#define CONF_TCC0_NVR0 0
|
||||
#define CONF_TCC0_NVR1 0
|
||||
#define CONF_TCC0_NVR2 0
|
||||
#define CONF_TCC0_NVR3 0
|
||||
#define CONF_TCC0_NVR4 0
|
||||
#define CONF_TCC0_NVR5 0
|
||||
#define CONF_TCC0_NVR6 0
|
||||
#define CONF_TCC0_NVR7 0
|
||||
#define CONF_TCC0_INVEN0 0
|
||||
#define CONF_TCC0_INVEN1 0
|
||||
#define CONF_TCC0_INVEN2 0
|
||||
#define CONF_TCC0_INVEN3 0
|
||||
#define CONF_TCC0_INVEN4 0
|
||||
#define CONF_TCC0_INVEN5 0
|
||||
#define CONF_TCC0_INVEN6 0
|
||||
#define CONF_TCC0_INVEN7 0
|
||||
#define CONF_TCC0_FILTERVAL0 0
|
||||
#define CONF_TCC0_FILTERVAL1 0*/
|
||||
|
||||
// <q> TCC0 Debug Running Mode
|
||||
// <i> Indicates whether the TCC0 Debug Running Mode is enabled or not
|
||||
// <id> tcc_arch_dbgrun
|
||||
#ifndef CONF_TCC0_DBGRUN
|
||||
#define CONF_TCC0_DBGRUN 0
|
||||
#endif
|
||||
|
||||
/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of Debug Control register.
|
||||
* May be used by other abstractions based on TC. */
|
||||
//#define CONF_TCC0_FDDBD 0
|
||||
|
||||
// <e> Event control
|
||||
// <id> timer_event_control
|
||||
#ifndef CONF_TCC0_EVENT_CONTROL_ENABLE
|
||||
#define CONF_TCC0_EVENT_CONTROL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> Match or Capture Channel 0 Event Output
|
||||
// <i> This bit indicates whether match/capture event on channel 0 is enabled and will be generated
|
||||
// <id> tcc_arch_mceo0
|
||||
#ifndef CONF_TCC0_MCEO0
|
||||
#define CONF_TCC0_MCEO0 0
|
||||
#endif
|
||||
|
||||
// <q> Match or Capture Channel 0 Event Input
|
||||
// <i> This bit indicates whether match/capture 0 incoming event is enabled
|
||||
// <id> tcc_arch_mcei0
|
||||
#ifndef CONF_TCC0_MCEI0
|
||||
#define CONF_TCC0_MCEI0 0
|
||||
#endif
|
||||
// <q> Match or Capture Channel 1 Event Output
|
||||
// <i> This bit indicates whether match/capture event on channel 1 is enabled and will be generated
|
||||
// <id> tcc_arch_mceo1
|
||||
#ifndef CONF_TCC0_MCEO1
|
||||
#define CONF_TCC0_MCEO1 0
|
||||
#endif
|
||||
|
||||
// <q> Match or Capture Channel 1 Event Input
|
||||
// <i> This bit indicates whether match/capture 1 incoming event is enabled
|
||||
// <id> tcc_arch_mcei1
|
||||
#ifndef CONF_TCC0_MCEI1
|
||||
#define CONF_TCC0_MCEI1 0
|
||||
#endif
|
||||
// <q> Match or Capture Channel 2 Event Output
|
||||
// <i> This bit indicates whether match/capture event on channel 2 is enabled and will be generated
|
||||
// <id> tcc_arch_mceo2
|
||||
#ifndef CONF_TCC0_MCEO2
|
||||
#define CONF_TCC0_MCEO2 0
|
||||
#endif
|
||||
|
||||
// <q> Match or Capture Channel 2 Event Input
|
||||
// <i> This bit indicates whether match/capture 2 incoming event is enabled
|
||||
// <id> tcc_arch_mcei2
|
||||
#ifndef CONF_TCC0_MCEI2
|
||||
#define CONF_TCC0_MCEI2 0
|
||||
#endif
|
||||
// <q> Match or Capture Channel 3 Event Output
|
||||
// <i> This bit indicates whether match/capture event on channel 3 is enabled and will be generated
|
||||
// <id> tcc_arch_mceo3
|
||||
#ifndef CONF_TCC0_MCEO3
|
||||
#define CONF_TCC0_MCEO3 0
|
||||
#endif
|
||||
|
||||
// <q> Match or Capture Channel 3 Event Input
|
||||
// <i> This bit indicates whether match/capture 3 incoming event is enabled
|
||||
// <id> tcc_arch_mcei3
|
||||
#ifndef CONF_TCC0_MCEI3
|
||||
#define CONF_TCC0_MCEI3 0
|
||||
#endif
|
||||
|
||||
// <q> Timer/Counter Event Input 0
|
||||
// <i> This bit is used to enable input event 0 to the TCC
|
||||
// <id> tcc_arch_tcei0
|
||||
#ifndef CONF_TCC0_TCEI0
|
||||
#define CONF_TCC0_TCEI0 0
|
||||
#endif
|
||||
|
||||
// <q> Timer/Counter Event Input 0 Invert
|
||||
// <i> This bit inverts the event 0 input
|
||||
// <id> tcc_arch_tceinv0
|
||||
#ifndef CONF_TCC0_TCINV0
|
||||
#define CONF_TCC0_TCINV0 0
|
||||
#endif
|
||||
// <q> Timer/Counter Event Input 1
|
||||
// <i> This bit is used to enable input event 1 to the TCC
|
||||
// <id> tcc_arch_tcei1
|
||||
#ifndef CONF_TCC0_TCEI1
|
||||
#define CONF_TCC0_TCEI1 0
|
||||
#endif
|
||||
|
||||
// <q> Timer/Counter Event Input 1 Invert
|
||||
// <i> This bit inverts the event 1 input
|
||||
// <id> tcc_arch_tceinv1
|
||||
#ifndef CONF_TCC0_TCINV1
|
||||
#define CONF_TCC0_TCINV1 0
|
||||
#endif
|
||||
|
||||
// <q> Timer/Counter Event Output
|
||||
// <i> This bit is used to enable the counter cycle event.
|
||||
//<id> tcc_arch_cnteo
|
||||
#ifndef CONF_TCC0_CNTEO
|
||||
#define CONF_TCC0_CNTEO 0
|
||||
#endif
|
||||
|
||||
// <q> Re-trigger Event Output
|
||||
// <i> This bit is used to enable the counter re-trigger event.
|
||||
//<id> tcc_arch_trgeo
|
||||
#ifndef CONF_TCC0_TRGEO
|
||||
#define CONF_TCC0_TRGEO 0
|
||||
#endif
|
||||
|
||||
// <q> Overflow/Underflow Event Output
|
||||
// <i> This bit is used to enable enable event on overflow/underflow.
|
||||
//<id> tcc_arch_ovfeo
|
||||
#ifndef CONF_TCC0_OVFEO
|
||||
#define CONF_TCC0_OVFEO 0
|
||||
#endif
|
||||
|
||||
// <o> Timer/Counter Interrupt and Event Output Selection
|
||||
// <0=> An interrupt/event is generated when a new counter cycle starts
|
||||
// <1=> An interrupt/event is generated when a counter cycle ends
|
||||
// <2=> An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
|
||||
// <3=> An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
|
||||
// <i> These bits define on which part of the counter cycle the counter event output is generated
|
||||
// <id> tcc_arch_cntsel
|
||||
#ifndef CONF_TCC0_CNTSEL
|
||||
#define CONF_TCC0_CNTSEL 0
|
||||
#endif
|
||||
|
||||
// <o> Timer/Counter Event Input 0 Action
|
||||
// <0=>Event action disabled
|
||||
// <1=>Start restart or re-trigger on event
|
||||
// <2=>Count on event
|
||||
// <3=>Start on event
|
||||
// <4=>Increment on event
|
||||
// <5=>Count on active state of asynchronous event
|
||||
// <6=>Capture overflow times (Max value)
|
||||
// <7=>Non-recoverable fault
|
||||
// <i> These bits define the action the TCC performs on TCE0 event input 0
|
||||
// <id> tcc_arch_evact0
|
||||
#ifndef CONF_TCC0_EVACT0
|
||||
#define CONF_TCC0_EVACT0 0
|
||||
#endif
|
||||
|
||||
// <o> Timer/Counter Event Input 1 Action
|
||||
// <0=>Event action disabled
|
||||
// <1=>Re-trigger counter on event
|
||||
// <2=>Direction control
|
||||
// <3=>Stop counter on event
|
||||
// <4=>Decrement counter on event
|
||||
// <5=>Period capture value in CC0 register, pulse width capture value in CC1 register
|
||||
// <6=>Period capture value in CC1 register, pulse width capture value in CC0 register
|
||||
// <7=>Non-recoverable fault
|
||||
// <i> These bits define the action the TCC performs on TCE0 event input 0
|
||||
// <id> tcc_arch_evact1
|
||||
#ifndef CONF_TCC0_EVACT1
|
||||
#define CONF_TCC0_EVACT1 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
/* Commented intentionally. No pattern control for timers. */
|
||||
/*#define CONF_TCC0_PGE0 0
|
||||
#define CONF_TCC0_PGE1 0
|
||||
#define CONF_TCC0_PGE2 0
|
||||
#define CONF_TCC0_PGE3 0
|
||||
#define CONF_TCC0_PGE4 0
|
||||
#define CONF_TCC0_PGE5 0
|
||||
#define CONF_TCC0_PGE6 0
|
||||
#define CONF_TCC0_PGE7 0
|
||||
#define CONF_TCC0_PGV0 0
|
||||
#define CONF_TCC0_PGV1 0
|
||||
#define CONF_TCC0_PGV2 0
|
||||
#define CONF_TCC0_PGV3 0
|
||||
#define CONF_TCC0_PGV4 0
|
||||
#define CONF_TCC0_PGV5 0
|
||||
#define CONF_TCC0_PGV6 0
|
||||
#define CONF_TCC0_PGV7 0*/
|
||||
|
||||
/* Commented intentionally. No pattern waveform control for timers. */
|
||||
/*#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_MFRQ_Val
|
||||
#define CONF_TCC0_RAMP TCC_WAVE_RAMP_RAMP1_Val
|
||||
#define CONF_TCC0_CIPEREN 0
|
||||
#define CONF_TCC0_CICCEN0 0
|
||||
#define CONF_TCC0_CICCEN1 0
|
||||
#define CONF_TCC0_CICCEN2 0
|
||||
#define CONF_TCC0_CICCEN3 0
|
||||
#define CONF_TCC0_POL0 0
|
||||
#define CONF_TCC0_POL1 0
|
||||
#define CONF_TCC0_POL2 0
|
||||
#define CONF_TCC0_POL3 0
|
||||
#define CONF_TCC0_POL4 0
|
||||
#define CONF_TCC0_POL5 0
|
||||
#define CONF_TCC0_POL6 0
|
||||
#define CONF_TCC0_POL7 0
|
||||
#define CONF_TCC0_SWAP0 0
|
||||
#define CONF_TCC0_SWAP1 0
|
||||
#define CONF_TCC0_SWAP2 0
|
||||
#define CONF_TCC0_SWAP3 0*/
|
||||
|
||||
//<o> TCC0 Compare and Capture value 0 <0x00-0xFFFFFF>
|
||||
// <id> tcc_arch_cc0
|
||||
#ifndef CONF_TCC0_CC0
|
||||
#define CONF_TCC0_CC0 0x0
|
||||
#endif
|
||||
|
||||
//<o> TCC0 Compare and Capture value 1 <0x00-0xFFFFFF>
|
||||
// <id> tcc_arch_cc1
|
||||
#ifndef CONF_TCC0_CC1
|
||||
#define CONF_TCC0_CC1 0x0
|
||||
#endif
|
||||
|
||||
//<o> TCC0 Compare and Capture value 2 <0x00-0xFFFFFF>
|
||||
// <id> tcc_arch_cc2
|
||||
#ifndef CONF_TCC0_CC2
|
||||
#define CONF_TCC0_CC2 0x0
|
||||
#endif
|
||||
|
||||
//<o> TCC0 Compare and Capture value 3 <0x00-0xFFFFFF>
|
||||
// <id> tcc_arch_cc3
|
||||
#ifndef CONF_TCC0_CC3
|
||||
#define CONF_TCC0_CC3 0x0
|
||||
#endif
|
||||
|
||||
/* Commented intentionally. No pattern control for timers. */
|
||||
/*#define CONF_TCC0_PATTB_PGEB0 0
|
||||
#define CONF_TCC0_PATTB_PGEB1 0
|
||||
#define CONF_TCC0_PATTB_PGEB2 0
|
||||
#define CONF_TCC0_PATTB_PGEB3 0
|
||||
#define CONF_TCC0_PATTB_PGEB4 0
|
||||
#define CONF_TCC0_PATTB_PGEB5 0
|
||||
#define CONF_TCC0_PATTB_PGEB6 0
|
||||
#define CONF_TCC0_PATTB_PGEB7 0
|
||||
#define CONF_TCC0_PATTB_PGVB0 0
|
||||
#define CONF_TCC0_PATTB_PGVB1 0
|
||||
#define CONF_TCC0_PATTB_PGVB2 0
|
||||
#define CONF_TCC0_PATTB_PGVB3 0
|
||||
#define CONF_TCC0_PATTB_PGVB4 0
|
||||
#define CONF_TCC0_PATTB_PGVB5 0
|
||||
#define CONF_TCC0_PATTB_PGVB6 0
|
||||
#define CONF_TCC0_PATTB_PGVB7 0*/
|
||||
|
||||
/* Commented intentionally. No waveform control for timers. */
|
||||
/*#define CONF_TCC0_WAVEGENB TCC_WAVEB_WAVEGENB_MFRQ_Val
|
||||
#define CONF_TCC0_RAMPB TCC_WAVE_RAMP_RAMP1_Val
|
||||
#define CONF_TCC0_CIPERENB 0
|
||||
#define CONF_TCC0_CICCEN0B 0
|
||||
#define CONF_TCC0_CICCEN1B 0
|
||||
#define CONF_TCC0_CICCEN2B 0
|
||||
#define CONF_TCC0_CICCEN3B 0
|
||||
#define CONF_TCC0_POL0B 0
|
||||
#define CONF_TCC0_POL1B 0
|
||||
#define CONF_TCC0_POL2B 0
|
||||
#define CONF_TCC0_POL3B 0
|
||||
#define CONF_TCC0_POL4B 0
|
||||
#define CONF_TCC0_POL5B 0
|
||||
#define CONF_TCC0_POL6B 0
|
||||
#define CONF_TCC0_POL7B 0
|
||||
#define CONF_TCC0_SWAP0B 0
|
||||
#define CONF_TCC0_SWAP1B 0
|
||||
#define CONF_TCC0_SWAP2B 0
|
||||
#define CONF_TCC0_SWAP3B 0*/
|
||||
|
||||
/* Commented intentionally. No buffering for timers. */
|
||||
/*#define CONF_TCC0_PERB 0
|
||||
#define CONF_TCC0_CCB0 0
|
||||
#define CONF_TCC0_CCB1 0
|
||||
#define CONF_TCC0_CCB2 0
|
||||
#define CONF_TCC0_CCB3 0*/
|
||||
// </h>
|
||||
|
||||
#define CONF_TCC0_CTRLA \
|
||||
TCC_CTRLA_PRESCALER(CONF_TCC0_PRESCALER) | (CONF_TCC0_RUNSTDBY << TCC_CTRLA_RUNSTDBY_Pos) \
|
||||
| TCC_CTRLA_PRESCSYNC(CONF_TCC0_PRESCSYNC) | (CONF_TCC0_CPTEN0 << TCC_CTRLA_CPTEN0_Pos) \
|
||||
| (CONF_TCC0_CPTEN1 << TCC_CTRLA_CPTEN1_Pos) | (CONF_TCC0_CPTEN2 << TCC_CTRLA_CPTEN2_Pos) \
|
||||
| (CONF_TCC0_CPTEN3 << TCC_CTRLA_CPTEN3_Pos) | (CONF_TCC0_ALOCK << TCC_CTRLA_ALOCK_Pos)
|
||||
#define CONF_TCC0_CTRLB (CONF_TCC0_LUPD << TCC_CTRLBSET_LUPD_Pos)
|
||||
#define CONF_TCC0_DBGCTRL (CONF_TCC0_DBGRUN << TCC_DBGCTRL_DBGRUN_Pos)
|
||||
#define CONF_TCC0_EVCTRL \
|
||||
TCC_EVCTRL_CNTSEL(CONF_TCC0_CNTSEL) | (CONF_TCC0_OVFEO << TCC_EVCTRL_OVFEO_Pos) \
|
||||
| (CONF_TCC0_TRGEO << TCC_EVCTRL_TRGEO_Pos) | (CONF_TCC0_CNTEO << TCC_EVCTRL_CNTEO_Pos) \
|
||||
| (CONF_TCC0_MCEO0 << TCC_EVCTRL_MCEO0_Pos) | (CONF_TCC0_MCEI0 << TCC_EVCTRL_MCEI0_Pos) \
|
||||
| (CONF_TCC0_MCEO1 << TCC_EVCTRL_MCEO1_Pos) | (CONF_TCC0_MCEI1 << TCC_EVCTRL_MCEI1_Pos) \
|
||||
| (CONF_TCC0_MCEO2 << TCC_EVCTRL_MCEO2_Pos) | (CONF_TCC0_MCEI2 << TCC_EVCTRL_MCEI2_Pos) \
|
||||
| (CONF_TCC0_MCEO3 << TCC_EVCTRL_MCEO3_Pos) | (CONF_TCC0_MCEI3 << TCC_EVCTRL_MCEI3_Pos) \
|
||||
| (CONF_TCC0_TCEI0 << TCC_EVCTRL_TCEI0_Pos) | (CONF_TCC0_TCEI1 << TCC_EVCTRL_TCEI1_Pos) \
|
||||
| (CONF_TCC0_TCINV0 << TCC_EVCTRL_TCINV0_Pos) | (CONF_TCC0_TCINV1 << TCC_EVCTRL_TCINV1_Pos) \
|
||||
| TCC_EVCTRL_EVACT1(CONF_TCC0_EVACT1) | TCC_EVCTRL_EVACT0(CONF_TCC0_EVACT0)
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_TCC_CONFIG_H
|
||||
214
Smol Watch Project/My Project/Config/peripheral_clk_config.h
Normal file
214
Smol Watch Project/My Project/Config/peripheral_clk_config.h
Normal file
@@ -0,0 +1,214 @@
|
||||
/* Auto-generated config file peripheral_clk_config.h */
|
||||
#ifndef PERIPHERAL_CLK_CONFIG_H
|
||||
#define PERIPHERAL_CLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <y> ADC Clock Source
|
||||
// <id> adc_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <i> Select the clock source for ADC.
|
||||
#ifndef CONF_GCLK_ADC_SRC
|
||||
#define CONF_GCLK_ADC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_ADC_FREQUENCY
|
||||
* \brief ADC's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_ADC_FREQUENCY
|
||||
#define CONF_GCLK_ADC_FREQUENCY 4000000
|
||||
#endif
|
||||
|
||||
// <y> EIC Clock Source
|
||||
// <id> eic_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <i> Select the clock source for EIC.
|
||||
#ifndef CONF_GCLK_EIC_SRC
|
||||
#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EIC_FREQUENCY
|
||||
* \brief EIC's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_EIC_FREQUENCY
|
||||
#define CONF_GCLK_EIC_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_CPU_FREQUENCY
|
||||
* \brief CPU's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_CPU_FREQUENCY
|
||||
#define CONF_CPU_FREQUENCY 4000000
|
||||
#endif
|
||||
|
||||
// <y> RTC Clock Source
|
||||
// <id> rtc_clk_selection
|
||||
// <RTC_CLOCK_SOURCE"> RTC source
|
||||
// <i> Select the clock source for RTC.
|
||||
#ifndef CONF_GCLK_RTC_SRC
|
||||
#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_RTC_FREQUENCY
|
||||
* \brief RTC's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_RTC_FREQUENCY
|
||||
#define CONF_GCLK_RTC_FREQUENCY 1024
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM1_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
|
||||
* \brief SERCOM1's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 4000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
|
||||
* \brief SERCOM1's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
// <y> TC Clock Source
|
||||
// <id> tc_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <i> Select the clock source for TC.
|
||||
#ifndef CONF_GCLK_TC3_SRC
|
||||
#define CONF_GCLK_TC3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_TC3_FREQUENCY
|
||||
* \brief TC3's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_TC3_FREQUENCY
|
||||
#define CONF_GCLK_TC3_FREQUENCY 4000000
|
||||
#endif
|
||||
|
||||
// <y> TCC Clock Source
|
||||
// <id> tcc_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <i> Select the clock source for TCC.
|
||||
#ifndef CONF_GCLK_TCC0_SRC
|
||||
#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_TCC0_FREQUENCY
|
||||
* \brief TCC0's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_TCC0_FREQUENCY
|
||||
#define CONF_GCLK_TCC0_FREQUENCY 4000000
|
||||
#endif
|
||||
|
||||
#include <hpl_osc32kctrl_config.h>
|
||||
|
||||
// <y> SLCD Clock Source
|
||||
// <id> slcd_clk_selection
|
||||
// <SLCD_CLOCK_SOURCE"> SLCD source
|
||||
// <i> Select the clock source for SLCD.
|
||||
#ifndef CONF_GCLK_SLCD_SRC
|
||||
#define CONF_GCLK_SLCD_SRC SLCD_CLOCK_SOURCE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SLCD_FREQUENCY
|
||||
* \brief SLCD's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SLCD_FREQUENCY
|
||||
#define CONF_GCLK_SLCD_FREQUENCY 32768
|
||||
#endif
|
||||
|
||||
#ifndef SLCD_FRAME_FREQUENCY
|
||||
#define SLCD_FRAME_FREQUENCY \
|
||||
(CONF_GCLK_SLCD_FREQUENCY \
|
||||
/ (((CONF_SLCD_PRESC + 1) * 16) * (CONF_SLCD_CKDIV + 1) \
|
||||
* ((CONF_SLCD_COM_NUM == 4) ? 6 : ((CONF_SLCD_COM_NUM == 5) ? 8 : (CONF_SLCD_COM_NUM + 1)))))
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // PERIPHERAL_CLK_CONFIG_H
|
||||
@@ -0,0 +1,9 @@
|
||||
/* Auto-generated config file sleep_manager_config.h */
|
||||
#ifndef SLEEP_MANAGER_CONFIG_H
|
||||
#define SLEEP_MANAGER_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // SLEEP_MANAGER_CONFIG_H
|
||||
Reference in New Issue
Block a user